diff --git a/Makefile b/Makefile
index 68fcd3502a0b27e33c88ba5b5e6e9514d35d1b70..cf6ddf16ce3012df51785f10ca7e5db0cad37427 100644
--- a/Makefile
+++ b/Makefile
@@ -69,7 +69,8 @@ EXPORTS = ${EXP_HDR}.EnvNumbers \
${EXP_HDR}.OSEntries \
${C_EXP_HDR}.RISCOS \
${C_EXP_HDR}.HALEntries \
- ${C_EXP_HDR}.HALDevice
+ ${C_EXP_HDR}.HALDevice \
+ ${C_EXP_HDR}.OSEntries
#
# Generic rules:
@@ -186,6 +187,10 @@ ${C_EXP_HDR}.HALDevice: o.Global.h.HALDevice h.HALDevice
${CP} h.HALDevice $@ ${CPFLAGS}
print o.Global.h.HALDevice { >> $@ }
+${C_EXP_HDR}.OSEntries: hdr.OSEntries
+ ${MKDIR} ${C_EXP_HDR}
+ perl Build:Hdr2H hdr.OSEntries $@
+
o.Global.h.HALDevice: hdr.HALDevice
${MKDIR} o.Global.h
dir o
diff --git a/VersionASM b/VersionASM
index 6c3f46c37546367beea14121a80a3f6f316abe12..678be64696ae7820e8b740bf9ba48b060b8259eb 100644
--- a/VersionASM
+++ b/VersionASM
@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
-Module_MinorVersion SETS "4.79.2.98.2.36"
-Module_Date SETS "19 Mar 2011"
-Module_ApplicationDate SETS "19-Mar-11"
+Module_MinorVersion SETS "4.79.2.98.2.37"
+Module_Date SETS "22 May 2011"
+Module_ApplicationDate SETS "22-May-11"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
-Module_FullVersion SETS "5.35 (4.79.2.98.2.36)"
-Module_HelpVersion SETS "5.35 (19 Mar 2011) 4.79.2.98.2.36"
+Module_FullVersion SETS "5.35 (4.79.2.98.2.37)"
+Module_HelpVersion SETS "5.35 (22 May 2011) 4.79.2.98.2.37"
END
diff --git a/VersionNum b/VersionNum
index e5505161b5340e0428af66e67d40fa2bd065de58..ec4317c99f9461f12fab5444e4e288c1f2b33f92 100644
--- a/VersionNum
+++ b/VersionNum
@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
-#define Module_MinorVersion_CMHG 4.79.2.98.2.36
-#define Module_Date_CMHG 19 Mar 2011
+#define Module_MinorVersion_CMHG 4.79.2.98.2.37
+#define Module_Date_CMHG 22 May 2011
#define Module_MajorVersion "5.35"
#define Module_Version 535
-#define Module_MinorVersion "4.79.2.98.2.36"
-#define Module_Date "19 Mar 2011"
+#define Module_MinorVersion "4.79.2.98.2.37"
+#define Module_Date "22 May 2011"
-#define Module_ApplicationDate "19-Mar-11"
+#define Module_ApplicationDate "22-May-11"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
-#define Module_FullVersion "5.35 (4.79.2.98.2.36)"
-#define Module_HelpVersion "5.35 (19 Mar 2011) 4.79.2.98.2.36"
+#define Module_FullVersion "5.35 (4.79.2.98.2.37)"
+#define Module_HelpVersion "5.35 (22 May 2011) 4.79.2.98.2.37"
#define Module_LibraryVersionInfo "5:35"
diff --git a/s/GetAll b/s/GetAll
index adc4f187fc402b4487499fdf6b8cf50ef997e8d1..37dad9a308d8f827b2528268feacb1b1a22954d3 100644
--- a/s/GetAll
+++ b/s/GetAll
@@ -19,6 +19,7 @@
GET Hdr:System
GET Hdr:CPU.Arch
GET Hdr:Machine.<Machine>
+ GET Hdr:HALSize.<HALSize>
GET Hdr:ImageSize.<ImageSize>
GET Hdr:UserIF.<UserIF>
$GetCPU
diff --git a/s/HAL b/s/HAL
index 30c52150e96afac86af0480bcbf0b79700b83646..3b79e5fc6de09c42c4ba760e6940edbbfed440a4 100644
--- a/s/HAL
+++ b/s/HAL
@@ -2384,8 +2384,11 @@ DebugHALPrint
Reset_IRQ_Handler
SUB lr, lr, #4
Push "a1-a4,v1-v2,sb,ip,lr"
- MRS lr, SPSR
- Push "lr"
+ MRS a1, SPSR
+ MRS a2, CPSR
+ ORR a3, a2, #SVC32_mode
+ MSR CPSR_c, a3
+ Push "a1-a2,lr"
MOV v2, #0
AddressHAL v2
MOV v1, #IICBus_Base
@@ -2402,8 +2405,9 @@ Reset_IRQ_Handler
LDRB a1, [a1, #KbdScanActive]
TEQ a1, #0
CallHAL HAL_KbdScanInterrupt,NE
- Pull "lr"
- MSR SPSR_cxsf, lr
+ Pull "a1-a2,lr"
+ MSR CPSR_c, a2
+ MSR SPSR_cxsf, a1
Pull "a1-a4,v1-v2,sb,ip,pc",,^
END
diff --git a/s/Kernel b/s/Kernel
index 6cd8d5ebb73dac11416b582445fb5dd6d50d5fb5..76124b0af5ebf0c97ab61bbb3fd87cc9a3688483 100644
--- a/s/Kernel
+++ b/s/Kernel
@@ -320,7 +320,7 @@ CBack_VectorReq * 4
OPT 4
[ HAL
- ORG ROM + 64*1024
+ ORG ROM + OSROM_HALSize
|
ORG ROM
]
@@ -337,7 +337,7 @@ KernelBase
; *****************************************************************************
[ HAL
-; ORG ROM + 64*1024
+; ORG ROM + OSROM_HALSize
|
; ORG ROM
]
@@ -354,7 +354,7 @@ DoTestThings SETS ""
RISCOS_Header
= "OSIm"
DCD 0
- DCD OSROM_ImageSize*1024 - 64*1024
+ DCD OSROM_ImageSize*1024 - OSROM_HALSize
DCD RISCOS_Entries - RISCOS_Header
DCD (RISCOS_Entries_End - RISCOS_Entries) / 4
diff --git a/s/VMSAv6 b/s/VMSAv6
index dbf908433bef8554f978d300b7631499ab8315e0..5ce61fc2002a8cf4ab9768022462e76dee2f4939 100644
--- a/s/VMSAv6
+++ b/s/VMSAv6
@@ -29,29 +29,6 @@ DebugAborts SETL {FALSE}
ASSERT :LNOT: ECC
ASSERT :LNOT: ARM6support
-; Fixed page allocation is as follows
-
- ^ 0
-; Undefined stack memory (size 8K) starts immediately after end of L2PT (which is variable size)
-; Soft CAM map (variable size) starts immediately after end of UndStack
-
-StaticPagesSize * @
-
-; Logical addresses are as follows
-
-FixedAreasL2Size * 96*1024 ; amount of L2 to cover fixed areas, excluding free pool
-
-UndStackSoftCamChunk * &01E00000
-UndStackSize * 8*1024
-CamEntriesForVicky * UndStackSoftCamChunk + UndStackSize
-
-
-; - address for virtual area for StrongARM data cache cleaning (32k, for two 16k areas)
-; - the two areas are used in strict rotation for each full clean, so that we can do a full
-; clean (and not flush) with interrupts on
-; - the address must be aligned such that EOR with 16*1024 flipflops between the two addresses
-ARMA_Cleaners_address * &01F10000
-
OneMByte EQU (1024*1024)
SixteenMByte EQU (1024*1024 * 16)