GitLab

Detail:
  Rounding the pixel clock to 0.25MHz was not correctly performed due to clock step division being outside the floor() function, so all times came out in steps of 1MHz.
  In GTF timing with interlacing v_lines_rqd specifies ROUND(v_lines/2,0) rather than ROUNDDOWN(v_lines/2,0).
  Abandon GTF calculations early if they result in a -ve duty cycle.
  Update margins to 1.8% from standard.
Admin:
  Mode with non-multiple-of-1MHz clock tested, now matches VESA CVT spreadsheet.
  GTF change not tested since int_rqd = 0 the code wasn't called.
  Margin% change not tested since margins_rqd = 0 the code wasn't called.
  Submission for the EDID bounty.

Version 0.54. Tagged as 'ScrModes-0_54'