Fix bug in CVT-RB timing calculation, add GTF range check

Detail:
  Rounding the pixel clock to 0.25MHz was not correctly performed due to clock step division being outside the floor() function, so all times came out in steps of 1MHz.
  In GTF timing with interlacing v_lines_rqd specifies ROUND(v_lines/2,0) rather than ROUNDDOWN(v_lines/2,0).
  Abandon GTF calculations early if they result in a -ve duty cycle.
  Update margins to 1.8% from standard.
Admin:
  Mode with non-multiple-of-1MHz clock tested, now matches VESA CVT spreadsheet.
  GTF change not tested since int_rqd = 0 the code wasn't called.
  Margin% change not tested since margins_rqd = 0 the code wasn't called.
  Submission for the EDID bounty.

Version 0.54. Tagged as 'ScrModes-0_54'

VersionNum

-/* (0.53)
+/* (0.54)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        0.53
+#define Module_MajorVersion_CMHG        0.54
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                10 Jan 2016
+#define Module_Date_CMHG                14 May 2016
 
-#define Module_MajorVersion             "0.53"
-#define Module_Version                  53
+#define Module_MajorVersion             "0.54"
+#define Module_Version                  54
 #define Module_MinorVersion             ""
-#define Module_Date                     "10 Jan 2016"
+#define Module_Date                     "14 May 2016"
 
-#define Module_ApplicationDate          "10-Jan-16"
+#define Module_ApplicationDate          "14-May-16"
 
 #define Module_ComponentName            "ScrModes"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Video/UserI/ScrModes"
 
-#define Module_FullVersion              "0.53"
-#define Module_HelpVersion              "0.53 (10 Jan 2016)"
-#define Module_LibraryVersionInfo       "0:53"
+#define Module_FullVersion              "0.54"
+#define Module_HelpVersion              "0.54 (14 May 2016)"
+#define Module_LibraryVersionInfo       "0:54"

c/edidsupport

@@ -201,7 +201,7 @@ static void get_dtd_ascii(EDIDBlockRef edidblockref, int block_number, char *dat
 static void generate_mode_using_gtf(double h_pixels, double v_lines, double ip_freq_rqd, ModeDescriptionRef mode_desc, MonitorDescriptionRef monitor)
 {
     const int margins_rqd = 0; /* Set to 1 if margins are wanted. */
-    const double margin_per = 0; /* Percentage size of margin (0 to 100) if reqd */
+    const double margin_per = 1.8; /* Percentage size of margin (0 to 100) if reqd */
     double v_lines_rnd = 0; /* Number of desired visible lines rounded down to */
                             /* The nearest character cell */
     double v_sync_rqd = 3; /* The width of the v sync in lines */
@@ -232,7 +232,7 @@ static void generate_mode_using_gtf(double h_pixels, double v_lines, double ip_f
 
     if (int_rqd == 1)
     {
-        v_lines_rnd = floor(v_lines / 2);
+        v_lines_rnd = round(v_lines / 2);
         v_field_rate_reqd = ip_freq_rqd * 2;
         interlace = 0.5;
     }
@@ -301,6 +301,13 @@ static void generate_mode_using_gtf(double h_pixels, double v_lines, double ip_f
 
     /* Find the ideal blanking duty cycle from the blanking duty cycle equation */
     double ideal_duty_cycle = C - (M * h_period / 1000);
+    if (ideal_duty_cycle < 0)
+    {
+        IFDEBUG printf("Error - negative duty cycle\n");
+        /* If this happens we should just ignore the mode */
+        free(mode_desc);
+        return;
+    }
 
     /* Find the number of pixels in the blanking time to the nearest double */
     /* character cell */
@@ -359,7 +366,7 @@ static void generate_mode_using_gtf(double h_pixels, double v_lines, double ip_f
     mode_desc->definition.vpar[FR_BPCH] = (int) v_back_porch;
     mode_desc->definition.vpar[FR_BDR1] = (int) top_margin;
 
-    if (int_rqd)
+    if (int_rqd == 1)
     {
         mode_desc->definition.vpar[FR_DISP] = (int) v_lines / 2;
     }
@@ -398,7 +405,7 @@ static void generate_mode_using_cvt_rb(double h_pixels, double v_lines, double i
 {
     const int int_rqd = 0; /* int_rqd specifies whether the mode should be interlaced. Most modes used are not. */
     const int margins_rqd = 0; /* Set to 1 if margins are wanted. */
-    const double margin_per = 0; /* Percentage size of margin(0 to 100) if reqd */
+    const double margin_per = 1.8; /* Percentage size of margin(0 to 100) if reqd */
     double cell_gran_rnd = 8; /* Character cell width in pixels. May be able to confirm this value in hardware but at present hardcode this to 8 (usual value), */
     double v_field_rate_reqd = 0; /* The actual vertical field rate after interlacing is taking into consideration */
     double v_lines_rnd = 0; /* Number of desired visible lines rounded down to the nearest character cell */
@@ -629,8 +636,8 @@ static void generate_mode_using_cvt_rb(double h_pixels, double v_lines, double i
 
         const double clock_step = 0.25;
 
-        /* Calculate the pixel clock frequency to nearest 0.125MHz */
-        act_pixel_freq = clock_step * floor(v_field_rate_reqd * total_v_lines * total_pixels / 1000000) / clock_step;
+        /* Calculate the pixel clock frequency to nearest 0.25MHz */
+        act_pixel_freq = clock_step * floor((v_field_rate_reqd * total_v_lines * total_pixels / 1000000) / clock_step);
 
         /* Find the number of lines in V_sync + back porch: */
         v_back_porch = (int) (act_vbi_lines - v_front_porch - v_sync_rnd);
@@ -652,7 +659,7 @@ static void generate_mode_using_cvt_rb(double h_pixels, double v_lines, double i
     mode_desc->definition.vpar[FR_SYNC] = (int) v_sync_rnd;
     mode_desc->definition.vpar[FR_BPCH] = v_back_porch;
     mode_desc->definition.vpar[FR_BDR1] = (int) top_margin;
-    if (int_rqd)
+    if (int_rqd == 1)
     {
         mode_desc->definition.vpar[FR_DISP] = (int) v_lines / 2;
     }