BlackLog

@@ -19,6 +19,18 @@ Debugger RM.
 
 ***************************************************************************
 
+; 1.18  SKS     Fixed disassembly of #xx,yy operands
+; 1.19  SKS     Fixed disassembly of LSR #32, ASR #32
+;               Comment where LDR pc relative comes from
+; 1.20  SKS     Fixed fp/coproc disassembly, memoryi/memorya parameters
+; 1.21  SKS     Fixed *debug response wrt ESCape
+; 1.22  SKS     Fixed memory wrt wrapping at 64M
+
+; ---- Released for Arthur 2.00 ----
+
+; 1.22  TMD 22-Nov-89    Fixed source to assemble again with new headers,
+;                        and with new AAsm which objects to DCD rel.sym.
+;                        (shouldn't affect object file)
 
 Change Log:
 ===========
@@ -167,6 +179,15 @@ Fixed access to banked register after LDM forcing user bank.
 Version: 1.37 Mon 02-Dec-91        Alan Glover                   
 
 Fix Bug RP-0512 - give the Debugger some address validation at last!
+;                        Add address validation as below
+;                        &0000000-&1ffffff - Use OS_ValidateAddress
+;                        &2000000-&2ffffff - No checks (always present)
+;                        &3000000-&33fffff - No access (I/O areas)
+;                        &3400000-&3ffffff - Read access only (ROMs)
+;                                              (writes=VIDC or MEMC)
+;                        MEMORYA will trap interactive mode going into
+;                        a read-only/no access area too.
+
 ---------------------------------------------------------------------------
 
 Version: 1.38 Fri 24-Jan-92        Alan Glover                   
@@ -178,6 +199,8 @@ Version: 1.39 Mon 13-Apr-92        Alan Glover
 
 Fix Bug RP-1082 - Revert RP-0512 fix.
 
+; ---- Released for RISC OS 3.10 ----
+
 ---------------------------------------------------------------------------
 
 Version: 1.40 Tue 06-Jul-93        Tim Dobson                    
@@ -210,6 +233,9 @@ Version: 1.44 Thu 03-Feb-94        Alan Glover
 Add a flag to allow a non-international help & syntax version to be built.
 Add new ARM6/ARM7DM instructions. Tighten up checking on undefined
 instructions.
+MRS, MSR, MULL, MLAL and check conformance with FPA10 spec. Tighten up
+tests for MUL/MULL/SWP - now insist b7:b4=2_1001
+
 
 ***************************************************************************
                       MEDUSA - RISC OS 3.50 build
@@ -251,3 +277,42 @@ Version: 1.45 Fri 28-Oct-94        Steve Cormie
 
 * Added directed comments to Messages file for message tokenisation.
 * Moved command help/syntax from Global.Messages to Messages file.
+
+; ---- Released for RISC OS 3.60 ----
+
+; 1.46  WT  07-Feb-96    Made StrongARM compatible (breakpoint code breaks IDcache)
+; 1.48  KJB 04-Jun-96    Added ARMv4 instructions (BX, LDR[H|SH|SB], STRH)
+;                        SWP wasn't being disassembled
+;                        CP15 comments amended to ARMv4
+;                        ARM3 warning removed from SWP (after all, MRS,
+;                          MULL etc don't have warnings!)
+
+; ---- Released for RISC OS 3.70 ----
+
+; 1.49  KJB 07-Oct-96    Operation code of MRC, MCR was shown times 2.
+;                        FLT was showing wrong dest reg, with registers
+;                          shown in wrong order.
+;                        WFC etc were showing precision.
+;                        Unknown FP opcodes now shown as normal coprocessor
+;                          operations.
+;                        LDC/STC (and FP derivatives) didn't detect
+;                          post-indexing with no writeback. Now reported as
+;                          undefined instructions.
+;                        UMULLEQS no longer pushes registers into the
+;                          comment field.
+;                        MSR/MRS now specified as described in ARM
+;                          Architecture Reference 4.
+; 1.50  KJB 10-Oct-96    Lots of warnings added.
+;                        More FP opcodes tightened up.
+;                        PC-relative load/store with writeback no longer
+;                         shown as simple ADR.
+;                        Thumb disassembly added.
+; 1.51  KJB 29-Oct-96    Bugs introduced by 1.49 and 1.50 fixed.
+;                        Warnings added to the LDRH family to match LDC and LDR.
+;                        Warning about StrongARM STM^ bug added.
+;                        Source code tidied up and simplified with macros.
+; 1.52  KJB 06-Nov-96    More bug fixes.
+;                        StrongARM warning revised following Digital guidelines.
+; 1.53  KJB 11-Nov-96    SWI called checkreg for no apparent reason.
+;                        Stopped Addr26 screwing up Thumb disassembly.
+;                        Set Addr26 to True.

HelpSrc

@@ -101,6 +101,14 @@ ShowVFPRegs_Help
 ShowVFPRegs_Syntax
         =       "Syntax: *",TokenEscapeChar,Token0
         =       " [A <addr>|C|E|]", 0
+
+Where_Help
+        =       "*",TokenEscapeChar,Token0
+        =       " describes the region in memory of an address or register."
+        =       13
+Where_Syntax
+        =       "Syntax: *",TokenEscapeChar,Token0
+        =       " [<addr|reg>]", 0
  |
 BreakClr_Help           DCB     "HDBGBCL", 0
 BreakClr_Syntax         DCB     "SDBGBCL", 0
@@ -137,6 +145,9 @@ ShowFPRegs_Syntax       DCB     "SDBGSFR", 0
 
 ShowVFPRegs_Help        DCB     "HDBGSVR", 0
 ShowVFPRegs_Syntax      DCB     "SDBGSVR", 0
+
+Where_Help              DCB     "HDBGWHR", 0
+Where_Syntax            DCB     "SDBGWHR", 0
  ]
 
         ALIGN

Makefile

@@ -31,7 +31,7 @@ HELPSRC       = HelpSrc
 TOKENSOURCE   = TokHelpSrc
 TOKHELPSRC    = ${TOKENSOURCE}
 ASMHDRS       = Debugger
-OBJS          = Debugger util dis2_vfp support
+OBJS          = Debugger util dis2_vfp support exc
 HDRS          =
 CMHGFILE      =
 
@@ -81,16 +81,19 @@ ACTIONS_ARM = actions/common \
               actions/ARMv7 \
               actions/ARMv7_ASIMD \
               actions/ARMv7_VFP \
+              actions/ARMv8_AArch32 \
+              actions/ARMv8FP_AArch32 \
               actions/FPA \
               actions/XScale_DSP
 
 ACTIONS_VFP = actions/common \
               actions/ARMv7_ASIMD \
-              actions/ARMv7_VFP
+              actions/ARMv7_VFP \
+              actions/ARMv8FP_AArch32
 
 ENCODINGS = Build:decgen.encodings.ARMv7 \
-            Build:decgen.encodings.ARMv7_ASIMD \
-            Build:decgen.encodings.ARMv7_VFP \
+            Build:decgen.encodings.ARMv8FP_AArch32 \
+            Build:decgen.encodings.ARMv8_AArch32 \
             Build:decgen.encodings.FPA \
             Build:decgen.encodings.XScale_DSP
 
@@ -116,9 +119,15 @@ dis2_vfp.o: dis2_vfp.c
 dis2_vfp.oz: dis2_vfp.c
 	${CC} ${CFLAGS} ${C_MODULE} -o $@ dis2_vfp.c
 
+excdump.h: hdr.ExcDump
+	${HDR2H} hdr.ExcDump $@
+
+exc.c: excdump.h
+
 clean::
 	${RM} c.dis2_vfp
 	${RM} c.dis2_arm
+	${RM} h.excdump
 	${RM} ${TOKENSOURCE}
 
 # Stuff from AAsmModule that's missing from CModule

Test/V6V7tests

@@ -16,7 +16,6 @@
         GET     Hdr:ListOpts
         GET     Hdr:Macros
         GET     Hdr:System
-        GET     Hdr:Services
 
         AREA    test,CODE,READONLY
 
@@ -107,7 +106,7 @@
         ; Misc instructions
         CPSID   i
         CPSIE   f
-        CPSID   aif,#12
+        CPSID   aif,#SVC32_mode
         CPS     12
         DCI     &F100000C               ; Mode != 0, no mode change bit, unpredictable
 
@@ -243,5 +242,40 @@
         UXTAH   r0, r1, r2
         UXTB16  r0, PC                  ; Not PC
         UXTAB16CC r0, r1, r2, ROR #24
+
+        ; V7 multi processor additions
+        PLDW    [r5, r6]
+
+        ; V7 virtualisation additions
+        MSR     ELR_hyp, r5
+        MSR     R8_fiq, r5
+        MRS     r5, SP_irq
+        MRS     r5, LR_mon
+        ERETNE
+        HVC     &1234
         
+        ; V8 additions
+        DCI     &E1043045               ; CRC32B  r3, r4, r5
+        DCI     &11043245               ; CRC32CBNE r3, r4, r5
+        DCI     &11243245               ; CRC32CHNE r3, r4, r5
+        DCI     &E14F3245               ; CRC32CW r3, pc, r5
+
+        DMB     NSHLD
+        DSB     LD
+
+        HLT     &DEAD
+        SEVL
+
+        LDA     r0, [r1]
+        LDACCB  r0, [r1]
+        LDACCH  r0, [pc]
+        STL     r2, [r2]
+
+        LDAEXNE r0, [r1]
+        LDAEXD  r0, r1, [r2]
+        LDAEXNEB r0, [pc]
+        LDAEXH  r0, [r1]
+        STLEX   r0, r1, [r2]
+        STLEXNE r0, pc, [r2]
+
         END

Test/c/testbed

@@ -23,8 +23,29 @@
 /* Standalone testbed app for comparing standalone dis2 builds against the
    Debugger module and decaof */
 
+void xsystem(const char *cmd)
+{
+//	printf("*%s\n",cmd);
+	if (system(cmd))
+	{
+		fprintf(stderr,"'%s' failed!\n",cmd);
+		exit(257);
+	}
+}
+
+FILE *xfopen(const char *file,const char *mode)
+{
+	FILE *f = fopen(file,mode);
+	if(!f)
+	{
+		fprintf(stderr,"Couldn't open '%s'\n",file);
+		exit(257);
+	}
+	return f;
+}
+
 #define DEBUGGER
-//#define DECAOF
+#define DECAOF
 
 #define MYDIFF
 
@@ -33,9 +54,9 @@ void postprocess(char *folder,char *in,char *out)
 {
 	char buf[4096];
 	sprintf(buf,"%s.%s",folder,in);
-	FILE *fin = fopen(buf,"r");
+	FILE *fin = xfopen(buf,"r");
 	sprintf(buf,"%s.%s",folder,out);
-	FILE *fout = fopen(buf,"w");
+	FILE *fout = xfopen(buf,"w");
 	setvbuf(fin,NULL,_IOFBF,65536);
 	setvbuf(fout,NULL,_IOFBF,65536);
 	while(!feof(fin) && fgets(buf,4096,fin))
@@ -86,11 +107,11 @@ int diff_decaof(char *folder,char *one,char *two,char *out)
 	FILE *fin1,*fin2;
 	FILE *fout;
 	sprintf(buf1,"%s.%s",folder,one);
-	fin1 = fopen(buf1,"r");
+	fin1 = xfopen(buf1,"r");
 	sprintf(buf1,"%s.%s",folder,two);
-	fin2 = fopen(buf1,"r");
+	fin2 = xfopen(buf1,"r");
 	sprintf(buf1,"%s.%s",folder,out);
-	fout = fopen(buf1,"w");
+	fout = xfopen(buf1,"w");
 	setvbuf(fin1,NULL,_IOFBF,65536);
 	setvbuf(fin2,NULL,_IOFBF,65536);
 	setvbuf(fout,NULL,_IOFBF,65536);
@@ -139,6 +160,18 @@ int diff_decaof(char *folder,char *one,char *two,char *out)
 		/* Skip any that decgen thinks are nonstandard */
 		if(strstr(c2,"Nonstandard encoding"))
 			continue;
+		/* Skip any that decgen thinks are undefined */
+		if(strstr(c2,"Undefined instruction"))
+			continue;
+		/* decaof & dis2 agree on how unknown VMRS/VMSR registers should be shown */
+		if(strstr(c2,"Bad VFP/NEON special register"))
+			continue;
+		/* decaof doesn't recognise MVFR2 */
+		if(strstr(c2,"MVFR2"))
+			continue;
+		/* decaof & dis2 agree on how VTBL, VTBX ranges should be represented */
+		if(strstr(c2,"VTB"))
+			continue;
 		/* Compare RHS */
 		int s1 = -1;
 		int s2 = -1;
@@ -189,11 +222,11 @@ int diff_decaof(char *folder,char *one,char *two,char *out)
 			else
 			{
 				s1 = S_ID;
-				if(isalnum(*c1))
+				if(isalnum(*c1) || (*c1 == '.'))
 				{
 					do {
 						n1++;
-					} while(isalnum(c1[n1]));
+					} while(isalnum(c1[n1]) || (c1[n1] == '.'));
 				}
 				else
 					n1 = 1;
@@ -240,11 +273,11 @@ int diff_decaof(char *folder,char *one,char *two,char *out)
 			else
 			{
 				s2 = S_ID;
-				if(isalnum(*c2))
+				if(isalnum(*c2) || (*c2 == '.'))
 				{
 					do {
 						n2++;
-					} while(isalnum(c2[n2]));
+					} while(isalnum(c2[n2]) || (c2[n2] == '.'));
 				}
 				else
 				{
@@ -270,10 +303,21 @@ int diff_decaof(char *folder,char *one,char *two,char *out)
 			{
 				if((n1 != n2) || xstrnicmp(c1,c2,(size_t) n1))
 				{
+					/* dis2 currently uses 'CP' for coprocessor numbers, even in objasm mode */
+					if ((n2 == n1+1) && (c2[0] == 'C') && !xstrnicmp(c1,c2+1,(size_t) n1))
+					{
+						goto ok;
+					}
+					/* for things like VRINTA.F32.F32, decaof only outputs one .F32, while dis2 outputs two */
+					if ((n2 == n1 + 4) && (n1 > 4) && !xstrnicmp(c1,c2,(size_t) n1) && !xstrnicmp(c2+n1-4,c2+n1,4))
+					{
+						goto ok;
+					}
 					fprintf(fout,"ID mismatch:\n%s\n%s\n",b1,b2);
 					ret = 1;
 					break;
 				}
+ok:
 				c1 += n1;
 				c2 += n2;
 			}
@@ -297,11 +341,11 @@ int diff_debugger(char *folder,char *one,char *two,char *out)
 	char buf1[4096],buf2[4096];
 	FILE *fin1,*fin2,*fout;
 	sprintf(buf1,"%s.%s",folder,one);
-	fin1 = fopen(buf1,"r");
+	fin1 = xfopen(buf1,"r");
 	sprintf(buf1,"%s.%s",folder,two);
-	fin2 = fopen(buf1,"r");
+	fin2 = xfopen(buf1,"r");
 	sprintf(buf1,"%s.%s",folder,out);
-	fout = fopen(buf1,"w");
+	fout = xfopen(buf1,"w");
 	setvbuf(fin1,NULL,_IOFBF,65536);
 	setvbuf(fin2,NULL,_IOFBF,65536);
 	setvbuf(fout,NULL,_IOFBF,65536);
@@ -423,61 +467,33 @@ void process(char *rawfile,char *folder,unsigned int *raw,unsigned int count)
 	int ret = 0;
 #ifdef DECAOF
 	sprintf(buf,"binaof %s %s.aof foo foo -C",rawfile,folder);
-	if(system(buf))
-	{
-		fprintf(stderr,"binaof failed!\n");
-		exit(EXIT_FAILURE);
-	}
+	xsystem(buf);
 #endif
 	printf("Disassembling\n");
 #ifdef DEBUGGER
 	sprintf(buf,"dis2 %s 0x%08x -debugger > %s.dis2_debugger",rawfile,(unsigned int) raw,folder);
-	if(system(buf))
-	{
-		fprintf(stderr,"dis2 failed!\n");
-		exit(EXIT_FAILURE);
-	}
+	xsystem(buf);
 	sprintf(buf,"memoryi %08x + %08x { > %s.debugger }",(unsigned int) raw,count*4,folder);
-	if(system(buf))
-	{
-		fprintf(stderr,"memoryi failed!\n");
-		exit(EXIT_FAILURE);
-	}
+	xsystem(buf);
 	sprintf(buf,"settype %s.debugger fff",folder);
-	system(buf);
+	xsystem(buf);
 #endif
 #ifdef DECAOF
 	sprintf(buf,"dis2 %s 0 -decaof > %s.dis2_decaof",rawfile,folder);
-	if(system(buf))
-	{
-		fprintf(stderr,"dis2 failed!\n");
-		exit(EXIT_FAILURE);
-	}
+	xsystem(buf);
 	sprintf(buf,"dis2 %s 0 -decaofual > %s.dis2_decaofual",rawfile,folder);
-	if(system(buf))
-	{
-		fprintf(stderr,"dis2 failed!\n");
-		exit(EXIT_FAILURE);
-	}
+	xsystem(buf);
 	sprintf(buf,"decaof -c %s.aof > %s.decaof",folder,folder);
-	if(system(buf))
-	{
-		fprintf(stderr,"decaof failed!\n");
-		exit(EXIT_FAILURE);
-	}
+	xsystem(buf);
 	sprintf(buf,"decaof -uc %s.aof > %s.decaofual",folder,folder);
-	if(system(buf))
-	{
-		fprintf(stderr,"decaof failed!\n");
-		exit(EXIT_FAILURE);
-	}
+	xsystem(buf);
 #endif
 	printf("Postprocessing\n");
 #ifdef DECAOF
-	sprintf(buf,"grep \"  0x\" %s/decaof > %s/decaof2",folder,folder);
-	system(buf);
-	sprintf(buf,"grep \"  0x\" %s/decaofual > %s/decaofual2",folder,folder);
-	system(buf);
+	sprintf(buf,"grep \"  0x\" %s.decaof > %s.decaof2",folder,folder);
+	xsystem(buf);
+	sprintf(buf,"grep \"  0x\" %s.decaofual > %s.decaofual2",folder,folder);
+	xsystem(buf);
 #endif
 #ifndef MYDIFF
 #ifdef DEBUGGER
@@ -497,7 +513,7 @@ void process(char *rawfile,char *folder,unsigned int *raw,unsigned int count)
 	ret |= diff_debugger(folder,"debugger","dis2_debugger","diff_debugger");
 #else
 	sprintf(buf,"gnudiff -u %s/debugger2 %s/dis2_debugger2 > %s/diff_debugger",folder,folder,folder);
-	system(buf);
+	xsystem(buf);
 #endif
 #endif
 #ifdef DECAOF
@@ -506,9 +522,9 @@ void process(char *rawfile,char *folder,unsigned int *raw,unsigned int count)
 	ret |= diff_decaof(folder,"decaofual2","dis2_decaofual","diff_decaofual");
 #else
 	sprintf(buf,"gnudiff -ui %s/decaof3 %s/dis2_decaof2 > %s/diff_decaof",folder,folder,folder);
-	system(buf);
+	xsystem(buf);
 	sprintf(buf,"gnudiff -ui %s/decaofual3 %s/dis2_decaofual2 > %s/diff_decaofual",folder,folder,folder);
-	system(buf);
+	xsystem(buf);
 #endif
 #endif
 	if(ret)
@@ -525,19 +541,14 @@ int main(int argc,char **argv)
 		fprintf(stderr,"usage: testbed <folder> <start> <count>\n");
 		fprintf(stderr,"or:    testbed <folder> <start> <count> <repeat>\n");
 		fprintf(stderr,"or:    testbed <folder> <file>\n");
-		exit(EXIT_FAILURE);
+		exit(257);
 	}
 	char *folder = argv[1];
 	unsigned int count,*raw,repeat;
 	if(argc == 3)
 	{
 		char *rawfile = argv[2];
-		FILE *f = fopen(rawfile,"rb");
-		if(!f)
-		{
-			fprintf(stderr,"Couldn't open '%s'\n",rawfile);
-			exit(EXIT_FAILURE);
-		}
+		FILE *f = xfopen(rawfile,"rb");
 		printf("Loading file\n");
 		fseek(f,0,SEEK_END);
 		count = (unsigned int) (ftell(f)>>2);

VersionASM

@@ -11,13 +11,13 @@
                         GBLS    Module_HelpVersion
                         GBLS    Module_ComponentName
                         GBLS    Module_ComponentPath
-Module_MajorVersion     SETS    "1.87"
-Module_Version          SETA    187
+Module_MajorVersion     SETS    "2.02"
+Module_Version          SETA    202
 Module_MinorVersion     SETS    ""
-Module_Date             SETS    "24 Oct 2014"
-Module_ApplicationDate  SETS    "24-Oct-14"
+Module_Date             SETS    "25 Feb 2018"
+Module_ApplicationDate  SETS    "25-Feb-18"
 Module_ComponentName    SETS    "Debugger"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Programmer/Debugger"
-Module_FullVersion      SETS    "1.87"
-Module_HelpVersion      SETS    "1.87 (24 Oct 2014)"
+Module_FullVersion      SETS    "2.02"
+Module_HelpVersion      SETS    "2.02 (25 Feb 2018)"
                         END

VersionNum

-/* (1.87)
+/* (2.02)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        1.87
+#define Module_MajorVersion_CMHG        2.02
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                24 Oct 2014
+#define Module_Date_CMHG                25 Feb 2018
 
-#define Module_MajorVersion             "1.87"
-#define Module_Version                  187
+#define Module_MajorVersion             "2.02"
+#define Module_Version                  202
 #define Module_MinorVersion             ""
-#define Module_Date                     "24 Oct 2014"
+#define Module_Date                     "25 Feb 2018"
 
-#define Module_ApplicationDate          "24-Oct-14"
+#define Module_ApplicationDate          "25-Feb-18"
 
 #define Module_ComponentName            "Debugger"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Programmer/Debugger"
 
-#define Module_FullVersion              "1.87"
-#define Module_HelpVersion              "1.87 (24 Oct 2014)"
-#define Module_LibraryVersionInfo       "1:87"
+#define Module_FullVersion              "2.02"
+#define Module_HelpVersion              "2.02 (25 Feb 2018)"
+#define Module_LibraryVersionInfo       "2:2"

actions/ARMv7

@@ -347,6 +347,9 @@ DMB_A1(option,nonstandard)
 	ONLY1(ARMv7);
 	if(!dmb_dsb_opt[option].valid)
 		warning(JUSTPARAMS,WARN_BAD_DMB_DSB_ISB_OPTION);
+	/* Special mention OSHLD/NSHLD/ISHLD/LD */
+	if((option==1)||(option==5)||(option==9)||(option==13))
+		ONLY1(ARMv8);
 	sprintf(params->buf,"DMB\t%s",dmb_dsb_opt[option].str);
 	return;
 }
@@ -357,6 +360,9 @@ DSB_A1(option,nonstandard)
 	ONLY1(ARMv7);
 	if(!dmb_dsb_opt[option].valid)
 		warning(JUSTPARAMS,WARN_BAD_DMB_DSB_ISB_OPTION);
+	/* Special mention OSHLD/NSHLD/ISHLD/LD */
+	if((option==1)||(option==5)||(option==9)||(option==13))
+		ONLY1(ARMv8);
 	sprintf(params->buf,"DSB\t%s",dmb_dsb_opt[option].str);
 	return;
 }
@@ -788,7 +794,8 @@ LDRHT_A1(cond,U,Rn,Rt,imm4H:imm4L,nonstandard)
 	COMMON
 	ONLY2(ARMv6T2,ARMv7);
 	_UNPREDICTABLE((Rt==15) || (Rn==15) || (Rn==Rt));
-	sprintf(params->buf,"LDRHT%s\t%s,[%s],#%s%d",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),imm4H_imm4L);
+	const char *fmt = (params->opt->ual?"LDRHT%s\t%s,[%s],#%s%d":"LDR%sHT\t%s,[%s],#%s%d");
+	sprintf(params->buf,fmt,condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),imm4H_imm4L);
 	return;
 }
 
@@ -797,7 +804,8 @@ LDRHT_A2(cond,U,Rn,Rt,Rm,nonstandard)
 	COMMON
 	ONLY2(ARMv6T2,ARMv7);
 	_UNPREDICTABLE((Rt==15) || (Rn==15) || (Rn==Rt) || (Rm==15));
-	sprintf(params->buf,"LDRHT%s\t%s,[%s],%s%s",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),REG(Rm));
+	const char *fmt = (params->opt->ual?"LDRHT%s\t%s,[%s],%s%s":"LDR%sHT\t%s,[%s],%s%s");
+	sprintf(params->buf,fmt,condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),REG(Rm));
 	return;
 }
 
@@ -848,7 +856,8 @@ LDRSBT_A1(cond,U,Rn,Rt,imm4H:imm4L,nonstandard)
 	COMMON
 	ONLY2(ARMv6T2,ARMv7);
 	_UNPREDICTABLE((Rt==15) || (Rn==15) || (Rn==Rt));
-	sprintf(params->buf,"LDRSBT%s\t%s,[%s],#%s%d",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),imm4H_imm4L);
+	const char *fmt = (params->opt->ual?"LDRSBT%s\t%s,[%s],#%s%d":"LDR%sSBT\t%s,[%s],#%s%d");
+	sprintf(params->buf,fmt,condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),imm4H_imm4L);
 	return;
 }
 
@@ -857,7 +866,8 @@ LDRSBT_A2(cond,U,Rn,Rt,Rm,nonstandard)
 	COMMON
 	ONLY2(ARMv6T2,ARMv7);
 	_UNPREDICTABLE((Rt==15) || (Rn==15) || (Rn==Rt) || (Rm==15));
-	sprintf(params->buf,"LDRSBT%s\t%s,[%s],%s%s",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),REG(Rm));
+	const char *fmt = (params->opt->ual?"LDRSBT%s\t%s,[%s],%s%s":"LDR%sSBT\t%s,[%s],%s%s");
+	sprintf(params->buf,fmt,condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),REG(Rm));
 	return;
 }
 
@@ -908,7 +918,8 @@ LDRSHT_A1(cond,U,Rn,Rt,imm4H:imm4L,nonstandard)
 	COMMON
 	ONLY2(ARMv6T2,ARMv7);
 	_UNPREDICTABLE((Rt==15) || (Rn==15) || (Rn==Rt));
-	sprintf(params->buf,"LDRSHT%s\t%s,[%s],#%s%d",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),imm4H_imm4L);
+	const char *fmt = (params->opt->ual?"LDRSHT%s\t%s,[%s],#%s%d":"LDR%sSHT\t%s,[%s],#%s%d");
+	sprintf(params->buf,fmt,condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),imm4H_imm4L);
 	return;
 }
 
@@ -917,7 +928,8 @@ LDRSHT_A2(cond,U,Rn,Rt,Rm,nonstandard)
 	COMMON
 	ONLY2(ARMv6T2,ARMv7);
 	_UNPREDICTABLE((Rt==15) || (Rn==15) || (Rn==Rt) || (Rm==15));
-	sprintf(params->buf,"LDRSHT%s\t%s,[%s],%s%s",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),REG(Rm));
+	const char *fmt = (params->opt->ual?"LDRSHT%s\t%s,[%s],%s%s":"LDR%sSHT\t%s,[%s],%s%s");
+	sprintf(params->buf,fmt,condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),REG(Rm));
 	return;
 }
 
@@ -2197,7 +2209,8 @@ STRHT_A1(cond,U,Rn,Rt,imm4H:imm4L,nonstandard)
 	COMMON
 	ONLY2(ARMv6T2,ARMv7);
 	_UNPREDICTABLE((Rt==15) || (Rn==15) || (Rn==Rt));
-	sprintf(params->buf,"STRHT%s\t%s,[%s],#%s%d",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),imm4H_imm4L);
+	const char *fmt = (params->opt->ual?"STRHT%s\t%s,[%s],#%s%d":"STR%sHT\t%s,[%s],#%s%d");
+	sprintf(params->buf,fmt,condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),imm4H_imm4L);
 	return;
 }
 
@@ -2206,7 +2219,8 @@ STRHT_A2(cond,U,Rn,Rt,Rm,nonstandard)
 	COMMON
 	ONLY2(ARMv6T2,ARMv7);
 	_UNPREDICTABLE((Rt==15) || (Rn==15) || (Rn==Rt) || (Rm==15));
-	sprintf(params->buf,"STRHT%s\t%s,[%s],%s%s",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),REG(Rm));
+	const char *fmt = (params->opt->ual?"STRHT%s\t%s,[%s],%s%s":"STR%sHT\t%s,[%s],%s%s");
+	sprintf(params->buf,fmt,condition(JUSTPARAMS,cond),REG(Rt),REG(Rn),(U?"":"-"),REG(Rm));
 	return;
 }
 
@@ -2841,7 +2855,7 @@ MRS_banked_A1(cond,R,m1,Rd,m,nonstandard)
 	ONLY1(ARMv7VE);
 	_UNPREDICTABLE(Rd==15);
 	sprintf(params->buf,"MRS%s\t%s,",condition(JUSTPARAMS,cond),REG(Rd));
-	dobankedmsr(JUSTPARAMS,(m<<1)|m1,R);
+	dobankedmsr(JUSTPARAMS,(m<<4)|m1,R);
 	return;
 }
 
@@ -2858,8 +2872,8 @@ MSR_banked_A1(cond,R,m1,Rn,m,nonstandard)
 	COMMON
 	ONLY1(ARMv7VE);
 	_UNPREDICTABLE(Rn==15);
-	sprintf(params->buf,"MRS%s\t",condition(JUSTPARAMS,cond));
-	dobankedmsr(JUSTPARAMS,(m<<1)|m1,R);
+	sprintf(params->buf,"MSR%s\t",condition(JUSTPARAMS,cond));
+	dobankedmsr(JUSTPARAMS,(m<<4)|m1,R);
 	scatf(params->buf,",%s",REG(Rn));
 	return;
 }

actions/ARMv7_ASIMD

@@ -264,7 +264,7 @@ VCLS_A1(D:Vd,size,Q,M:Vm,nonstandard)
 {
 	COMMON
 	ONLY1(ASIMD);
-	ASIMD_D_M(JUSTPARAMS,"CLS",size,0,Q,D_Vd,M_Vm);
+	ASIMD_D_M(JUSTPARAMS,"VCLS",size,0,Q,D_Vd,M_Vm);
 	return;
 }
 
@@ -650,7 +650,7 @@ VMOVN_A1(D:Vd,size,M:Vm,nonstandard)
 {
 	COMMON
 	ONLY1(ASIMD);
-	sprintf(params->buf,"VMOVN%s.I%d\tD%d,Q%d",ASIMDCOND,8<<size,D_Vd,M_Vm>>1);
+	sprintf(params->buf,"VMOVN%s.I%d\tD%d,Q%d",ASIMDCOND,16<<size,D_Vd,M_Vm>>1);
 	return;
 }
 
@@ -1171,7 +1171,7 @@ VRSUBHN_A1(D:Vd,size,N:Vn,M:Vm,nonstandard)
 {
 	COMMON
 	ONLY1(ASIMD);
-	ASIMD_I_DD_QN_QM(JUSTPARAMS,"VRSUBHN",size,D_Vd,N_Vn,M_Vm);
+	ASIMD_I_DD_QN_QM(JUSTPARAMS,"VRSUBHN",size+1,D_Vd,N_Vn,M_Vm);
 	return;
 }
 
@@ -1342,7 +1342,7 @@ VSRI_A1(D:Vd,imm6,L,Q,M:Vm,nonstandard)
 		esize = 8;
 		amt = 16-imm6;
 	}
-	const char *fmt = (Q?"VRSI%s.%d\tQ%d,Q%d,#%d":"VRSI%s.%d\tD%d,D%d,#%d");
+	const char *fmt = (Q?"VSRI%s.%d\tQ%d,Q%d,#%d":"VSRI%s.%d\tD%d,D%d,#%d");
 	sprintf(params->buf,fmt,ASIMDCOND,esize,D_Vd>>Q,M_Vm>>Q,amt);
 	return;
 }

actions/ARMv7_VFP

@@ -155,7 +155,7 @@ VFNMA_VFNMS_A1(cond,D,Vn,Vd,sz,N,op,M,Vm,nonstandard)
 	_UNDEFINED(sz && !VFPDP);
 	COMMON
 	ONLY1(VFPv4);
-	VFP_CC_VD_VN_VM(JUSTPARAMS,(op?"VFNMS":"VFNMA"),(op?"VFNMS":"VFNMA"),cond,sz,Vd,D,Vn,N,Vm,M);
+	VFP_CC_VD_VN_VM(JUSTPARAMS,(op?"VFNMA":"VFNMS"),(op?"VFNMA":"VFNMS"),cond,sz,Vd,D,Vn,N,Vm,M);
 	return;
 }
 

actions/ARMv8FP_AArch32

+# Copyright 2018 Castle Technology Ltd
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# Actions for ARMv8 FP disassembly (just the ARMv8 bits)
+
+VMAXNM_VMINNM_A1(op,D:Vd,N:Vn,Q,M:Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	ASIMD_F32_D_N_M(JUSTPARAMS,(op?"VMINNM":"VMAXNM"),Q,D_Vd,N_Vn,M_Vm);
+	return;
+}
+
+VMAXNM_VMINNM_A2(D,Vn,Vd,sz,op,N,M,Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	VFP_CC_VD_VN_VM(JUSTPARAMS,(op?"VMINNM":"VMAXNM"),(op?"VMINNM":"VMAXNM"),14,sz,Vd,D,Vn,N,Vm,M);
+	return;
+}
+
+VCVTx_ASIMD_A1(D:Vd,RM,op,Q,M:Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	const char rms[4] = {'A','N','P','M'};
+	sprintf(params->buf,(Q?"VCVT%c.%c32.F32\tQ%d,Q%d":"VCVT%c.%c32.F32\tD%d,D%d"),rms[RM],(op?'U':'S'),D_Vd>>Q,M_Vm>>Q);
+	return;
+}
+
+VCVTx_fp_A1(D,RM,Vd,sz,op,M,Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	const char rms[4] = {'A','N','P','M'};
+	if (sz)
+	{
+		sprintf(params->buf,"VCVT%c.%c32.F64\tS%d,D%d",rms[RM],(op?'S':'U'),(Vd<<1)|D,(M<<4)|Vm);
+	}
+	else
+	{
+		sprintf(params->buf,"VCVT%c.%c32.F32\tS%d,S%d",rms[RM],(op?'S':'U'),(Vd<<1)|D,(Vm<<1)|M);
+	}
+	return;
+}
+
+VCVTB_VCVTT_A1(cond,D,Vd,op,T,M,Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	if (op)
+	{
+		sprintf(params->buf,"VCVT%c%s.F16.F64\tS%d,D%d",(T?'T':'B'),condition(JUSTPARAMS,cond),(Vd<<1)|D,(M<<4)|Vm);
+	}
+	else
+	{
+		sprintf(params->buf,"VCVT%c%s.F64.F16\tD%d,S%d",(T?'T':'B'),condition(JUSTPARAMS,cond),(D<<4)|Vd,(Vm<<1)|M);
+	}
+	return;
+}
+
+VRINTx_ASIMD_A1(D:Vd,op,Q,M:Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	const char rms[4] = {'N','A','M','P'};
+	sprintf(params->buf,(Q?"VRINT%c.F32.F32\tQ%d,Q%d":"VRINT%c.F32.F32\tD%d,D%d"),rms[op>>1],D_Vd>>Q,M_Vm>>Q);
+	return;
+}
+
+VRINTx_fp_A1(D,RM,Vd,sz,M,Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	const char rms[4] = {'A','N','P','M'};
+	char opstr[12];
+	sprintf(opstr,"VRINT%c.F%d",rms[RM],(sz?64:32));
+	VFP_CC_VD_VM(JUSTPARAMS,opstr,opstr,14,sz,Vd,D,Vm,M);
+	return;
+}
+
+VRINTR_VRINTZ_fp_A1(cond,D,Vd,sz,op,M,Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	char opstr[16];
+	sprintf(opstr,"VRINT%c%s.F%d",(op?'Z':'R'),condition(JUSTPARAMS,cond),(sz?64:32));
+	VFP_CC_VD_VM(JUSTPARAMS,opstr,opstr,14,sz,Vd,D,Vm,M);
+	return;
+}
+
+VRINTX_ASIMD_A1(D:Vd,Q,M:Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	sprintf(params->buf,(Q?"VRINTX.F32.F32\tQ%d,Q%d":"VRINTX.F32.F32\tD%d,D%d"),D_Vd>>Q,M_Vm>>Q);
+	return;
+}
+
+VRINTZ_ASIMD_A1(D:Vd,Q,M:Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	sprintf(params->buf,(Q?"VRINTZ.F32.F32\tQ%d,Q%d":"VRINTZ.F32.F32\tD%d,D%d"),D_Vd>>Q,M_Vm>>Q);
+	return;
+}
+
+VRINTX_fp_A1(cond,D,Vd,sz,M,Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	char opstr[16];
+	sprintf(opstr,"VRINTX%s.F%d",condition(JUSTPARAMS,cond),(sz?64:32));
+	VFP_CC_VD_VM(JUSTPARAMS,opstr,opstr,14,sz,Vd,D,Vm,M);
+	return;
+}
+
+VSELxx_A1(D,cc,Vn,Vd,sz,N,M,Vm,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	const char conds[4] = {0,6,10,12};
+	VFP_CC_VD_VN_VM(JUSTPARAMS,"VSEL","VSEL",conds[cc],sz,Vd,D,Vn,N,Vm,M);
+	return;
+}

actions/ARMv8_AArch32

+# Copyright 2016 Castle Technology Ltd
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# Actions for ARMv8 disassembly
+
+CRC_A1(cond,sz,Rn,Rd,C,Rm,nonstandard)
+{
+	COMMON
+	static const char sizes[] = "BHWD";
+	ONLY1(ARMv8);
+	_UNPREDICTABLE((Rd==15) || (Rn==15) || (Rm==15) || (sz==3) || (cond!=14));
+	sprintf(params->buf,"CRC32%s%c\t%s,%s,%s",C?"C":"",sizes[sz],REG(Rd),REG(Rn),REG(Rm));
+	return;
+}
+
+SEVL_A1(cond,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	sprintf(params->buf,"SEVL%s",condition(JUSTPARAMS,cond));
+	return;
+}
+
+HLT_A1(cond,imm12:imm4,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	_UNPREDICTABLE(cond!=14);
+	sprintf(params->buf,"HLT%s\t%s%s%04X",condition(JUSTPARAMS,cond),(params->opt->ual?"#":""),HEX,imm12_imm4);
+	return;
+}
+
+LDAEXB_A1(cond,Rn,Rt,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	_UNPREDICTABLE((Rt==15) || (Rn==15));
+	sprintf(params->buf,"LDAEXB%s\t%s,[%s]",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn));
+	return;
+}
+
+LDAEXH_A1(cond,Rn,Rt,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	_UNPREDICTABLE((Rt==15) || (Rn==15));
+	sprintf(params->buf,"LDAEXH%s\t%s,[%s]",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn));
+	return;
+}
+
+LDAEX_A1(cond,Rn,Rt,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	_UNPREDICTABLE((Rt==15) || (Rn==15));
+	sprintf(params->buf,"LDAEX%s\t%s,[%s]",condition(JUSTPARAMS,cond),REG(Rt),REG(Rn));
+	return;
+}
+
+LDAEXD_A1(cond,Rn,Rt,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	_UNPREDICTABLE((Rt&1) || (Rt==14) || (Rn==15));
+	sprintf(params->buf,"LDAEXD%s\t%s,%s,[%s]",condition(JUSTPARAMS,cond),REG(Rt),REG((Rt+1)&0xf),REG(Rn));
+	return;
+}
+
+STLEXB_A1(cond,Rn,Rd,Rt,nonstandard)
+{
+	COMMON
+	_UNPREDICTABLE((Rd==15) || (Rt==15) || (Rn==15));
+	_UNPREDICTABLE((Rd==Rn) || (Rd==Rt));
+	ONLY1(ARMv8);
+	sprintf(params->buf,"STLEXB%s\t%s,%s,[%s]",condition(JUSTPARAMS,cond),REG(Rd),REG(Rt),REG(Rn));
+	return;
+}
+
+STLEXH_A1(cond,Rn,Rd,Rt,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	_UNPREDICTABLE((Rd==15) || (Rt==15) || (Rn==15));
+	_UNPREDICTABLE((Rd==Rn) || (Rd==Rt));
+	sprintf(params->buf,"STLEXH%s\t%s,%s,[%s]",condition(JUSTPARAMS,cond),REG(Rd),REG(Rt),REG(Rn));
+	return;
+}
+
+STLEX_A1(cond,Rn,Rd,Rt,nonstandard)
+{
+	COMMON
+	_UNPREDICTABLE((Rd==15) || (Rt==15) || (Rn==15));
+	_UNPREDICTABLE((Rd==Rn) || (Rd==Rt));
+	ONLY1(ARMv8);
+	sprintf(params->buf,"STLEX%s\t%s,%s,[%s]",condition(JUSTPARAMS,cond),REG(Rd),REG(Rt),REG(Rn));
+	return;
+}
+
+STLEXD_A1(cond,Rn,Rd,Rt,nonstandard)
+{
+	COMMON
+	_UNPREDICTABLE((Rd==15) || (Rt&1) || (Rt==14) || (Rn==15));
+	_UNPREDICTABLE((Rd==Rn) || ((Rd&0xe)==Rt));
+	ONLY1(ARMv8);
+	sprintf(params->buf,"STLEXD%s\t%s,%s,%s,[%s]",condition(JUSTPARAMS,cond),REG(Rd),REG(Rt),REG((Rt+1)&0xf),REG(Rn));
+	return;
+}
+
+LDA_A1(cond,sz,Rn,Rt,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	_UNPREDICTABLE((Rt==15) || (Rn==15));
+	sprintf(params->buf,"LDA%s%s\t%s,[%s]",condition(JUSTPARAMS,cond),(sz==0)?"":(sz==2)?"B":"H",REG(Rt),REG(Rn));
+	return;
+}
+
+STL_A1(cond,sz,Rn,Rt,nonstandard)
+{
+	COMMON
+	ONLY1(ARMv8);
+	_UNPREDICTABLE((Rt==15) || (Rn==15));
+	sprintf(params->buf,"STL%s%s\t%s,[%s]",condition(JUSTPARAMS,cond),(sz==0)?"":(sz==2)?"B":"H",REG(Rt),REG(Rn));
+	return;
+}

c/support

@@ -33,6 +33,18 @@ char *strcat(char *str1,const char *str2)
 	return ret;
 }
 
+int strcmp(const char *str1, const char *str2)
+{
+	char c;
+	int diff;
+	do
+	{
+		c = *str1++;
+		diff = c - *str2++;
+	} while (c && !diff);
+	return diff;
+}
+
 void *memcpy(void *ptr1,const void *ptr2,size_t n)
 {
 	while(n--)
@@ -46,7 +58,7 @@ int sprintf(char *out,const char *format,...)
 {
 	va_list a;
 	va_start(a,format);
-	int ret = vsprintf(out,format,a);
+	int ret = vsnprintf(out,SIZE_MAX,format,a);
 	va_end(a);
 	return ret;
 }
@@ -57,21 +69,49 @@ int _sprintf(char *out,const char *format,...)
 {
 	va_list a;
 	va_start(a,format);
-	int ret = vsprintf(out,format,a);
+	int ret = vsnprintf(out,SIZE_MAX,format,a);
+	va_end(a);
+	return ret;
+}
+
+int snprintf(char *out,size_t max,const char *format,...)
+{
+	va_list a;
+	va_start(a,format);
+	int ret = vsnprintf(out,max,format,a);
+	va_end(a);
+	return ret;
+}
+
+extern int _snprintf(char *out,size_t max,const char *format,...);
+
+int _snprintf(char *out,size_t max,const char *format,...)
+{
+	va_list a;
+	va_start(a,format);
+	int ret = vsnprintf(out,max,format,a);
 	va_end(a);
 	return ret;
 }
 
 int vsprintf(char *out,const char *format,va_list a)
 {
-	int count=0;
+	return vsnprintf(out,SIZE_MAX,format,a);
+}
+
+#define OUTC(C) do { char chr = C; if (count < usable_max) out[count] = chr; count++; } while(0)
+
+int vsnprintf(char *out,size_t max,const char *format,va_list a)
+{
+	size_t count=0;
 	int c;
+	size_t usable_max = (out ? max : 0);
 	while((c = *format++) != 0)
 	{
 		if(c == '%')
 		{
 			/* We'll only deal with the following format specifiers:
-			   %s   (control-terminated - to cope with messages)
+			   %[-<width>]s   (control-terminated - to cope with messages)
 			   %c
 			   %<width>[ll]X
 			   %<width>[ll]x
@@ -81,6 +121,8 @@ int vsprintf(char *out,const char *format,va_list a)
 			int width=0;
 			bool islong=false;
 			c = *format++;
+			if (c == '-')
+				c = *format++;
 			while((c >= '0') && (c <= '9'))
 			{
 				width = width*10 + c - '0';
@@ -91,12 +133,27 @@ int vsprintf(char *out,const char *format,va_list a)
 			case 's':
 				{
 				const char *s = va_arg(a,const char *);
-				while(*s >= ' ')
-					out[count++] = *s++;
+				if(width)
+				{
+					/* Assume left-justified */
+					do
+					{
+						OUTC(((*s >= ' ') ? *s++ : ' '));
+					}
+					while(--width);
+				}
+				else
+				{
+					while(*s >= ' ')
+					{
+						OUTC(*s++);
+						width--;
+					}
+				}
 				}
 				break;
 			case 'c':
-				out[count++] = va_arg(a,int);
+				OUTC(va_arg(a,int));
 				break;
 			case 'l':
 				islong = true;
@@ -116,16 +173,18 @@ int vsprintf(char *out,const char *format,va_list a)
 					width = 1;
 				do
 				{
-					unsigned int n = h>>60;
+					unsigned int n = (unsigned int) (h>>60);
 					if(n || (i<width))
 					{
 						width = 16;
+						char c2;
 						if(n <= 9)
-							out[count++] = n+'0';
+							c2 = n+'0';
 						else if(c == 'X')
-							out[count++] = n+'A'-10;
+							c2 = n+'A'-10;
 						else
-							out[count++] = n+'a'-10;
+							c2 = n+'a'-10;
+						OUTC(c2);
 					}
 					h=h<<4;
 				} while(--i >= 0);
@@ -138,7 +197,7 @@ int vsprintf(char *out,const char *format,va_list a)
 				if((i & 0x80000000) && (c == 'd'))
 				{
 					i = -i;
-					out[count++] = '-';
+					OUTC('-');
 				}
 				while(i)
 				{
@@ -151,7 +210,7 @@ int vsprintf(char *out,const char *format,va_list a)
 					}
 					while(width > k)
 					{
-						out[count++] = '0';
+						OUTC('0');
 						width--;
 					}
 					c = '0';
@@ -160,25 +219,24 @@ int vsprintf(char *out,const char *format,va_list a)
 						i -= j;
 						c++;
 					}
-					out[count++] = c;
+					OUTC(c);
 					width = k-1;
 				}
 				while(width-- >= 0)
-					out[count++] = '0';
+					OUTC('0');
 				}
 				break;
 			}
 		}
-		else if(c == '\\')
-		{
-			out[count++] = *format++;
-		}
 		else
 		{
-			out[count++] = c;
+			OUTC(c);
 		}
 	}
-	out[count] = 0;
+	if (out && max)
+	{
+		out[(count < max) ? count : (max-1)] = 0;
+	}
 	return count;
 }
 

c/util

@@ -20,19 +20,19 @@
 const optval dmb_dsb_opt[16] =
 {
 	{ "#0", false },
-	{ "#1", false },
+	{ "OSHLD", true },
 	{ "OSHST", true },
 	{ "OSH", true },
 	{ "#4", false },
-	{ "#5", false },
+	{ "NSHLD", true },
 	{ "NSHST", true },
 	{ "NSH", true },
 	{ "#8", false },
-	{ "#9", false },
+	{ "ISHLD", true },
 	{ "ISHST", true },
 	{ "ISH", true },
 	{ "#12", false },
-	{ "#13", false },
+	{ "LD", true },
 	{ "ST", true },
 	{ "SY", true },
 };
@@ -65,7 +65,7 @@ const optval vfp_mrs[16] =
 	{ "c2", false },
 	{ "c3", false },
 	{ "c4", false },
-	{ "c5", false },
+	{ "MVFR2", true },
 	{ "MVFR1", true },
 	{ "MVFR0", true },
 	{ "FPEXC", true },
@@ -152,9 +152,10 @@ const char *archwarnings[ARCH_MAX] =
 	"ASIMD",
 	"ASIMD half-precision",
 	"ASIMD FP required",
-	"ASIMDv2 FP or later"
+	"ASIMDv2 FP or later",
 	"FPA",
 	"XScale DSP instruction",
+	"ARMv8 or later",
 };
 #endif
 
@@ -326,7 +327,7 @@ void dobankedmsr(JUSTPARAMDECL,uint32_t SYSm,uint32_t R)
 			{8,USR32},{9,USR32},{10,USR32},{11,USR32},{12,USR32},{13,USR32},{14,USR32},{0,0},
 			{8,FIQ32},{9,FIQ32},{10,FIQ32},{11,FIQ32},{12,FIQ32},{13,FIQ32},{14,FIQ32},{0,0},
 			{14,IRQ32},{13,IRQ32},{14,SVC32},{13,SVC32},{14,ABT32},{13,ABT32},{14,UND32},{13,UND32},
-			{0,0},{0,0},{0,0},{0,0},{14,MON32},{13,MON32},{14,HYP32},{12,HYP32},
+			{0,0},{0,0},{0,0},{0,0},{14,MON32},{13,MON32},{14,HYP32},{13,HYP32},
 		};
 		reg = REG(enc[SYSm][0]);
 		mode = enc[SYSm][1];