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Fix wrong XCBTable being used for pre-rev T StrongARMs. Update HAL UART API docs.
Jeffrey Lee authored 
Detail:
  s/ARMops - Fix pre-rev T StrongARMs using the wrong XCBTable, causing invalid page flags to be used for the write-through cache policy
  Docs/HAL/Serial - Update HAL UART API docs. Mostly filling in some blanks, but also correcting a couple of things, and documenting new Features bit 4, LineStatus bit 8, and the effect on InterruptID.
Admin:
  Tested on pre-rev T StrongARM RiscPC


Version 5.61. Tagged as 'Kernel-5_61'
fe59a83a
Name Last commit Last update
..
5thColumn RISC OS 3.71 kernel changes merged.
HAL Fix wrong XCBTable being used for pre-rev T StrongARMs. Update HAL UART API docs.
MemMaps RISC OS 3.71 kernel changes merged.
PrivDoc RISC OS 3.71 kernel changes merged.
!ReadMe Import from cleaned 370 CD
0197276.02 Import from cleaned 370 CD
32bit Delete lots of old switches
32bitAPIs Commit of kernel as featured in release 5.00.
A540Extend Import from cleaned 370 CD
AMBControl Import from cleaned 370 CD
CallbackChange Miscellaneous stuff.
GraphicsV Merged in changes from Castle
HiResTTX Added 256-colour version of the (high-resolution only) teletext code, and support for teletext when hardware scroll is disabled. Both are required for Tungsten.
Kernel Import from cleaned 370 CD
KernlSplit Import from cleaned 370 CD
MMUControl Import from cleaned 370 CD
ModPostServ HAL device support, and a couple of new service calls.
Mode22 Import from cleaned 370 CD
Modes Import from cleaned 370 CD
MonLead Import from cleaned 370 CD
PageFlags Lots of Tungsten work.
PaletteV Import from cleaned 370 CD
RO370 Lots of Tungsten work.
ReadSysInf Lots of Tungsten work.
ReadUnsigned Merge over some changes from the Cortex branch
TVmodesMed,dde