1. 07 Aug, 2021 1 commit
    • Jeffrey Lee's avatar
      Add safety checks to s.CPUFeatures · e2e5a722
      Jeffrey Lee authored
      To avoid CallASWI's CPUFeatures implementation getting dangerously out
      of sync with the kernel, add extra asserts to both sets of sources to
      check try and make sure both sets of sources get updated when new flags
      are added.
      e2e5a722
  2. 28 Jul, 2021 1 commit
  3. 22 May, 2016 2 commits
    • Jeffrey Lee's avatar
      Revise comments - it's multiprocessing extensions, not virtualisation · 02664d59
      Jeffrey Lee authored
      Version 5.35, 4.79.2.323. Tagged as 'Kernel-5_35-4_79_2_323'
      02664d59
    • Jeffrey Lee's avatar
      Revise WFE detection · 7c914258
      Jeffrey Lee authored
      Detail:
        s/CPUFeatures - Take account of the fact that single-core ARMv7+ chips implement MPIDR but aren't guaranteed to implement a useful WFE. So for ARMv7+, only report WFE as being available/useful if MPIDR indicates that virtualisation extensions are supported.
      Admin:
        Tested on Raspberry Pi 1 & 3, BB-xM
      
      
      Version 5.35, 4.79.2.322. Tagged as 'Kernel-5_35-4_79_2_322'
      7c914258
  4. 20 May, 2016 1 commit
    • Jeffrey Lee's avatar
      Fix CPU features being clobbered by software RAM clear · 36bf6e21
      Jeffrey Lee authored
      Detail:
        s/ARMops, s/HAL - Move CPU feature init to after the RAM clear, to prevent the cached values being clobbered on platforms where the HAL doesn't perform the RAM clear
        s/CPUFeatures - Update/clarify comment
      Admin:
        Tested on Raspberry Pi
        Fixes issue spotted by Sprow
      
      
      Version 5.35, 4.79.2.320. Tagged as 'Kernel-5_35-4_79_2_320'
      36bf6e21
  5. 19 May, 2016 1 commit
    • Jeffrey Lee's avatar
      Add new OS_PlatformFeatures reason code for reading CPU features (inspired by... · 9944f0f8
      Jeffrey Lee authored
      Add new OS_PlatformFeatures reason code for reading CPU features (inspired by ARMv6+ CPUID scheme). Add OS_ReadSysInfo 8 flags for indicating the alignment mode the ROM was built with. Fix long-standing bug with OS_PlatformFeatures when an unknown reason code is used.
      
      Detail:
        s/CPUFeatures, hdr/OSMisc, hdr/KernelWS - Code and definitions for reading CPU features and reporting them via OS_PlatformFeatures 34. All the instruction set features which are exposed by the CPUID scheme and which are relevant to RISC OS are exposed, along with a few extra flags which we derive ourselves (e.g. things relating to < ARMv4, and some register usage restrictions in instructions). s/CPUFeatures is designed to be easily copyable into a future version of CallASWI without requiring any changes.
        s/ARMops - Read and cache CPU features during ARMop initialisation
        s/GetAll - GET new file
        s/Kernel - Hook up the CPU features code to OS_PlatformFeatures. Fix a long standing stack imbalance bug (fixed in RISC OS 3.8, but never merged back to our main branch) which meant that calling OS_PlatformFeatures with an invalid reason code would raise an error, even if it was the X form of the SWI that was called. Similar fix also applied to the unused service call code, along with a fix for the user's R1-R9 being corrupt (shuffled up one place) should an error have been generated.
        s/MemInfo - Extra LTORG needed to keep things happy
        s/Middle - Extend OS_ReadSysInfo 8 to include flags for indicating what memory alignment mode (if any) the OS relies upon. Together with OS_PlatformFeatures 34 this could e.g. be used by !CPUSetup to determine which options should be offered to the user.
      Admin:
        Tested on Raspberry Pi 1, 2, 3
      
      
      Version 5.35, 4.79.2.319. Tagged as 'Kernel-5_35-4_79_2_319'
      9944f0f8