Commit 3d5802b0 authored by Jeffrey Lee's avatar Jeffrey Lee Committed by ROOL
Browse files

OS_PlatformFeatures 34: Report presence of some CP15 regs

Report whether:
* DFAR & DFSR are writable
* IFAR, IFSR, AIFSR, ADFSR are implemented
parent 994013b4
......@@ -1332,7 +1332,7 @@ SoftAplWorkMaxSize * AppSpaceDANode + DANode_MaxSize
ExtendedROMFooter # 4 ; Pointer to the extended ROM footer structure. 0 if not initialised, -1 if not found.
CPUFeatures # 2*4
CPUFeatures # 3*4
[ :DEF: ShowWS
! 0, "Free space after EnvString = ":CC::STR:(&500-@)
......
......@@ -113,6 +113,11 @@ CPUFeature_UMULL_UMLAL # 1
CPUFeature_WFE # 1
CPUFeature_Rotated_loads # 1 ; CPU supports old-style rotated load behaviour
CPUFeature_Unaligned_loads # 1 ; CPU supports new-style unaligned load/store behaviour
CPUFeature_CP15_IFAR # 1 ; CP15 IFAR register implemented
CPUFeature_CP15_IFSR # 1 ; CP15 IFSR register implemented
CPUFeature_CP15_AIFSR # 1 ; CP15 AIFSR register implemented
CPUFeature_CP15_DFAR_DFSR_writable # 1 ; CP15 DFAR & DFSR are writable
CPUFeature_CP15_ADFSR # 1 ; CP15 ADFSR register implemented
CPUFeature_Max # 0
; OS_MMUControl reason codes
......
......@@ -141,8 +141,9 @@ Init_ARMarch ROUT
CPUFeatures
DCD 0
DCD 0
DCD 0
CPUFeatures_Size * 8
CPUFeatures_Size * 12
|
CPUFeatures_Size * ?CPUFeatures
]
......@@ -170,10 +171,11 @@ CalcCPUFeatures ROUT
|
ADR r2, CPUFeatures
]
ASSERT CPUFeatures_Size == 8
ASSERT CPUFeatures_Size == 12
MOV r3, #0
STR r3, [r2]
STR r3, [r2, #4]
STR r3, [r2, #8]
; Fill in the features defined by the instruction set feature registers
ADR r3, FeatureRegsTable
ADR r4, FeatureRegsTableEnd
......@@ -222,6 +224,7 @@ CalcCPUFeatures ROUT
CMP r4, #ARMv4
SetFeatureGE LDRSB
SetFeatureGE SYS_mode
SetFeatureGE CP15_DFAR_DFSR_writable
SetFeatureLE MULS_flag_corruption
[ InKernel ; Kernel init is too early for SWIs, just check target machine type instead
[ "$Machine" <> "IOMD"
......@@ -246,10 +249,24 @@ CalcCPUFeatures ROUT
SetFeatureLE Rotated_loads
BLT %FT40
SetFeature Unaligned_loads
SetFeature CP15_IFSR
; Look at the cache type register to work out whether this is ARMv6 or ARMv7+
MRC p15, 0, r5, c0, c0, 1 ; Cache type register
TST r5, #1<<31 ; EQ = ARMv6, NE = ARMv7+
SetFeatureEQ Rotated_loads
SetFeatureNE CP15_AIFSR
SetFeatureNE CP15_ADFSR
; IFAR is only guaranteed to be present on ARMv6T2+
[ InKernel :LAND: ("$Machine" = "RPi" :LOR: "$Machine" = "ARM11ZF")
SetFeature CP15_IFAR ; Cheeky hard-coding for Pi 1/ARM11ZF, which is pre-v6T2 but does have the register
|
SetFeatureNE CP15_IFAR ; v7+ has it
CMPEQ r4, #ARMvF ; v6 with feature registers?
MRCEQ p15, 0, r5, c0, c1, 0 ; ID_PFR0
ANDEQ r5, r5, #15<<4 ; State1
CMPEQ r5, #3<<4
SetFeatureEQ CP15_IFAR ; Thumb-2 implemented, i.e. v6T2
]
; Guess whether WFE does something useful by whether we're a multicore chip
MRC p15, 0, r5, c0, c0, 5 ; MPIDR
MRCEQ p15, 0, r6, c0, c0, 0 ; ARMv6: Register is optional, so compare value against MIDR to see if it's implemented. There's no multiprocessing extensions flag so assume the check against MIDR will be good enough.
......@@ -257,7 +274,9 @@ CalcCPUFeatures ROUT
TEQ r5, r6
SetFeatureNE WFE
; Detect instructions introduced by virtualisation extensions
MRC p15, 0, r5, c0, c1, 1 ; ID_PFR1
CMP r4, #ARMvF
MOVNE r5, #0
MRCEQ p15, 0, r5, c0, c1, 1 ; ID_PFR1
TST r5, #15<<12 ; ARMv7
SetFeatureNE HVC
TSTEQ r5, #15<<24 ; ARMv8
......@@ -361,16 +380,15 @@ PlatFeatSWI_ReadCPUFeatures ROUT
|
ADR r0, CPUFeatures
]
ASSERT CPUFeatures_Size == 8
LDMIA r0, {r0-r1}
ASSERT CPUFeature_Max >= 32
ASSERT CPUFeatures_Size == 12
LDMIA r0, {r0-r2}
ASSERT CPUFeature_Max >= 64
MOV r4, #-1
ASSERT CPUFeature_Max <= 64
LDR r5, =&ffffffff :SHR: (64 - CPUFeature_Max)
MOV r5, #-1
ASSERT CPUFeature_Max <= 96
LDR r6, =&ffffffff :SHR: (96 - CPUFeature_Max)
25
MOV r2, #0
MOV r3, #0
MOV r6, #0
MOV r7, #0
30
Pull "lr"
......
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