GitLab

Detail:
  Makefile - now exports a C version of hdr.OSEntries
Admin:
  Tested in Iyonix ROM softload.
  Needed for latest USB drivers to build.


Version 5.35, 4.79.2.112. Tagged as 'Kernel-5_35-4_79_2_112'

Detail:
  A fair number of bus/device types and IDs have been added to the Cortex branch since the branch was created.
  Now that the ClearIRQ entry has also been added, it's about time that the HAL branch was brought up to date.
Admin:
  Untested, but should be fine.


Version 5.35, 4.79.2.111. Tagged as 'Kernel-5_35-4_79_2_111'

Detail:
  s/PMF/i2cutils - Although the code will detect the Philips RTC correctly, it was failing to set the device size in R4, causing CMOS RAM to be misread. This change fixes that.
Admin:
  Tested in IOMD HAL build on development version of RPCEmu.


Version 5.35, 4.79.2.110. Tagged as 'Kernel-5_35-4_79_2_110'

Fix bug in InitCMOSCache that could cause CMOS to be errouneously reset if NVRAM is of type 'MaybeIIC'

Detail:
  s/PMF/i2cutils - Kernel was checking if the full IIC flags word was equal to MaybeIIC instead of just checking if the Provision bits equalled MaybeIIC. Thus if any of the additional flags were set along with MaybeIIC the kernel would have skipped the probing code, skipped the IIC code, and fallen through to using the (likely unimplemented) HAL interface for initialising the NVRAM cache.
Admin:
  Tested in IOMD build under RPCemu; kernel now takes the correct path for MaybeIIC + ProtectAtEnd.


Version 5.35, 4.79.2.109. Tagged as 'Kernel-5_35-4_79_2_109'

Version 5.35, 4.79.2.108. Tagged as 'Kernel-5_35-4_79_2_108'

Also upissued to RISC OS 5.16 to release this in ROM
Detail:
  (list files and functions that have changed)
Admin:
tested at Castle (JB)
  (highlight level of testing that has taken place)
  (bugfix number if appropriate)


Version 5.35, 4.79.2.107. Tagged as 'Kernel-5_35-4_79_2_107'

Detail:
  OS_SetVarVal was failing to call XOS_SynchroniseCodeAreas after copying the code variables code block into the system heap. This has now been fixed.
Admin:
  Fix tested in Cortex branch on rev C2 beagleboard. Debugger module now shows the right register names instead of ofla!


Version 5.35, 4.79.2.106. Tagged as 'Kernel-5_35-4_79_2_106'

Detail:
  Hdr:Macros has just been changed on the trunk in such a way that you now
  need to include Hdr:CPU.Arch as well. Previously this include file was only
  referenced by the Cortex branch kernel - now mirrored on the HAL branch
  kernel too.
Admin:
  Verified that IOMD ROM now builds again - should fix Tungsten ROM build too.

Version 5.35, 4.79.2.105. Tagged as 'Kernel-5_35-4_79_2_105'

Detail:
  s/ChangeDyn - Swap CMP with TEQ to avoid accidental clobbering of V flag before its state is checked on return from a SWI. Errors encounterd during sparse dynamic area resize operations (OS_DynamicArea 9 & 10) should now be reported properly.
Admin:
  Not tested, but the same fix has been proven to work on the Cortex branch.


Version 5.35, 4.79.2.104. Tagged as 'Kernel-5_35-4_79_2_104'

Detail:
  Noted reservation of IO controller type  passed to OS_Memory 9 used when
  system is running as a coprocessor. Not used by current code but we need to
  make sure that any future reservations use different numbers.
Admin:
  No functional change. Brought to our attention by Rob Sprowson.

Version 5.35, 4.79.2.103. Tagged as 'Kernel-5_35-4_79_2_103'

Detail:
  Some users reported problems building the sources if they had other
  installations of perl on their build machine. The build system was using a
  mixture of "perl" and "<Perl$Dir>.perl" to invoke the interpreter, and
  sometimes but not always using "do" to expand system variables on the
  command line. This has now been standardised to use "do <Perl$Dir>.perl in
  all cases, and where possible, to use the makefile macro ${PERL}.
Admin:
  Checked that a Tungsten build still works on a build machine with no other
  perl installation. "perl" was aliased to an error to ensure it wasn't used.

Version 5.35, 4.79.2.102. Tagged as 'Kernel-5_35-4_79_2_102'

Detail:
  Castle seems to have settled on an official 5.14 build, so changed our
  version to distinguish our test builds from the official one.
Admin:
  No testing required

Version 5.35, 4.79.2.101. Tagged as 'Kernel-5_35-4_79_2_101'

Detail:
    Version file updated
Admin:
    John Ballance, Castle

Version 5.35, 4.79.2.100. Tagged as 'Kernel-5_35-4_79_2_100'

Detail:
  Error number &1F3 allocated.
Admin:
  Requires HdrSrc 1.63.
  Fix supplied by Rob Sprowson.

Version 5.35, 4.79.2.99. Tagged as 'Kernel-5_35-4_79_2_99'

Detail:
  * Added some documentation on previously undocumented HAL calls
  * Corrected NVMemoryFlag_Provision bitmask to match documentation
  * Bugfix: NVMemoryFlag_ProtectAtEnd flag was being ignored
Admin:
  Not tested

Version 5.35, 4.79.2.98. Tagged as 'Kernel-5_35-4_79_2_98'

Version 5.35, 4.79.2.97. Tagged as 'Kernel-5_35-4_79_2_97'

Detail:
  Updated GraphicsV documentation
  Upped ROM version number - currently matches latest Castle release (5.13)
Admin:
  No code change

Version 5.35, 4.79.2.96. Tagged as 'Kernel-5_35-4_79_2_96'

Detail:

Admin:


Version 5.35, 4.79.2.95. Tagged as 'Kernel-5_35-4_79_2_95'

Detail:
Admin:


Version 5.35, 4.79.2.94. Tagged as 'Kernel-5_35-4_79_2_94'

Detail:

Admin:	needed for changed module


Version 5.35, 4.79.2.93. Tagged as 'Kernel-5_35-4_79_2_93'

Detail:

Admin:


Version 5.35, 4.79.2.92. Tagged as 'Kernel-5_35-4_79_2_92'

	no other changes
Detail:
Admin:


Version 5.35, 4.79.2.91. Tagged as 'Kernel-5_35-4_79_2_91'

OS_ReadSysInfo 6 (subreason code is 23 for IRQsema). This will
be useful if zero page is ever protected and the IRQ semaphore
moved.

Version 5.35, 4.79.2.90. Tagged as 'Kernel-5_35-4_79_2_90'

Detail:
  Internationalisation of *Help code (ie probably dating back to RISC OS 3.1)
  broke the Escape condition checking. This is particularly nasty if you
  do *Help . on a machine with slow hardware scrolling!
Admin:
  Not tested.

Version 5.35, 4.79.2.89. Tagged as 'Kernel-5_35-4_79_2_89'

Detail:
Admin:


Version 5.35, 4.79.2.88. Tagged as 'Kernel-5_35-4_79_2_88'

Version 5.35, 4.79.2.87. Tagged as 'Kernel-5_35-4_79_2_87'

Detail:
Admin:


Version 5.35, 4.79.2.86. Tagged as 'Kernel-5_35-4_79_2_86'

Version 5.35, 4.79.2.85. Tagged as 'Kernel-5_35-4_79_2_85'

Version 5.35, 4.79.2.84. Tagged as 'Kernel-5_35-4_79_2_84'

Detail:
  Tightened up BBE resources export, to exclude in appropriate files (this
  component has a non-standard resources directory structure).
Admin:
  Tested in a Tungsten BBE build.

Retagged, since this won't affect any existing builds.

Detail:
Admin:


Version 5.35, 4.79.2.83. Tagged as 'Kernel-5_35-4_79_2_83'

Detail: Kevin work, in response to D Ellis fault find
Admin:
      Castle IP


Version 5.35, 4.79.2.82. Tagged as 'Kernel-5_35-4_79_2_82'

     1: default ticker based vsync generated whenever no device present to do so
     2: graphicsv handling and spec updated to use the hi 8 bits in the
        reason code (R4) to define the display number. Kernel only knows
        of display 0
Detail:
Admin:
     tested castle  castle added ip


Version 5.35, 4.79.2.81. Tagged as 'Kernel-5_35-4_79_2_81'

Detail:
Admin:


Version 5.35, 4.79.2.80. Tagged as 'Kernel-5_35-4_79_2_80'

        HAL_Video_IIC_Op
Detail:
Admin:
     JB  Castle IP

Version 5.35, 4.79.2.79. Tagged as 'Kernel-5_35-4_79_2_79'

Detail:
  * I noticed in passing that the default exception handlers were broken for
    non-IOMD machines if the exception was raised in FIQ mode - unless you
    had a very large application slot, then the machine would lock up. Now
    properly HAL-ised.
  * Added a new event number, allocated for PRISM use back in June.
Admin:
  Not tested. However, it can't make the situation any worse!

Version 5.35, 4.79.2.78. Tagged as 'Kernel-5_35-4_79_2_78'

Detail:
  Previously, UnthreadV was only called when the IRQsema chain was empty, the
  link for the just-completed interrupt having just been removed. However,
  the information in the link is necessary to allow OS_Heap to be called from
  UnthreadV context, and patching up IRQsema within the UnthreadV handler
  prevents the implementation of a prioritised threading scheme. As a result,
  we must call UnthreadV every time the interrupt dispatch unthreads, and
  leave it up to the UnthreadV handler to distinguish between return to
  thread context and return from a nested interrupt handler.
Admin:
  Will require some sort of patch to enable heap-safe prioritised threading
  on RISC OS-STB 5.0.0 or RISC OS 5.07, the only two released OSes with the
  previous UnthreadV behaviour.

Version 5.35, 4.79.2.77. Tagged as 'Kernel-5_35-4_79_2_77'

Detail:
Admin:
  castle IP


Version 5.35, 4.79.2.76. Tagged as 'Kernel-5_35-4_79_2_76'

   Tungsten HAL IIC_Transfer not initialising the checksum
Detail:

Admin:
   tested at castle.. again!
   castle added IP


Version 5.35, 4.79.2.75. Tagged as 'Kernel-5_35-4_79_2_75'

Detail:
   CheckSumBlock called IIC_OpV to checksum byte 0 of CMOS, but read back the
   resultant checksum from the wrong offset (#20.. new R1 value)..  now
   corrected to #24 as the correct offset (approx line 997).

Admin:
   tested at castle in iyonix
   castle added IP


Version 5.35, 4.79.2.74. Tagged as 'Kernel-5_35-4_79_2_74'