1. 22 Oct, 2009 1 commit
    • Jeffrey Lee's avatar
      Fix error handling for sparse dynamic area resize operations, increase Cortex... · 04f4e5cd
      Jeffrey Lee authored
      Fix error handling for sparse dynamic area resize operations, increase Cortex kernel version number to 5.15
        s/ChangeDyn - Swap CMP with TEQ to avoid accidental clobbering of V flag before its state is checked on return from a SWI. Errors encountered during sparse dynamic area resize operations (OS_DynamicArea 9 & 10) should now be reported properly.
        Version - Update kernel version/date to 5.15, to match current HAL version. This change is to allow modules to properly detect whether the kernel has the sparse dynamic area fix - it does not (yet) mean that the Cortex kernel contains all the features of the current development HAL kernel!
        Tested on rev C2 beagleboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_14'
  2. 30 Sep, 2009 1 commit
    • Jeffrey Lee's avatar
      Update Cortex kernel to cope correctly with HAL RTC errors · d08aa9dc
      Jeffrey Lee authored
        The kernel will now attempt to cope with errors returned by HAL RTC devices - For RTC read operations, instead of just loading random garbage, the bad result will now be ignored and the soft 5-byte time left unaltered.
        Tested on rev C2 beagleboard. Year now correctly defaults to 1970 instead of 1900 if the OMAP3 RTC driver returns an error because the RTC isn't running yet.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_13'
  3. 06 Sep, 2009 1 commit
    • Jeffrey Lee's avatar
      Disable DebugTerminal by default for OMAP3 kernel · a44eed24
      Jeffrey Lee authored
        The host-mode driver for the MUSB OTG controller is now working, so there's no longer any reason to have the DebugTerminal enabled by default.
        Tested on rev C2 beagleboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_12'
  4. 23 Jul, 2009 1 commit
    • Jeffrey Lee's avatar
      Add HAL RTC support to Cortex branch of kernel, clean up RTCSupport code · 7f21e480
      Jeffrey Lee authored
        HAL kernels (on the Cortex branch at least) now support HALDevice-based RTCs. If the kernels own RTC code is disabled or fails to detect an RTC, then after HAL_InitDevices is called the HALDevice list will be scanned for any HAL-resident RTC devices.
        Additionally, the RTCSupport flag (in Hdr:Machine.Machine), which was previously TRUE for all HAL kernels, can now be set to FALSE in HAL kernels to disable the kernels own IIC RTC code. This allows the unwanted legacy RTC code to be disabled for machines which are known to use HAL RTCs instead.
        hdr/RTCDevice - new header describing data structures used for HAL RTC device
        hdr/HALDevice - added RTCDevice device type, IIC serial bus type
        hdr/KernelWS - upgraded RTCFitted from a 1 byte field to 4 byte. It now stores either a null value (for no RTC), a value <2048 for an IIC RTC address, or a value >= 2048 for a RTCDevice ptr
        Makefile - added header export of hdr/RTCDevice
        s/GetAll - include hdr/RTCDevice
        s/NewReset - initialise HAL RTC after HAL_InitDevices if required
        s/PMF/i2cutils, s/PMF/osinit, s/PMF/osword - modifications to allow use of HAL RTC (and disallow use of builtin IIC RTC)
        Tested on rev C2 beagleboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_11'
  5. 17 Jul, 2009 1 commit
  6. 15 Jun, 2009 1 commit
    • Ben Avison's avatar
      Fix bugs and inefficiencies revealed by unaligned data audit · 8a9e694c
      Ben Avison authored
        s.PMF.i2cutils line 454: this LDR of byte values was harmless (bits 8
          upwards are discarded later) but slower than an LDRB on ARMv6 or later.
        s.PMF.i2cutils line 556: should have loaded RTCFitted using LDRB. Looks
          like effect would have been to reduce utilisation of CMOS cache.
        s.vdu.vduswis line 1500: mistakenly accessing ExternalFramestore using LDR.
          I don't think the intention was to prevent the screen DA being resized
          while screen memory was claimed, but that was the effect.
        s.vdu.vduwrch line 3106: this LDR of a 1-byte variable was harmless (only
          used for testing bit 4) but slower than an LDRB on ARMv6 or later.
        CPU version is no longer specified in the makefile - it's better to inherit
        it from the build environment now that we actually set it appropriately.
        Built and briefly tested.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_9'
  7. 17 May, 2009 1 commit
    • Ben Avison's avatar
      Miscellaneous v6-related updates · 9d9aa41b
      Ben Avison authored
       * Stopped calling the broken abort fixup code when running under VMSAv6.
         Might be desirable to update it, possibly farmed out to a separate module -
         still need to think about this.
       * Unaligned load optimisations can now be disabled by the global NoUnaligned
         flag for testing purposes.
       * Extended OS_ReadUnsigned to permit reading of 64-bit unsigned integers.
         See Docs.ReadUnsigned for more details. Also sped it up by using MLA
         (or UMLAL) for most digits rather than repeated addition.
       * Bugfix is OS_GSRead: an uninitialised r0 was being passed to
         OS_ReadUnsigned, causing undesirable effects on rare occasions.
        Tested on a rev B7 beagleboard.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_8'
  8. 10 May, 2009 3 commits
    • Jeffrey Lee's avatar
      Disable paged scrolling when using the debug terminal · 76cbfa84
      Jeffrey Lee authored
        s/vdu/vduwrch - Modify PageTest to never use paged scrolling when DebugTerminal is true (since serial terminals aren't able to send shift up/down messages)
        Tested on rev C2 beagleboard.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_7'
    • Ben Avison's avatar
      Unaligned loads/stores optimised for ARMv6+ · 70865f8b
      Ben Avison authored
        Having scanned the kernel source for unaligned load code fragments which
        would abort on ARMv6 and v7 and not having found any, I took the opportunity
        to give them build-time switches to use unaligned LDR((S)H)/STR(H)
        instructions if built for a new enough platform. Also added a couple of
        cases of LDRSB that will benefit v4 CPUs and a few instances of the v6
        SXTH instruction, but since objasm doesn't yet understand it (and when it
        does, not everyone will have upgraded) they are currently written as
        DCI statements.
        Most of the changes are to OS_Word handlers, which are notorious in that
        their input/output block is not word-aligned.
        Not tested, but it should at least build.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_6'
    • Jeffrey Lee's avatar
      Assorted kernel fixes for ARMv6/ARMv7 · ca8f36f5
      Jeffrey Lee authored
        s/ARMops - Fix IMB_Range_WB_CR7_Lx to clean the correct number of cache lines
        s/HAL - Change CP15 control register flags so unaligned loads are enabled on ARMv6 (to simplify support for ARMv7 where unaligned loads are always enabled, and to match the behaviour expected by the example code in Hdr:CPU.Arch)
        s/AMBControl/memmap - Make AMB_LazyFixUp use the correct L2PT protection flags depending on ARM600/VMSAv6 MMU model. Also guard against problems caused by future L2PT flag changes.
        s/vdu/vdugrafj - Fix previously undiscovered 32bit incompatability in GetSprite (OS_SpriteOp 14/16)
        Tested on rev C2 beagleboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_5'
  9. 23 Apr, 2009 1 commit
    • Jeffrey Lee's avatar
      Fix kernel cache clean/invalidate operations for Cortex CPUs · d28235ea
      Jeffrey Lee authored
        s/ARMops - Fix set/way-based cache ops for cache type WB_CR7_Lx to iterate sets/ways/cache levels properly
        s/HAL - Fix HAL_InvalidateCache_ARMvF to iterate sets/ways/cache levels properly
        Tested on rev C2 beagleboard
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_4'
  10. 06 Mar, 2009 1 commit
    • Jeffrey Lee's avatar
      Add VMSAv6 MMU support, fixes to allow booting on beagleboard · 3d1317e7
      Jeffrey Lee authored
        s/ARM600 - fix to SyncCodeAreasRange to correctly read cache line length for WB_CR7_Lx caches
        s/ARMops - Cortex cache handling fixes. Enable L2 cache for Cortex.
        s/ChangeDyn - VMSAv6 support in AllocateBackingLevel2
        s/HAL - Improve RISCOS_InitARM to set/clear correct CP15 flags for ARMv6/v7. VMSAv6 support in code to generate initial page tables.
        s/NewReset - Extra DebugTX calls during OS startup. Disable pre-HAL Processor_Type for HAL builds.
        s/VMSAv6 - Main VMSAv6 MMU code - stripped down version of s/ARM600 with support for basic VMSAv6 features.
        hdr/Options - Use VMSAv6 MMU code, not ARM600. Disable ARM6support since current VMSAv6 code will conflict with it.
        Tested basic OS functionality under qemu-omap3 and revision B6 beagleboard.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_3'
  11. 21 Feb, 2009 1 commit
    • Jeffrey Lee's avatar
      Add support for Cortex cache type. Extend ARM_Analyse to, where appropriate,... · ad9cdf41
      Jeffrey Lee authored
      Add support for Cortex cache type. Extend ARM_Analyse to, where appropriate, use CPU feature registers to identify CPU capabilities.
        s/ARMops - Support for Cortex multi-level cache (CT_ctype_WB_CR7_Lx). New ARM_Analyse_Fancy to identify CPU capabilities using feature registers.
        s/HAL - Modify pre-ARMop cache code to handle Cortex-syle caches.
        s/MemInfo - Replace ARM_flush_TLB macro call with appropriate ARMop to provide Cortex compatability
        hdr/ARMops - Update list of ARM architectures
        hdr/CoPro15ops - Deprecate ARM_flush_* macros for HAL kernels, as they are no longer capable of flushing all cache types. ARMops should be used instead.
        hdr/KernelWS - Add storage space for multi-level cache properties required for new cache cleaning code.
        Tested under qemu-omap3. Still unable to verify on real hardware due to lack of appropriate MMU code. However new OMAP3 HAL code that uses similar cache management functions appears to work fine on real hardware.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_2'
  12. 01 Feb, 2009 1 commit
    • Jeffrey Lee's avatar
      Initial kernel support for Cortex-A8 processors. · e2262380
      Jeffrey Lee authored
        hdr/ARMops - Added Cortex_A8 processor type, new ARM architecture number
        hdr/Options - Enabled various kernel debug options
        s/ARMops - Added Cortex-A8/OMAP3530 to known CPUs list. Ignore cache type register for ARM architecture &F.
        s/NewIRQs - Increase MaxInterrupts to 96
        Brief testing under qemu-omap3.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98_2_1'
  13. 22 Dec, 2008 1 commit
    • Ben Avison's avatar
      Minor kernel updates · ab08ee91
      Ben Avison authored
        * Added some documentation on previously undocumented HAL calls
        * Corrected NVMemoryFlag_Provision bitmask to match documentation
        * Bugfix: NVMemoryFlag_ProtectAtEnd flag was being ignored
        Not tested
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_98'
  14. 03 Dec, 2008 1 commit
  15. 04 Oct, 2008 1 commit
    • Ben Avison's avatar
      Merged in changes from Castle · ffe4d1b4
      Ben Avison authored
        Updated GraphicsV documentation
        Upped ROM version number - currently matches latest Castle release (5.13)
        No code change
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_96'
  16. 22 Feb, 2006 1 commit
  17. 16 Feb, 2006 1 commit
  18. 07 Oct, 2005 1 commit
  19. 24 Sep, 2005 1 commit
  20. 23 Sep, 2005 1 commit
  21. 16 Sep, 2005 1 commit
  22. 15 Sep, 2005 1 commit
    • Ben Avison's avatar
      Bugfix to *Help. · 82d4de44
      Ben Avison authored
        Internationalisation of *Help code (ie probably dating back to RISC OS 3.1)
        broke the Escape condition checking. This is particularly nasty if you
        do *Help . on a machine with slow hardware scrolling!
        Not tested.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_89'
  23. 12 Sep, 2005 1 commit
  24. 09 Jun, 2005 1 commit
  25. 18 May, 2005 1 commit
  26. 04 May, 2005 1 commit
  27. 21 Mar, 2005 1 commit
  28. 12 Nov, 2004 1 commit
    • Ben Avison's avatar
      BBE tidying. · ec70a1a4
      Ben Avison authored
        Tightened up BBE resources export, to exclude in appropriate files (this
        component has a non-standard resources directory structure).
        Tested in a Tungsten BBE build.
      Retagged, since this won't affect any existing builds.
  29. 04 Nov, 2004 2 commits
  30. 02 Nov, 2004 1 commit
    • John Ballance's avatar
      several mode: · 208da9fd
      John Ballance authored
           1: default ticker based vsync generated whenever no device present to do so
           2: graphicsv handling and spec updated to use the hi 8 bits in the
              reason code (R4) to define the display number. Kernel only knows
              of display 0
           tested castle  castle added ip
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_81'
  31. 29 Oct, 2004 2 commits
  32. 13 Oct, 2004 1 commit
    • Ben Avison's avatar
      Bugfix and header change. · 9a6346d8
      Ben Avison authored
        * I noticed in passing that the default exception handlers were broken for
          non-IOMD machines if the exception was raised in FIQ mode - unless you
          had a very large application slot, then the machine would lock up. Now
          properly HAL-ised.
        * Added a new event number, allocated for PRISM use back in June.
        Not tested. However, it can't make the situation any worse!
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_78'
  33. 06 Oct, 2004 1 commit
    • Ben Avison's avatar
      Change to calling conditions of UnthreadV. · 5e89ff87
      Ben Avison authored
        Previously, UnthreadV was only called when the IRQsema chain was empty, the
        link for the just-completed interrupt having just been removed. However,
        the information in the link is necessary to allow OS_Heap to be called from
        UnthreadV context, and patching up IRQsema within the UnthreadV handler
        prevents the implementation of a prioritised threading scheme. As a result,
        we must call UnthreadV every time the interrupt dispatch unthreads, and
        leave it up to the UnthreadV handler to distinguish between return to
        thread context and return from a nested interrupt handler.
        Will require some sort of patch to enable heap-safe prioritised threading
        on RISC OS-STB 5.0.0 or RISC OS 5.07, the only two released OSes with the
        previous UnthreadV behaviour.
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_77'
  34. 08 Sep, 2004 2 commits
  35. 06 Sep, 2004 1 commit
    • John Ballance's avatar
      fix for invalid cmos checksum computation on iyonix new version date for 5.07 · 83827e89
      John Ballance authored
         CheckSumBlock called IIC_OpV to checksum byte 0 of CMOS, but read back the
         resultant checksum from the wrong offset (#20.. new R1 value)..  now
         corrected to #24 as the correct offset (approx line 997).
         tested at castle in iyonix
         castle added IP
      Version 5.35, Tagged as 'Kernel-5_35-4_79_2_74'