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Commit e769c131 authored by Kevin Bracey's avatar Kevin Bracey
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RISC OS 3.71 kernel changes merged. 

Not fully tested on all hardware permutations.
parent b408edcc
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Showing with 121 additions and 27 deletions
s/KbdResPC
View file @ e769c131
......@@ -94,7 +94,7 @@ SetUpKbd
BEQ %FT30
|
LDRB R1, [R0, #IOMD_ID0] ;Are we running on Morris
CMP R1, #&98
CMP R1, #&E7
LDRB R1, [R0, #IOMD_ID1]
CMPEQ R1, #&5B
BNE %FT30 ;NE: no, assume IOMD, so only one PS2 port
......
s/Kernel
View file @ e769c131
......@@ -822,7 +822,14 @@ Do_CallBack ; CallBack allowed:
STR r14, [r12, #4*15] ; user PC
MOV r14, r12
Pull "r10-r12"
[ SASTMhatbroken
STMIA r14!,{r0-r12}
STMIA r14,{r13,r14}^ ; user registers
NOP
SUB r14,r14,#13*4
|
STMIA r14, {r0-r14}^ ; user registers
]
MOV R12, #CallAd_ws
LDMIA R12, {R12, PC} ; jump to CallBackHandler
......
s/Middle
View file @ e769c131
......@@ -246,15 +246,15 @@ SBRKPT ROUT
STMIA r12!, {r0}
MOV r0, r12
LDMFD sp, {r10-r12}
[ SAUBxferbroken
NOP
NOP
]
[ SASTMhatbroken
STMIA r0!,{r1-r12}
STMIA r0, {r13_usr,r14_usr}^ ; user mode case done.
SUB r0, r0, #12*4
|
STMIA r0, {r1-r12, r13_usr, r14_usr}^ ; user mode case done.
NOP
[ SAUBxferbroken
NOP
]
]
10 LDR stack, =SVCSTK
MOV r12, #BrkAd_ws
......@@ -389,15 +389,8 @@ EVENTH MOV pc, lr
NOCALL MOV r0, #0 ; default callback routine
LDR r14, [r0, #CallBf]
[ SAUBxferbroken
NOP
NOP
]
LDMIA r14, {r0-r12, r13_usr, r14_usr}^ ; load user's regs
NOP
[ SAUBxferbroken
NOP
]
LDR r14, [r14, #4*15]
MOVS pc, r14
......@@ -596,7 +589,13 @@ DumpyTheRegisters ROUT
LDR R1, [R0, -R0] ; PC when exception happened
STR R1, [R0, #(15-8)*4] ; In the right slot now ...
TST R1, #SVC_mode
[ SASTMhatbroken
STMEQIA R0!,{R8-R12}
STMEQIA R0, {R13,R14}^ ; user mode case done.
SUBEQ R0, R0, #5*4
|
STMEQIA R0, {R8-R14}^ ; user mode case done.
]
BEQ UNDEF1
TST R1, #1 ; SWI mode?
......
s/NewReset
View file @ e769c131
......@@ -294,7 +294,11 @@ VIDCTAB
; Program Control Register first, to clear power-down bit
[ VCOstartfix
& &E0000404 ; CR: FIFO load 16 words, 1 bpp, ck/2, vclk (allow for doubled VCO freq)
|
& &E0000400 ; CR: FIFO load 16 words, 1 bpp, ck/1, vclk
]
; Don't bother programming all 256 palette entries, we'll be here all night
; Since we're setting up a 1 bit-per-pixel mode, just do colours 0 and 1
......@@ -337,7 +341,11 @@ VIDCTAB
& &B1000001 ; SCR: sound disabled (+use 24MHz clock)
& &C00F1003 ; EREG = comp sync, DACs on, ereg output ext lut
[ VCOstartfix
& &D0000302 ; FSYNREG, clk = (3+1)/(2+1) * 24MHz = 32MHz (higher frequency as part of fix)
|
& &D0000305 ; FSYNREG, clk = (3+1)/(5+1) * 24MHz = 16MHz
]
& &F0013000 ; DCR: bus D[31:0], Hdisc ;RCM 29/9/94: changed from &F0012000 at PSwindells request
& &FFFFFFFF ; That's the lot
|
......@@ -500,6 +508,33 @@ Continue
MOV R0, #timer0_bit
STRB R0, [R1, #IOCIRQCLRA] ; Clear pending t0 interrupt j.i.c.
[ VCOstartfix
;2nd part of fix for VCO failing to start on A7000 (esp. 7500FE) - forcing PCOMP high for about 3 ms
LDRB R0, [R1,#IOMD_ID0]
CMP R0, #&E7
LDREQB R0, [R1,#IOMD_ID1]
CMPEQ R0, #&D4
BEQ vcofix_notMorris ; risky to force PCOMP on Risc PC
MOV R0, #VIDCPhys
LDR R2, =&D0000342 ; VIDC20 FSYNREG, as in VIDCTAB but with force PCOMP high
STR R2, [R0]
MOV R0, #3072*2 ; time delay of about 3 ms (0.5 us units)
STRB R0, [R1, #Timer0LR] ; copy counter into output latch
LDRB R2, [R1, #Timer0CL] ; R2 := low output latch
vcofix_waitloop
STRB R0, [R1, #Timer0LR] ; copy counter into output latch
LDRB R3, [R1, #Timer0CL] ; R3 := low output latch
TEQ R3, R2 ; unchanged ?
BEQ vcofix_waitloop ; then loop
MOV R2, R3 ; copy anyway
SUBS R0, R0, #1 ; decrement count
BNE vcofix_waitloop ; loop if not finished
MOV R0, #VIDCPhys
LDR R2, =&D0000302 ; VIDC20 FSYNREG, as in VIDCTAB (PCOMP low again)
STR R2, [R0]
vcofix_notMorris
]
; now size memory
BL MemSize ; out: r0 = page size, r1 = memory size, r2 = MEMC CR value, r3-r14 corrupt
......@@ -658,6 +693,9 @@ SetUpKbdReturn
ARMA_drain_WB
ARMA_flush_IC
vectorpoke_notSA_1
[ ARM810support
ARM8_branchpredict_flush ;IMB on ARM810, and harmless on other ARMs
]
]
BIC r0, r0, #I32_bit ; and enable IRQs
......@@ -857,6 +895,9 @@ conversionSWIfill
ARMA_drain_WB
ARMA_flush_IC
afterpokingaround_notSA
[ ARM810support
ARM8_branchpredict_flush ;IMB on ARM810, and harmless on other ARMs
]
]
; Initialise CAO ptr to none.
......@@ -1107,7 +1148,7 @@ not_full_reset
BEQ dont_program_mousetype
|
LDRB R0, [R8, #IOMD_ID0]
CMP R0, #&98
CMP R0, #&E7
LDRB R0, [R8, #IOMD_ID1]
CMPEQ r0, #&5B
BNE dont_program_mousetype
......@@ -1222,7 +1263,7 @@ DefaultCMOSTable ; list of non-zero options wanted :
= SoundCMOS, &F0 ; speaker on, volume 7, channel 1
= LanguageCMOS, ConfiguredLang
= YearCMOS, 95 ; changed from 93 to 95 on 12-Jan-95 to fix MED-04318
= YearCMOS, 97 ; changed from 95 to 97 on 02-Jan-97
= YearCMOS+1, 19
[ :LNOT: Select16BitSound
= TutuCMOS, 2_0100 ; tbs chars valid, ctrlchars '|x'
......@@ -2050,6 +2091,9 @@ CopyDefaultIRQ1V
ARMA_flush_IC
MOV r0,#0 ;restore r0 as zero base
furtherpoke_notSA
[ ARM810support
ARM8_branchpredict_flush ;IMB on ARM810, and harmless on other ARMs
]
]
[ CPU_Type = "ARM600"
......@@ -2146,7 +2190,9 @@ furtherpoke_notSA
SWI XOS_NewLine
]
SWI XOS_EnterOS ; switch back to SVC mode (IRQs, FIQs enabled)
[ RO371Timings
BL finalmemoryspeed
]
; end of added code
[ International ; Open the kernel messages file.
......@@ -2359,6 +2405,12 @@ processor_names
ALIGN 32
DCB "StrongARM Processor",10,13,10,0
ALIGN 32
[ MorrisIDString
DCB "ARM 7500 Processor",10,13,10,0
ALIGN 32
DCB "ARM 7500FE Processor",10,13,10,0
ALIGN 32
]
; type, internal type, features
]
cputable
......@@ -2367,7 +2419,17 @@ cputable
DCD &7000,2,0
DCD &7100,3,0
DCD &8100,4,2_11101
[ {TRUE}
;corrected for 3.71 (SA does not abort for vector reads in 26-bit mode)
DCD &a100,5,2_11011
|
;value for 3.70
DCD &a100,5,2_11111
]
[ MorrisIDString
DCD &7500,6,0
DCD &7501,7,0
]
DCD -1
]
......@@ -2378,11 +2440,30 @@ MessageFileName DCB "Resources:$.Resources.Kernel.Messages",0
[ StrongARM
Processor_Type
[ MorrisIDString
MOV r0,#IOMD_Base
LDRB r1,[r0,#IOMD_ID0]
CMP r1,#&E7
LDRB r1,[r0,#IOMD_ID1]
CMPEQ r1,#&D4
BEQ PT_RiscPC ; E7,D4 means Risc PC
CMP r1,#&5B
MOVEQ r0,#&7500 ; 5B means 7500
BEQ PT_lookup
CMP r1,#&AA
MOVEQ r0,#&7500
ORREQ r0,r0,#&0001 ; AA means 7500FE - mark as 7501
BEQ PT_lookup
PT_RiscPC
]
ReadCop R0,CR_ID ; see data sheets for values
; ARM 600 funny
TST R0,#&f000
MOVEQ R0,R0, LSL #4
AND R0,R0,#&ff00
[ MorrisIDString
PT_lookup
]
ADR R1,cputable
66
LDR R2,[R1],#4
......
s/PMF/osinit
View file @ e769c131
......@@ -616,7 +616,7 @@ ReadMachineType ENTRY "r0-r12"
TEQ r11, #IOST_7500 ; and set EQ if Morris to do conditional stuff below
|
LDRB r0, [r12, #IOMD_ID0]
CMP r0, #&98
CMP r0, #&E7
LDRB r0, [r12, #IOMD_ID1]
CMPEQ r0, #&5B
MOVEQ r11, #IOST_7500 ;EQ, Morris
......
s/vdu/vdudriver
View file @ e769c131
......@@ -1017,11 +1017,11 @@ DbgFilename
[ MorrisSupport
; MOV R10, #IOMD_Base
; LDRB R9, [R10, #IOMD_ID0]
; CMP R9, #&98
; CMP R9, #&E7
; LDRB R9, [R10, #IOMD_ID1]
; CMPEQ R9, #&5B
; MOVEQ R9, #32000 ;Morris clocks VIDC20L at 32Mhz
; LDRNE R9, =24000 ;RISC PC clocks VIDC20 at 24MHz
; CMPEQ R9, #&D4
; MOVNE R9, #32000 ;Morris clocks VIDC20L at 32Mhz
; LDREQ R9, =24000 ;RISC PC clocks VIDC20 at 24MHz
MOV R9, #0
LDRB R9, [R9, #IOSystemType]
TST R9, #IOST_7500
......@@ -1935,11 +1935,11 @@ ProcessVIDCListType3 ROUT
[ MorrisSupport
; MOV R14, #IOMD_Base
; LDRB R1, [R14, #IOMD_ID0]
; CMP R1, #&98
; CMP R1, #&E7
; LDRB R1, [R14, #IOMD_ID1]
; CMPEQ R1, #&5B
; MOVEQ R1, #32000 ;Morris clocks VIDC20L at 32Mhz
; LDRNE R1, =24000 ;RISC PC clocks VIDC20 at 24MHz
; CMPEQ R1, #&D4
; MOVNE R1, #32000 ;Morris clocks VIDC20L at 32Mhz
; LDREQ R1, =24000 ;RISC PC clocks VIDC20 at 24MHz
MOV R1, #0
LDRB R1, [R1, #IOSystemType]
TST R1, #IOST_7500
......@@ -2357,8 +2357,15 @@ ComputeModuli ENTRY "r2-r12", ComputeModuliStack
LDR r5, [r2, #BestVInRange - BestDInRange] ; r5 = Best V
SUBS r4, r4, #1 ; values in FSyn are n-1
[ VCOstartfix
;do *not* do the very slow trick - this will stall the VCO and it may not restart
;properly later (we don't give a fig for power consumption)
MOVEQ r4, #3
MOVEQ r5, #8 ; after sub below, (7+1)/(3+1) so VCO runs at twice ref clock
|
MOVEQ r4, #63 ; if R=V=1 then use max R
MOVEQ r5, #2 ; and min V to make VCO go really slow
]
SUB r5, r5, #1 ; for both v and r
ASSERT FSyn_RShift = 0
......
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