Commit 3e9f9f3a authored by ROOL's avatar ROOL 🤖
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This commit was manufactured by cvs2git to create tag 'Kernel- 5_35-4_79_2_60'.

Sprout from HAL 2003-04-15 20:18:37 UTC Kevin Bracey <kbracey@gitlab.riscosopen.org> 'Version increased to dizzy 5.03'
Delete:
    Docs/HAL/ADisNote
    Docs/HAL/ARMop_API
    Docs/HAL/Entries
    Docs/HAL/HAL_API
    Docs/HAL/Init
    Docs/HAL/MoreEnts
    Docs/HAL/NewAPI
    Docs/HAL/NewCDV
    Docs/HAL/Notes
    Docs/HAL/OS_Hardware
    Docs/HAL/OpenBusAdapter
    Docs/HAL/Serial
    Docs/MemMaps/+Access,ffd
    Docs/MemMaps/+SrcIndex
    Docs/MemMaps/+SrcIndexO
    Docs/MemMaps/130
    Docs/MemMaps/258
    Docs/PrivDoc/+Access,ffd
    Docs/PrivDoc/+SrcIndex
    Docs/PrivDoc/+SrcIndexO
    Docs/PrivDoc/5thColumn/+Access,ffd
    Docs/PrivDoc/5thColumn/+SrcIndex
    Docs/PrivDoc/5thColumn/+SrcIndexO
    Docs/PrivDoc/5thColumn/Concept
    Docs/PrivDoc/MMPM
    Docs/PrivDoc/ScreenMode
    NewModes/Make,feb
    NewModes/NEWF2
    NewModes/NEWFORMAT
    NewModes/OldFormat
    NewModes/OldPSSrc
    NewModes/OldToNew,ffb
    NewModes/PSSrc
    Resources/UK/CmdHelp
    Resources/UK/Messages
    Resources/UK/Morris4/Messages
    Resources/UK/Omega/Messages
    Resources/UK/Ursula/Messages
    TestSrc/A600tlb
    TestSrc/Arm3
    TestSrc/Begin
    TestSrc/Cmos
    TestSrc/ErrorCount,ffb
    TestSrc/ExtCmd
    TestSrc/ExtIO
    TestSrc/InitModule
    TestSrc/Ioc
    TestSrc/LEDDelay
    TestSrc/MEMC1
    TestSrc/Mem1IOMD
    TestSrc/Mem1MEMC1
    TestSrc/Mem2
    TestSrc/Mem3
    TestSrc/Mem4
    TestSrc/Mem5
    TestSrc/ROMCard
    TestSrc/ShowIOMDRs
    TestSrc/TestMain
    TestSrc/ToggleLED
    TestSrc/Vidc
    h/HALDevice
    hdr/ARMops
    hdr/Copro15ops
    hdr/EnvNumbers
    hdr/ExportVals/!HowTo
    hdr/ExportVals/Makefile
    hdr/ExportVals/Mk,fd7
    hdr/ExportVals/s/GetVals
    hdr/ExportVals/values
    hdr/HALDevice
    hdr/HALEntries
    hdr/KernelWS
    hdr/KeyWS
    hdr/ModHand
    hdr/OSEntries
    hdr/Old/Arthur/PublicWS
    hdr/Old/Arthur/Space200
    hdr/Old/NewSpace
    hdr/Old/VickySpace
    hdr/Options
    hdr/PublicWS
    hdr/RISCOS
    hdr/Variables
    hdr/VduExt
    s/AMBControl/AMB
    s/AMBControl/Memory
    s/AMBControl/Options
    s/AMBControl/Workspace
    s/AMBControl/allocate
    s/AMBControl/deallocate
    s/AMBControl/growp
    s/AMBControl/growshrink
    s/AMBControl/main
    s/AMBControl/mapslot
    s/AMBControl/mapsome
    s/AMBControl/memmap
    s/AMBControl/readinfo
    s/AMBControl/service
    s/AMBControl/shrinkp
    s/ARM600
    s/ARMops
    s/Arthur2
    s/Arthur3
    s/ArthurSWIs
    s/ChangeDyn
    s/Convrsions
    s/End
    s/ExtraSWIs
    s/FlashROM
    s/GetAll
    s/HAL
    s/HeapMan
    s/HeapSort
    s/KbdResA1
    s/KbdResPC
    s/KbdResRCMM
    s/Kernel
    s/LibKern
    s/MEMC1
    s/MEMC2
    s/MOSDict
    s/MemInfo
    s/Middle
    s/ModHand
    s/MoreComms
    s/MoreSWIs
    s/Morris
    s/MsgCode
    s/NewIRQs
    s/NewReset
    s/Oscli
    s/PMF/Buffer
    s/PMF/Def
    s/PMF/IIC
    s/PMF/Internat
    s/PMF/KbdDrA1
    s/PMF/convdate
    s/PMF/i2cutils
    s/PMF/key
    s/PMF/mouse
    s/PMF/osbyte
    s/PMF/oseven
    s/PMF/osinit
    s/PMF/osword
    s/PMF/oswrch
    s/PMF/realtime
    s/SWINaming
    s/Super1
    s/SysComms
    s/TickEvents
    s/UnSqueeze
    s/Utility
    s/vdu/vdu23
    s/vdu/vdu5
    s/vdu/vducursoft
    s/vdu/vdudecl
    s/vdu/vdudriver
    s/vdu/vdufont
    s/vdu/vdufontl1
    s/vdu/vdugrafa
    s/vdu/vdugrafb
    s/vdu/vdugrafc
    s/vdu/vdugrafd
    s/vdu/vdugrafdec
    s/vdu/vdugrafe
    s/vdu/vdugraff
    s/vdu/vdugrafg
    s/vdu/vdugrafh
    s/vdu/vdugrafi
    s/vdu/vdugrafj
    s/vdu/vdugrafk
    s/vdu/vdugrafl
    s/vdu/vdugrafv
    s/vdu/vduhint
    s/vdu/vdumodes
    s/vdu/vdupal10
    s/vdu/vdupal20
    s/vdu/vdupalette
    s/vdu/vdupalxx
    s/vdu/vduplot
    s/vdu/vdupointer
    s/vdu/vduswis
    s/vdu/vduttx
    s/vdu/vduwrch
parent e187fb9f
directory
5thColumn 1000 0 Mike_Stephens 2e05be22 30fd2d55 0
MMPM fff 1 Mike_Stephens 2c53f7f8 31060a6b 0
ScreenMode fff 1 Mike_Stephens 2c4d19fc 31060a6b 0
File deleted
directory
Concept fff 0 Mike_Stephens 27ad92e9 31060a69 0
directory
Concept fff 1 Mike_Stephens 27ad92e9 31060a69 0
; > 5thColumn.Concept
RISC OS Support for extension ROMs
==================================
Author: Tim Dobson
Status: Draft
Issue: 0.02
History:
Date Revision Changes
11-Oct-90 0.00 Started
16-Oct-90 0.01 Completed first draft
04-Feb-91 0.02 Updated to reflect reality
This document describes the purpose of the extension ROM system and
discusses various design issues. For the full technical documentation, refer
to the document "5thColumn.Manual".
The extension ROM system allows the development of hardware platforms fitted
with a normal 32 bit wide RISC OS ROM set plus one or more 8, 16 or 32 bit
ROMs or EPROMs containing software modules which add to or replace modules
in the main ROM set. This allows the same main ROM set to be used in a wider
variety of hardware platforms, removing the extra cost and lead times of
re-romming, and possibly reducing costs by allowing bulk purchase of the
main ROM set.
The extension ROM(s) appear in the memory map in unused parts of the low
(&03400000 to &037FFFFF) or high (&03800000 to &03FFFFFF) ROM areas. A 32
bit wide extension ROM set is directly executable in place, saving on user
RAM. 8 or 16 bit wide sets have to be copied into RAM to execute. By using
the low ROM area (whose access time is programmable independently from the
high area containing the main ROM set) slow EPROMs can be used.
A particularly attractive configuration might be to have 8 ROM sockets on
the board, 4 for the main ROM set, and the other 4 capable of taking either
one 32 bit wide set (eg a large set of applications eg Internet) or up to 4
individual 8 bit wide ROMs containing smaller applications or utilities.
The scheme also allows a machine to have limited protection against
unauthorised access, if the extension ROM contains a module which requires a
password to be entered before continuing.
In order to allow different sizes of EPROMs to be used without having to
have links on the board, the software will look for extension ROMs at higher
addresses first, and work backwards. This means that the high order address
lines (which should be tied to +5v on smaller sizes of EPROM) will be pulled
high initially, although they will be pulled low later on when looking for
further extension ROMs.
The way in which the kernel initialises modules has been changed. If there
is more than one version of the same module present in the ROM (which
includes the main ROM, expansion card ROMs and extension ROMs) then only the
newest version of the module is initialised. If an extension ROM contains a
newer version of a module in the main ROM, then the newer version will be
initialised at the point in the initialisation sequence where the main ROM
version would have been initialised. This allows main ROM modules to be
replaced without the problems associated with initialisation order.
; > PrivDoc.MMPM
Still to do on memory management, as of 26-May-93:
; Must be TMD
+ Make SoftCAMMap variable size
+ Finish routine to allocate backing L2 for an area
+ Write routine to allocate logical addresses for areas
+ Write routine to check for overlapping areas
+ Complete Create dynamic area routine
(done apart from final OS_ChangeDynamicArea to get required size)
+ Write Remove dynamic area routine
(done apart from initial OS_ChangeDynamicArea to shrink to zero size)
+ Write Return info on dynamic area routine
+ Write Enumerate dynamic areas routine
+ Write Renumber dynamic areas routine
+ Change OS_ReadDynamicArea to use new list
+ Change OS_ValidateAddress to use new list
+ Put in new error messages properly
* If CreateArea fails to grow area to required size, it should kill area and return error
* Change ChangeDynamicArea code to use lists:
+ Check enough is working for Wimp_ClaimFreeMemory to use OS_DynamicArea(create)
* Check PreShrink and PostShrink work completely OK
* Check PreGrow and PostGrow work (apart from passing in page blocks)
* Migrate existing areas to new world:
* Update InitDynamicAreas initially to fake up a node for the RMA, and check it works
* Use DynamicArea_Create to create RMA from scratch (if feasible)
* Update InitDynamicAreas to fake up a node for the system heap + check it (no way of using create routine)
* Change OS_ReadRAMFsLimits to use OS_ReadDynamicArea
* Write RAMFS area handlers
* Create RAMFS dynamic area using DynamicArea_Create, + check it works
* Do similar for font cache, sprite area
* Put in code to split grow block into chunks, and create page blocks (without checking for updates from PreGrow)
* Put in checks for PreGrow requesting particular pages, and call alternative code:
* Do the double shuffle
* Issue Service_PagesUnsafe/Safe
* Stop it getting the static pages (esp. cursor/sound page, L1 and maybe L2)
* Put in extra code to cope with doubly-mapped areas
* Write area handlers for screen, and move it to new world
* Change size of application space to 24M (check all refs to 16M in whole image)
* Put in indirections for hardware vector poking
* Change FPE to use indirections (KWelton)
* Move RMA to &02100000, and change size of app space to 28M
* Conversion to do late aborts
; Could be done by ANOther
* OS_Memory:
a) conversion bits
b) read phys.memory arrangement
c) read amounts of various sorts of memory
d) read controller addresses
\ No newline at end of file
; > PrivDoc.ScreenMode
Still to do on screen mode selection, as of 21-Jul-93:
Key: + Done and tested
- Done but not tested
* Still to do
x Not done for a good reason
+ Make OS_ReadModeVariable work with mode selectors
+ OS_ScreenMode(ReturnMode)
+ OS_ScreenMode(EnumerateModes)
+ Create variable holding video bandwidth
+ Add this reason code to just load up video bandwidth, VideoSize and issue service
+ Service_ModeExtension additions
+ Load up r4 and r5 with video bandwidth, VideoSize respectively
+ Change vdugrafg:SetUpSprModeData:04 to check for mode selector, and goto 10 if so
+ Check other occurrences of BranchIfKnownMode to look for similar bits
+ Put code to handle new sprite mode word into PushModeInfo (any monitor only?)
+ Remove new sprite mode word fudging in vdugrafg:SetupSprModeData and
vdugrafl:SwitchOutputToSprite
+ Make SwitchOutputToSprite(new format) set up ECFIndex (it doesn't at the moment!)
+ Make sure tests for equal mode numbers don't assume equal ptrs to mode selectors are equivalent
+ Modify NewModes module to respond to Service_EnumerateScreenModes, to test enumeration.
+ OS_ScreenMode(SetMonitorType)
+ Allocate soft copy for monitortype
+ Write routine to update soft copy from CMOS
+ Call this routine in initialisation
+ Make *Configure MonitorType update soft copy
+ Change ReadMonitorType to read from soft copy
+ Add this reason code to either store given value or update from CMOS
+ Make sprites which have mode selectors as their mode word illegal
+ Move conversion of mode selectors to new format sprite mode words
into PreCreateHeader, rather than PostCreateHeader, so that it
doesn't call SetupSprModeData with a (now illegal) mode selector
-> MT ScreenModes module
-> AG Make switch output to sprite for a new format sprite make mode selector for current mode?
-> AG *ScreenSave in mode 50 seems to produce a sprite with a palette.
-> NK Trying to set a WimpMode with XEigFactor=27 caused data abort.
Investigate and/or range-limit values.
-> AG Put in support for returning errors from PushModeInfo (for bad mode
selectors and new format sprite mode words):
+ Make mode change routine check for error from PushModeInfo and FindOKMode
+ Make FindSubstitute check errors from PushModeInfo
+ Make FindOKMode check errors from FindSubstitute
+ Make CheckModeValid check errors from FindOKMode
+ Make SetupSprModeData capable of returning errors:
+ Ditto SpriteV handler (already OK)
+ Ditto PreCreateHeader
+ Ditto CreateHeader
+ Ditto GetSprite
-> AG Make SwitchOutputToSprite/Mask check errors from PushModeInfo
- Design and code algorithm for working out FIFO reload position for VIDC20
(Still need explanation from ARM of why 7 quad-words doesn't always work)
* OS_ScreenMode(SelectMode)
+ Make normal mode selection routine into a subroutine
+ Write veneers to put round call to this in OS_ScreenMode(SelectMode)
* Change actual mode change code to cope with mode selectors
+ Prevent main routine looking at shadow bit in mode selector
+ Modify FindOKMode to cope with mode selector
+ Modify OS_CheckModeValid to cope with mode selector
+ Make all pushed mode variables into words (not bytes)
+ Modify PushModeInfo to cope with mode selector
+ Make YEigFactor default to 2 if yres < xres/2 (and change spec. to reflect that)
+ Make numbered modes work after loading mode file
+ Allocate space for OS copy of mode selector
x Make OS mode selector part of saved VDU context
(not needed since sprites can't have mode selectors as their mode)
x Sort out internal mode variables PalIndex, ECFIndex wrt
converting existing mode numbers into mode selectors (no need, still use old workspace-getting code)
x Make mode selector blocks for all existing numbered modes
(no need, constructed on fly since only needed during svc call)
* Check that copying mode selector has no adverse effects
* Sort out why issuing a mode change with invalid mode selector doesn't give error
* Modify FindOKMode to cope with 16 and 32 bpp modes somehow
* Prevent pointer position from going into the sync pulse (causes screen picture disruption)
* Adjust borders on all modes, to cope with VIDC20 problem
(Needs algorithm from ARM that works!)
* Mode change happily passes round any old rubbish to Service_ModeExtension - it should:-
* First check that value is word-aligned - if not it may be a new sprite mode word
* Do a Validate_Address on fixed bit of block?
* What should *ScreenLoad do with a new format sprite?
| Copyright 1996 Acorn Computers Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
| > NewModes.Make
WimpSlot -min 1024k -max 1024k
AASM <Obey$Dir>.PSSrc <Obey$Dir>.PSModule -module -quit
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; general purpose mode macros
ClockShift * 9
SyncShift * 11
; pixel rate specifiers
CRPix_24000 * 3 :OR: (0 :SHL: ClockShift)
CRPix_16000 * 2 :OR: (0 :SHL: ClockShift)
CRPix_12000 * 1 :OR: (0 :SHL: ClockShift)
CRPix_8000 * 0 :OR: (0 :SHL: ClockShift)
CRPix_25175 * 3 :OR: (1 :SHL: ClockShift)
CRPix_36000 * 3 :OR: (2 :SHL: ClockShift)
MACRO
VIDC_List $lbpp,$hsync,$hbpch,$hlbdr,$hdisp,$hrbdr,$hfpch, $vsync,$vbpch,$vlbdr,$vdisp,$vrbdr,$vfpch,$pixrate,$sp
LCLA sub
LCLA syncpol
[ $lbpp = 3
sub SETA 5
]
[ $lbpp = 2
sub SETA 7
]
[ $lbpp = 1
sub SETA 11
]
[ $lbpp = 0
sub SETA 19
]
[ "$sp"=""
syncpol SETA 0 :SHL: SyncShift ; normal sync polarity
|
ASSERT $sp<=3
syncpol SETA $sp :SHL: SyncShift
]
ASSERT ($hsync :AND: 1)=0
ASSERT ($hbpch :AND: 1)=1
ASSERT ($hlbdr :AND: 1)=0
ASSERT ($hdisp :AND: 1)=0
ASSERT ($hrbdr :AND: 1)=0
ASSERT ($hfpch :AND: 1)=1
[ (($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch) :AND: 3)<>0
! 0, "Warning: mode unsuitable for interlaced use"
]
; Horizontal
& (&80:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch -2 )/2) :SHL: 14) ; HCR
& (&84:SHL:24) :OR: ((($hsync -2 )/2) :SHL: 14) ; HSWR
& (&88:SHL:24) :OR: ((($hsync+$hbpch -1 )/2) :SHL: 14) ; HBSR
& (&8C:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr -sub)/2) :SHL: 14) ; HDSR
& (&90:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr+$hdisp -sub)/2) :SHL: 14) ; HDER
& (&94:SHL:24) :OR: ((($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr -1 )/2) :SHL: 14) ; HBER
& (&9C:SHL:24) :OR: (((($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch-2)/2+1)/2):SHL:14); HIR
; Vertical
& (&A0:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr+$vfpch -1) :SHL: 14) ; VCR
& (&A4:SHL:24) :OR: (($vsync -1) :SHL: 14) ; VSWR
& (&A8:SHL:24) :OR: (($vsync+$vbpch -1) :SHL: 14) ; VBSR
& (&AC:SHL:24) :OR: (($vsync+$vbpch+$vlbdr -1) :SHL: 14) ; VDSR
& (&B0:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp -1) :SHL: 14) ; VDER
& (&B4:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr -1) :SHL: 14) ; VBER
; Control Register
& (&E0:SHL:24) :OR: (CRPix_$pixrate) :OR: ($lbpp :SHL: 2) :OR: syncpol
& -1
MEND
MACRO
VIDC_WS $bpp,$hpix,$vpix,$multx,$multy, $dht
& VduExt_XWindLimit, $hpix-1
& VduExt_ScrRCol, ($hpix/8)-1
& VduExt_LineLength, $hpix*$bpp/8
[ "$dht" <> ""
& VduExt_ModeFlags, Flag_DoubleVertical
& VduExt_ScrBRow, ($vpix/16)-1
|
& VduExt_ScrBRow, ($vpix/8)-1
]
& VduExt_YWindLimit, $vpix-1
& VduExt_ScreenSize, $hpix*$vpix*$bpp/8
& VduExt_XEigFactor, $multx
& VduExt_YEigFactor, $multy
MEND
VLN_0 VIDC_List 0, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 0
VLN_1 VIDC_List 1, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 1
VLN_2 VIDC_List 2, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 2
VLN_3 VIDC_List 1, 72,145, 48, 640, 48, 71, 3,18,22,250,19, 0,16000,0 ; MODE 3
VLN_4 VIDC_List 0, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 4
VLN_5 VIDC_List 1, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 5
VLN_6 VIDC_List 1, 36, 73, 24, 320, 24, 35, 3,18,22,250,19, 0, 8000,0 ; MODE 6
VLN_7 VIDC_List 2, 36, 73, 24, 320, 24, 35, 3,18,22,250,19, 0, 8000,0 ; MODE 7
VLN_8 VIDC_List 1, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 8
VLN_9 VIDC_List 2, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 9
VLN_10 VIDC_List 3, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 10
VLN_11 VIDC_List 1, 72,145, 48, 640, 48, 71, 3,18,22,250,19, 0,16000,0 ; MODE 11
VLN_12 VIDC_List 2, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 12
VLN_13 VIDC_List 3, 36, 73, 24, 320, 24, 35, 3,18,18,256,17, 0, 8000,0 ; MODE 13
VLN_14 VIDC_List 2, 72,145, 48, 640, 48, 71, 3,18,22,250,19, 0,16000,0 ; MODE 14
VLN_15 VIDC_List 3, 72,145, 48, 640, 48, 71, 3,18,18,256,17, 0,16000,0 ; MODE 15
VLN_16 VIDC_List 2, 72,215, 46,1056, 46,101, 3,18,18,256,17, 0,24000,0 ; MODE 16
VLN_17 VIDC_List 2, 72,215, 46,1056, 46,101, 3,18,22,250,19, 0,24000,0 ; MODE 17
;VLN_18 VIDC_List 0, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 18
;VLN_19 VIDC_List 1, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 19
;VLN_20 VIDC_List 2, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 20
;VLN_21 VIDC_List 3, 56,183, 2, 640, 2, 13, 3,17, 1,512, 1, 0,24000,0 ; MODE 21
VLN_24 VIDC_List 3, 72,215, 46,1056, 46,101, 3,18,18,256,17, 0,24000,0 ; MODE 24
VLN_33 VIDC_List 3, 74,127, 0, 768, 0, 55, 3,18, 0,288, 0, 3,16000,0 ; MODE 33
VLN_34 VIDC_List 3, 74, 87, 0, 832, 0, 31, 3,18, 0,288, 0, 3,16000,0 ; MODE 34
VLM_0 VIDC_List 0, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 0
VLM_1 VIDC_List 1, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 1
VLM_2 VIDC_List 2, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 2
VLM_3 VIDC_List 1, 72, 63, 88, 640, 88, 73, 3,16,20,250,20, 3,16000,0 ; MODE 3
VLM_4 VIDC_List 0, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 4
VLM_5 VIDC_List 1, 36, 51, 24, 320, 24, 57, 3,16,17,256,17, 3, 8000,0 ; MODE 5
VLM_6 VIDC_List 1, 36, 33, 44, 320, 44, 35, 3,16,20,250,20, 3, 8000,0 ; MODE 6
VLM_7 VIDC_List 2, 36, 31, 44, 320, 44, 37, 3,18,22,250,16, 3, 8000,0 ; MODE 7
VLM_8 VIDC_List 1, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 8
VLM_9 VIDC_List 2, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 9
VLM_10 VIDC_List 3, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 10
VLM_11 VIDC_List 1, 72, 63, 88, 640, 88, 73, 3,16,20,250,20, 3,16000,0 ; MODE 11
VLM_12 VIDC_List 2, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 12
VLM_13 VIDC_List 3, 36, 33, 44, 320, 44, 35, 3,16,17,256,17, 3, 8000,0 ; MODE 13
VLM_14 VIDC_List 2, 72, 63, 88, 640, 88, 73, 3,16,20,250,20, 3,16000,0 ; MODE 14
VLM_15 VIDC_List 3, 72, 63, 88, 640, 88, 73, 3,16,17,256,17, 3,16000,0 ; MODE 15
VLM_16 VIDC_List 2,112, 47,132,1056,132, 57, 3,16,17,256,17, 3,24000,0 ; MODE 16
VLM_17 VIDC_List 2,112, 47,132,1056,132, 57, 3,16,20,250,20, 3,24000,0 ; MODE 17
VLM_18 VIDC_List 0, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 18
VLM_19 VIDC_List 1, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 19
VLM_20 VIDC_List 2, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 20
VLM_21 VIDC_List 3, 56,111, 2, 640, 2, 85, 3,17, 1,512, 1, 0,24000,0 ; MODE 21
VLM_24 VIDC_List 3,112, 47,132,1056,132, 57, 3,16,17,256,17, 3,24000,0 ; MODE 24
VLM_25 VIDC_List 0, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 25
VLM_26 VIDC_List 1, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 26
VLM_27 VIDC_List 2, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 27
VLM_28 VIDC_List 3, 96, 47, 0, 640, 0, 15, 2,32, 0,480, 0,11,25175,3 ; MODE 28
VLM_31 VIDC_List 2, 72,129, 0, 800, 0, 23, 2,22, 0,600, 0, 1,36000,0 ; MODE 31
VLH_23 VIDC_List 2, 52, 47, 2, 288, 2, 1, 3,43, 4,896, 4, 0,24000,0 ; MODE 23
[ {FALSE} ; This mode not supported by VIDC, so not used
V32tab1
VIDC_List 0,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
]
V32tab2 ; MODES 1,5
VIDC_List 1,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
V32tab2T ; MODE 6
VIDC_List 1,36,73,24,320,24,35, 3,18,22,250,19,0,8000,0
V32tab4 ; MODES 2,9
VIDC_List 2,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
V32tab4T ; MODE 7
VIDC_List 2,36,73,24,320,24,35, 3,18,22,250,19,0,8000,0
V32tab8 ; MODES 10,13
VIDC_List 3,36,73,24,320,24,35, 3,18,18,256,17,0,8000,0
V64tab1 ; MODES 0,4
VIDC_List 0,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V64tab2 ; MODE 8
VIDC_List 1,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V64tab2T ; MODES 3,11
VIDC_List 1,72,145,48,640,48,71, 3,18,22,250,19,0,16000,0
V64tab4 ; MODE 12
VIDC_List 2,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V64tab4T ; MODE 14
VIDC_List 2,72,145,48,640,48,71, 3,18,22,250,19,0,16000,0
V64tab8 ; MODE 15
VIDC_List 3,72,145,48,640,48,71, 3,18,18,256,17,0,16000,0
V132tab4 ; MODE 16
VIDC_List 2,72,215,46,1056,46,101, 3,18,18,256,17,0,24000,0
V132tab4T ; MODE 17
VIDC_List 2,72,215,46,1056,46,101, 3,18,22,250,19,0,24000,0
[ {TRUE}
V64tab1D ; MODE 18
VIDC_List 0,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
V64tab2D ; MODE 19
VIDC_List 1,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
V64tab4D ; MODE 20
VIDC_List 2,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
V64tab8D ; MODE 21 (NEW)
VIDC_List 3,56,183,2,640,2,13, 3,17,1,512,1,0,24000,0
[ {FALSE} ; not used any more
V128tab1 ; MODE 22
VIDC_List 2,54,39,2,320,2,7, 2,44,1,976,1,0,24000,0
]
V115tab1 ; MODE 23 new Unoid monitor style, 1152x896
; changed again 29-Jul-88 to give 64.4Hz
VIDC_List 2,52,47,2,288,2,1, 3,43,4,896,4,0,24000,0
|
V64tab1D ; MODE 18 (old)
VIDC_List 0,56,199,2,640,2,1, 3,17,1,512,1,0,24000,0
V64tab2D ; MODE 19 (old)
VIDC_List 1,56,199,2,640,2,1, 3,17,1,512,1,0,24000,0
V64tab4D ; MODE 20 (old)
VIDC_List 2,56,199,2,640,2,1, 3,17,1,512,1,0,24000,0
V128tab1 ; MODE 22 (old)
VIDC_List 2,60,41,0,320,0,3, 2,44,1,976,1,0,24000,0
V115tab1 ; MODE 23
VIDC_List 2,60,41,16,288,16,3, 2,44,57,864,57,0,24000,0
]
V132tab8 ; MODE 24 (NEW)
VIDC_List 3,72,215,46,1056,46,101, 3,18,18,256,17,0,24000,0
[ {FALSE} ; This mode not supported by VIDC, so not used
V32tab1
& &803FC000
& &84044000
& &880D8000
& &8C0E4000
& &90364000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000030
& -1
]
V32tab2 ; MODES 1,5
& &803FC000
& &84044000
& &880D8000
& &8C0F4000
& &90374000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000034
& -1
V32tab2T ; MODE 6
& &803FC000
& &84044000
& &880D8000
& &8C0F4000
& &90374000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC0A8000 ; start 4 pixels down
& &B0490000 ; end 2 pixels up
& &B44DC000
& &E0000034
& -1
V32tab4 ; MODES 2,9
& &803FC000
& &84044000
& &880D8000
& &8C0FC000
& &9037C000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000038
& -1
V32tab4T ; MODE 7
& &803FC000
& &84044000
& &880D8000
& &8C0FC000
& &9037C000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC0A8000 ; start 4 pixels down
& &B0490000 ; end 2 pixels up
& &B44DC000
& &E0000038
& -1
V32tab8 ; MODES 10,13
& &803FC000
& &84044000
& &880D8000
& &8C100000
& &90380000
& &943B8000
& &9C200000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E000002C
& -1
V64tab1 ; MODES 0,4
& &807FC000
& &8408C000
& &881B0000
& &8C1EC000
& &906EC000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000032
& -1
V64tab2 ; MODE 8
& &807FC000
& &8408C000
& &881B0000
& &8C1FC000
& &906FC000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E0000036
& -1
V64tab2T ; MODES 3,11
& &807FC000
& &8408C000
& &881B0000
& &8C1FC000
& &906FC000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC0A8000 ; Start 4 pixels down
& &B0490000 ; End 2 pixels up
& &B44DC000
& &E0000036
& -1
V64tab4 ; MODE 12
& &807FC000
& &8408C000
& &881B0000
& &8C204000
& &90704000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E000002A
& -1
V64tab4T ; MODE 14
& &807FC000
& &8408C000
& &881B0000
& &8C204000
& &90704000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC0A8000 ; Start 4 pixels down
& &B0490000 ; End 2 pixels up
& &B44DC000
& &E000002A
& -1
V64tab8 ; MODE 15
& &807FC000
& &8408C000
& &881B0000
& &8C208000
& &90708000
& &94770000
& &9C400000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E000001E
& -1
V132tab4 ; MODE 16
& &80BFC000
& &8408C000
& &8823C000 ; 1B0000
& &8C28C000
& &90ACC000
& &94B34000 ; B20000
& &9C600000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E000002B
& -1
V132tab4T ; MODE 17
& &80BFC000
& &8408C000
& &8823C000 ; 1B0000
& &8C28C000
& &90ACC000
& &94B34000 ; B34000
& &9C600000
& &A04DC000
& &A4008000
& &A8050000
& &AC0A8000 ; start 4 pixels down
& &B0490000 ; end 2 pixels up
& &B44DC000
& &E000002B
& -1
[ {TRUE}
V64tab1D ; MODE 18
& &806FC000
& &8406C000
& &881DC000
& &8C1BC000
& &906BC000
& &946E4000
& &9C380000
& &A0854000
& &A4008000
& &A804C000
& &AC050000
& &B0850000
& &B4854000
& &E0000033
& -1
V64tab2D ; MODE 19
& &806FC000
& &8406C000
& &881DC000
& &8C1CC000
& &906CC000
& &946E4000
& &9C380000
& &A0854000
& &A4008000
& &A804C000
& &AC050000
& &B0850000
& &B4854000
& &E0000037
& -1
V64tab4D ; MODE 20
& &806FC000
& &8406C000
& &881DC000
& &8C1D4000
& &906D4000
& &946E4000
& &9C380000
& &A0854000
& &A4008000
& &A804C000
& &AC050000
& &B0850000
& &B4854000
& &E000002B
& -1
V64tab8D ; MODE 21 (NEW)
& &806FC000
& &8406C000
& &881DC000
& &8C1D8000
& &906D8000
& &946E4000
& &9C380000
& &A0854000
& &A4008000
& &A804C000
& &AC050000
& &B0850000
& &B4854000
& &E000000F
& -1
[ {FALSE} ; not used any more
V128tab1 ; MODE 22
& &8034C000
& &84068000
& &880B8000
& &8C0B0000
& &90330000
& &94340000
& &9C1A8000
& &A0FFC000
& &A4004000
& &A80B4000
& &AC0B8000
& &B0FF8000
& &B4FFC000
& &E000002B
& -1
]
V115tab1 ; MODE 23 new Unoid monitor style, 1152x896
; changed again 29-Jul-88 to give 64.4Hz
& &8030C000
& &84064000
& &880C4000
& &8C0BC000
& &902FC000
& &9430C000
& &9C188000 ; changed 16-Aug-88, was 1A8
& &A0ED4000
& &A4008000
& &A80B4000
& &AC0C4000
& &B0EC4000
& &B4ED4000
& &E000002B
& -1
|
V64tab1D ; MODE 18 (old)
& &80704000
& &8406C000
& &881FC000
& &8C1DC000
& &906DC000
& &94704000
& &9C384000
& &A0854000
& &A4008000
& &A804C000
& &AC050000
& &B0850000
& &B4854000
& &E0000033
& -1
V64tab2D ; MODE 19 (old)
& &80704000
& &8406C000
& &881FC000
& &8C1EC000
& &906EC000
& &94704000
& &9C384000
& &A0854000
& &A4008000
& &A804C000
& &AC050000
& &B0850000
& &B4854000
& &E0000037
& -1
V64tab4D ; MODE 20 (old)
& &80704000
& &8406C000
& &881FC000
& &8C1F4000
& &906F4000
& &94704000
& &9C384000
& &A0854000
& &A4008000
& &A804C000
& &AC050000
& &B0850000
& &B4854000
& &E000002B
& -1
V128tab1 ; MODE 22 (old)
& &8034C000
& &84074000
& &880C8000
& &8C0BC000
& &9033C000
& &94348000
& &9C1A8000 ; was wrong
& &A0FFC000
& &A4004000
& &A80B4000
& &AC0B8000
& &B0FF8000
& &B4FFC000
& &E000002B
& -1
V115tab1 ; MODE 23
& &8034C000
& &84074000
& &880C8000
& &8C0DC000
& &9031C000
& &94348000
& &9C1A8000 ; was wrong
& &A0FFC000
& &A4004000
& &A80B4000
& &AC198000
& &B0F18000
& &B4FFC000
& &E000002B
& -1
]
V132tab8 ; MODE 24 (NEW)
& &80BFC000
& &8408C000
& &8823C000
& &8C290000
& &90AD0000
& &94B34000
& &9C600000
& &A04DC000
& &A4008000
& &A8050000
& &AC098000
& &B0498000
& &B44DC000
& &E000000F
& -1
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;
; A600tlb
;
; POST procedure for checking the TLB in A600 MMU.
;
; for each of level 1, level 2 small-page, level 2 large-page
; construct page table
; flush cache
; start timer
; for 32 addresses (with different mappings)
; check address mapping
; save timer
; for same 32 addresses
; check address mapping
; compare test times (did 2nd test require table walk ?)
Use a list of addresses that cover a good mixture of virtual addresses
Build a page table that maps these to physical RAM addresses in various ways
Access the addresses in such an order that the cache rotates, scrapping
one entry each time through the list, and loading another. So each cache
entry gets used 31 times, then is lost.
Choice of physical mapping should ensure that the cache entries contain
lots of different values of page and section base addresses.
Choice of virtual test address should ensure that cache tag varies as
widely as posible, too. PRBS ?
Very widely varying values of cache tag require that a large number
of mappings exist .. if these are 2-level mappings, that requires
a lot of RAM. Page tables should be multiply-mapped.
RISC OS puts lots of stuff below the 4M mark. Limits App space to 16M
for backwards compatibility. Probably worth testing outside these
limits to ensure Gold doesn't fall over, but failure rates would be
very low.
;
; POST procedure for checking access faults (was PPL test)
;
; for each of level 1, level 2 small-page, level 2 large-page
; construct page table
; for user, supervisor mode
; check address alignment fault
; check section translation fault
; check
; check page translation fault
; for 3 domain types
; for 16 domains
; check access permissions
;
;
; POST procedure for checking IDC
;
;
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