Commit 1b818335 authored by Ben Avison's avatar Ben Avison
Browse files

Changed default PaletteV handler so that read palette reason code returns all...

Changed default PaletteV handler so that read palette reason code returns all four supremacy bits in the palette entries (previously it cleared all except bit 7). This brings it into line with the bulk read reason code.

Version 5.11. Tagged as 'Kernel-5_11'
parent 247389ac
......@@ -6,9 +6,9 @@
GBLS Module_MinorVersion
GBLS Module_Date
GBLS Module_FullVersion
Module_MajorVersion SETS "5.10"
Module_Version SETA 510
Module_MajorVersion SETS "5.11"
Module_Version SETA 511
Module_MinorVersion SETS ""
Module_Date SETS "26 Jan 2000"
Module_FullVersion SETS "5.10"
Module_FullVersion SETS "5.11"
END
/* (5.10)
/* (5.11)
*
* This file is automatically maintained by srccommit, do not edit manually.
*
*/
#define Module_MajorVersion_CMHG 5.10
#define Module_MajorVersion_CMHG 5.11
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 26 Jan 2000
#define Module_MajorVersion "5.10"
#define Module_Version 510
#define Module_MajorVersion "5.11"
#define Module_Version 511
#define Module_MinorVersion ""
#define Module_Date "26 Jan 2000"
#define Module_FullVersion "5.10"
#define Module_FullVersion "5.11"
......@@ -824,8 +824,8 @@ PV_BulkRead ROUT
; 24 (read border colour)
; 25 (read cursor colour)
;
; out: R2 = first flash setting (BBGGRRS0), supremacy bit 7
; R3 = second flash setting (BBGGRRS0), supremacy bit 7
; out: R2 = first flash setting (BBGGRRS0), supremacy bits 4-7
; R3 = second flash setting (BBGGRRS0), supremacy bits 4-7
;
PV_ReadPalette ROUT
......@@ -850,17 +850,19 @@ PV_ReadPalette ROUT
; note no need to fudge 256-colour modes, since we have the correct full 256 entry palette
; bjga: changed to handle 4 bits of supremacy (BulkRead already does)
LDR r10, [WsPtr, #FirPalAddr]
LDR r10, [r10, r11, LSL #2] ; r10 := 1st XSBBGGRR
MOV r2, r10, LSL #8 ; r2 := 1st BBGGRR00
TST r10, #1 :SHL: 27
ORRNE r2, r2, #&80 ; r2 := 1st BBGGRRS0
AND r10, r10, #&0F000000 ; r10 := 1st 0S000000
ORR r2, r2, r10, LSR #20 ; r2 := 1st BBGGRRS0
LDR r10, [WsPtr, #SecPalAddr]
LDR r10, [r10, r11, LSL #2] ; r10 := 2nd XSBBGGRR
MOV r3, r10, LSL #8 ; r3 := 2nd BBGGRR00
TST r10, #1 :SHL: 27
ORRNE r3, r3, #&80 ; r3 := 2nd BBGGRRS0
AND r10, r10, #&0F000000 ; r10 := 2nd 0S000000
ORR r3, r3, r10, LSR #20 ; r3 := 2nd BBGGRRS0
99
MOV r4, #0
Pull "r10, r11, pc"
......
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