Commit f5644f74 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Enable high processor vectors/zero page relocation. OS_DynamicArea 20 fixes.

Detail:
  Makefile, hdr/Options - By default enable high processor vectors/zero page relocation for compatible machines, but also allow the components file to override the setting if required
  s/ChangeDyn - Fix OS_DynamicArea 20 to check the correct range for doubly mapped areas, and to correctly localise its error message
Admin:
  Tested on Iyonix


Version 5.35, 4.79.2.268. Tagged as 'Kernel-5_35-4_79_2_268'
parent c8f15bd6
...@@ -28,7 +28,7 @@ TOKHELPSRC = ${TOKENSOURCE} ...@@ -28,7 +28,7 @@ TOKHELPSRC = ${TOKENSOURCE}
HELPSRC = HelpStrs HELPSRC = HelpStrs
ROM_SOURCE = GetAll.s ROM_SOURCE = GetAll.s
KERNEL_MODULE = bin${SEP}${COMPONENT} KERNEL_MODULE = bin${SEP}${COMPONENT}
ASFLAGS = -PD "FreezeDevRel SETL {${FREEZE_DEV_REL}}" ASFLAGS += -PD "FreezeDevRel SETL {${FREEZE_DEV_REL}}"
CUSTOMROM = custom CUSTOMROM = custom
CUSTOMEXP = custom CUSTOMEXP = custom
EXPORTS = ${EXP_HDR}.EnvNumbers \ EXPORTS = ${EXP_HDR}.EnvNumbers \
......
...@@ -13,11 +13,11 @@ ...@@ -13,11 +13,11 @@
GBLS Module_ComponentPath GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35" Module_MajorVersion SETS "5.35"
Module_Version SETA 535 Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.267" Module_MinorVersion SETS "4.79.2.268"
Module_Date SETS "04 Jul 2015" Module_Date SETS "04 Jul 2015"
Module_ApplicationDate SETS "04-Jul-15" Module_ApplicationDate SETS "04-Jul-15"
Module_ComponentName SETS "Kernel" Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel" Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.267)" Module_FullVersion SETS "5.35 (4.79.2.268)"
Module_HelpVersion SETS "5.35 (04 Jul 2015) 4.79.2.267" Module_HelpVersion SETS "5.35 (04 Jul 2015) 4.79.2.268"
END END
...@@ -5,12 +5,12 @@ ...@@ -5,12 +5,12 @@
* *
*/ */
#define Module_MajorVersion_CMHG 5.35 #define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.267 #define Module_MinorVersion_CMHG 4.79.2.268
#define Module_Date_CMHG 04 Jul 2015 #define Module_Date_CMHG 04 Jul 2015
#define Module_MajorVersion "5.35" #define Module_MajorVersion "5.35"
#define Module_Version 535 #define Module_Version 535
#define Module_MinorVersion "4.79.2.267" #define Module_MinorVersion "4.79.2.268"
#define Module_Date "04 Jul 2015" #define Module_Date "04 Jul 2015"
#define Module_ApplicationDate "04-Jul-15" #define Module_ApplicationDate "04-Jul-15"
...@@ -18,6 +18,6 @@ ...@@ -18,6 +18,6 @@
#define Module_ComponentName "Kernel" #define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel" #define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.267)" #define Module_FullVersion "5.35 (4.79.2.268)"
#define Module_HelpVersion "5.35 (04 Jul 2015) 4.79.2.267" #define Module_HelpVersion "5.35 (04 Jul 2015) 4.79.2.268"
#define Module_LibraryVersionInfo "5:35" #define Module_LibraryVersionInfo "5:35"
...@@ -297,10 +297,10 @@ FixCallBacks SETL {TRUE} ; also addresses some atomicity ...@@ -297,10 +297,10 @@ FixCallBacks SETL {TRUE} ; also addresses some atomicity
GBLL InterlacedPointer GBLL InterlacedPointer
InterlacedPointer SETL {TRUE} :LAND: STB ; enable code to do proper interlaced pointer InterlacedPointer SETL {TRUE} :LAND: STB ; enable code to do proper interlaced pointer
[ :LNOT: :DEF: HiProcVecs
GBLL HiProcVecs ; Relocate processor vectors and first 16K of workspace to &FFFF0000 GBLL HiProcVecs ; Relocate processor vectors and first 16K of workspace to &FFFF0000
HiProcVecs SETL {FALSE} ; Leave off for now HiProcVecs SETL "$Machine"="Tungsten" :LOR: :LNOT: NoARMv6
; In an ideal world, we'd use something like this: ]
; HiProcVecs SETL "$Machine"="Tungsten" :LOR: :LNOT: NoARMv6
GBLL DebugForcedReset ; debug forced hard resets GBLL DebugForcedReset ; debug forced hard resets
DebugForcedReset SETL {FALSE} DebugForcedReset SETL {FALSE}
......
...@@ -2302,14 +2302,17 @@ DynArea_Locate Entry "r2-r5" ...@@ -2302,14 +2302,17 @@ DynArea_Locate Entry "r2-r5"
TEQ r10, #0 TEQ r10, #0
PullEnv EQ PullEnv EQ
ADREQL r0, ErrorBlock_BadAddress ADREQL r0, ErrorBlock_BadAddress
BEQ DynArea_ReturnError BEQ DynArea_TranslateAndReturnError
BL %FT60 ; check treacle DA node BL %FT60 ; check treacle DA node
B %BT50 B %BT50
60 60
LDR r1, [r10, #DANode_Flags]
LDR r0, [r10, #DANode_Size]
TST r1, #DynAreaFlags_DoublyMapped
LDR r1, [r10, #DANode_Base] LDR r1, [r10, #DANode_Base]
LDR r2, [r10, #DANode_Size] ADD r2, r1, r0 ; r1:=base r2:=top
ADD r2, r1, r2 ; r1:=base r2:=top SUBNE r1, r1, r0 ; doubly mapped is special
CMP r5, r1 CMP r5, r1
CMPCS r2, r5 CMPCS r2, r5
LDRHI r1, [r10, #DANode_Number] ; number LDRHI r1, [r10, #DANode_Number] ; number
......
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