Huge update to L7200 HAL for Customer M 2 demo - now runs with 5.02 Kernel used in Tungsten.

Added "fast" flash tool for Customer L, allowing ROMs to be sent serially at
115200 baud not 9600 baud.
Fix to VDU despatch for ARMv4 and later.
Fixes to power on delete keyboard and keyboard timeout
Implemented MemoryReadPhys and MemoryAmounts with the HAL.

Version 5.35, 4.79.2.59. Tagged as 'Kernel-5_35-4_79_2_59'

Version

@@ -16,7 +16,7 @@ Date    SETS    Module_Date      ; version for STB/NC OS
         |
 Version SETA    502
 VString SETS    "5.02"
-Date    SETS    "28 Feb 2003"    ; version for RISC OS on desktop computers
+Date    SETS    "25 Mar 2003"    ; version for RISC OS on desktop computers
         ]
 
         END

VersionASM

@@ -13,11 +13,11 @@
                         GBLS    Module_ComponentPath
 Module_MajorVersion     SETS    "5.35"
 Module_Version          SETA    535
-Module_MinorVersion     SETS    "4.79.2.58"
-Module_Date             SETS    "02 Mar 2003"
-Module_ApplicationDate  SETS    "02-Mar-03"
+Module_MinorVersion     SETS    "4.79.2.59"
+Module_Date             SETS    "31 Mar 2003"
+Module_ApplicationDate  SETS    "31-Mar-03"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.35 (4.79.2.58)"
-Module_HelpVersion      SETS    "5.35 (02 Mar 2003) 4.79.2.58"
+Module_FullVersion      SETS    "5.35 (4.79.2.59)"
+Module_HelpVersion      SETS    "5.35 (31 Mar 2003) 4.79.2.59"
                         END

VersionNum

@@ -5,19 +5,19 @@
  *
  */
 #define Module_MajorVersion_CMHG        5.35
-#define Module_MinorVersion_CMHG        4.79.2.58
-#define Module_Date_CMHG                02 Mar 2003
+#define Module_MinorVersion_CMHG        4.79.2.59
+#define Module_Date_CMHG                31 Mar 2003
 
 #define Module_MajorVersion             "5.35"
 #define Module_Version                  535
-#define Module_MinorVersion             "4.79.2.58"
-#define Module_Date                     "02 Mar 2003"
+#define Module_MinorVersion             "4.79.2.59"
+#define Module_Date                     "31 Mar 2003"
 
-#define Module_ApplicationDate          "02-Mar-03"
+#define Module_ApplicationDate          "31-Mar-03"
 
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.35 (4.79.2.58)"
-#define Module_HelpVersion              "5.35 (02 Mar 2003) 4.79.2.58"
+#define Module_FullVersion              "5.35 (4.79.2.59)"
+#define Module_HelpVersion              "5.35 (31 Mar 2003) 4.79.2.59"
 #define Module_LibraryVersionInfo       "5:35"

hdr/HALEntries

@@ -149,6 +149,8 @@ EntryNo_HAL_KbdScan             #       1
 EntryNo_HAL_KbdScanFinish       #       1
 EntryNo_HAL_KbdScanInterrupt    #       1
 
+EntryNo_HAL_PhysInfo            #       1
+
 ; Various flags and constants
 
 ; NVMemory

hdr/KernelWS

@@ -1326,7 +1326,7 @@ MaxCamEntry     #       4       ; maximum index into the cam map, ie
 
 RAMLIMIT        #       4
 
-                #       4       ; spare
+ROMPhysAddr     #       4
 
 HiServ_ws       #       4
 HiServ          #       4

s/HAL

@@ -536,6 +536,7 @@ RISCOS_Start
         MOV     a3, #(AP_ROM * L2X_APMult) + L2_C + L2_B
         SUB     a4, v7, v6
         BL      Init_MapIn
+        MOV     a3, v6
         B       %FT75
 
 70
@@ -560,12 +561,14 @@ RISCOS_Start
         SUB     a4, v7, v5
         MOV     a3, #(AP_ROM * L2X_APMult) + L2_C + L2_B
         BL      Init_MapIn
+        MOV     a3, v5
 75
         ; We've now allocated all the pages we're going to before the MMU comes on.
         ; Note the end address (for RAM clear)
         ADD     a1, v3, #DRAMOffset_PageZero - DRAMOffset_L1PT
         STR     v1, [a1, #InitUsedBlock]
         STR     v2, [a1, #InitUsedEnd]
+        STR     a3, [a1, #ROMPhysAddr]
 
         ; Note the HAL flags passed in.
         LDR     a2, [sp, #0]
@@ -795,6 +798,7 @@ MMUon_nol1ptoverlap
 
 ; Remember some stuff that's about to get zapped
         LDR     v8, =ZeroPage
+        LDR     v4, [v8, #ROMPhysAddr]
         LDR     v5, [v8, #RAMLIMIT]
         LDR     v7, [v8, #MaxCamEntry]
 
@@ -805,6 +809,7 @@ MMUon_nol1ptoverlap
         BLEQ    ClearPhysRAM
 
 ; Put it back
+        STR     v4, [v8, #ROMPhysAddr]
         STR     v5, [v8, #RAMLIMIT]
         STR     v7, [v8, #MaxCamEntry]
 
@@ -921,7 +926,7 @@ MMUon_nol1ptoverlap
         LDR     sp, =ABTSTK
         MSR     CPSR_c, #F32_bit+I32_bit+UND32_mode
         LDR     sp, =UNDSTK
-        MSR     CPSR_c, #F32_bit+I32_bit+SVC2632
+        MSR     CPSR_c, #F32_bit+SVC2632
         LDR     sp, =SVCSTK
 
         LDR     ip, =CAM

s/MemInfo

@@ -446,9 +446,19 @@ NotAvailable    *       &88888888
 ;       Returns information about the memory arrangement table.
 ;
 MemoryPhysSize
+ [ HAL
+        Entry   "r0,r3,sb,ip"
+        AddressHAL
+        MOV     r0, #0
+        CallHAL HAL_PhysInfo
+        MOV     r1, r0
+        MOV     r2, #4*1024
+        EXIT
+ |
         MOV     r1, #PhysSpaceSize :SHR: ByteShift
         MOV     r2, #4*1024
         MOV     pc, lr
+ ]
 
 
 ;----------------------------------------------------------------------------------------
@@ -462,11 +472,92 @@ MemoryPhysSize
 ;       Returns the physical memory arrangement table in the given block.
 ;
 MemoryReadPhys  ROUT
-        Entry   "r1-r10"
 
  [ HAL
-        ! 0, "Sort out MemoryReadPhys"
+        Entry   "r0-r12"
+        AddressHAL
+        MOV     r0, r1
+        SUB     sp, sp, #4
+        MOV     r1, sp
+        CallHAL HAL_PhysInfo            ; fills in everything except DRAM
+        LDR     r11, [sp], #4
+
+        ; r0 to r11 is DRAM or not present.
+        LDR     r1, [sp, #4]            ; Get table address back
+        ADD     r1, r1, r0, LSR #ByteShift
+        MOV     r2, r0                  ; Current physical address.
+        MOV     r3, #0                  ; Next word to store in table.
+        MOV     r4, #32                 ; How much more we have to shift r3 before storing it.
+        MOV     r5, #0                  ; Current page number.
+        MOV     r6, #PhysRamTable
+        LDR     r7, [r3, #CamEntriesPointer]
+        ADD     r7, r7, #4              ; Point to PPL entries.
+        LDR     r8, [r3, #MaxCamEntry]
+10
+        LDMIA   r6!, {r9,r10}           ; Get physical address and size of next block.
+
+        CMP     r9, r0                  ; If not DRAM then
+        CMPHS   r11, r9
+        ADDLO   r5, r5, r10, LSR #12    ;   adjust current page number
+        BLO     %BT10                   ;   and try next block.
+
+        ADD     r10, r10, r9            ; Add amount of unused space between current and start of block.
+        SUB     r10, r10, r2            ; size = size + (physaddr - current)
+20
+        SUBS    r4, r4, #4              ; Reduce shift.
+        MOVCS   r3, r3, LSR #4          ; If more space in current word then shift it.
+        STRCC   r3, [r1], #4            ; Otherwise, store current word
+        MOVCC   r3, #0                  ;   and start a new one.
+        MOVCC   r4, #28
+
+        CMP     r2, r9                  ; If not reached start of block then page is not present.
+        ORRCC   r3, r3, #(NotPresent :OR: NotAvailable) :SHL: 28
+        BCC     %FT30
+        LDR     lr, [r7, r5, LSL #3]    ; Page is there so get PPL and determine if it's available or not.
+        TST     lr, #PageFlags_Unavailable
+        ORREQ   r3, r3, #DRAM_Pattern :SHL: 28
+        ORRNE   r3, r3, #(DRAM_Pattern :OR: NotAvailable) :SHL: 28
+        ADD     r5, r5, #1              ; Increment page count.
+30
+        ADD     r2, r2, #&1000          ; Increase current address.
+        SUBS    r10, r10, #&1000        ; Decrease size of block.
+        BGT     %BT20                   ; Stop if no more block left.
+
+        CMP     r8, r5                  ; Stop if we run out of pages.
+        BCS     %BT10
+
+        TEQ     r3, #0                          ; If not stored last word then
+        MOVNE   r3, r3, LSR r4                  ;   put bits in correct position
+        ADDNE   r2, r2, r4, LSL #BitShift       ;   adjust current address
+        RSBNE   r4, r4, #32                     ;   rest of word is not present
+        LDRNE   lr, =NotPresent :OR: NotAvailable
+        ORRNE   r3, r3, lr, LSL r4
+        STRNE   r3, [r1], #4                    ;   and store word.
+
+        ; End of last block of DRAM to r11 is not present.
+        MOV     r6, r0
+        ADD     lr, r11, #1
+        RSBS    r2, r2, lr
+        MOVNE   r0, r1
+        LDRNE   r1, =NotPresent :OR: NotAvailable
+        MOVNE   r2, r2, LSR #ByteShift
+        BLNE    memset
+
+        ; If softloaded (ie ROM image is wholely within DRAM area returned
+        ; by HAL_PhysInfo), mark that as unavailable DRAM.
+        MOV     r0, #0
+        LDR     r0, [r0, #ROMPhysAddr]
+        LDR     r1, [sp, #4]
+        CMP     r0, r6
+        ADDHS   lr, r0, #OSROM_ImageSize*1024
+        SUBHS   lr, lr, #1
+        CMPHS   r11, lr
+        ADDHS   r0, r1, r0, LSR #ByteShift
+        LDRHS   r1, =DRAM_Pattern :OR: NotAvailable
+        MOVHS   r2, #(OSROM_ImageSize*1024) :SHR: ByteShift
+        BLHS    memset
  |
+        Entry   "r1-r10"
         ; &00000000 to OSROM_ImageSize*1024 is ROM.
         MOV     r2, #(OSROM_ImageSize*1024-&00000000) :SHR: WordShift
         LDR     r3, =ROM_Pattern :OR: NotAvailable
@@ -602,8 +693,16 @@ MemoryAmounts   ROUT
         BEQ     %FT30                   ; Don't understand 0 (so the spec says).
 
         TEQ     lr, #5:SHL:8            ; Check for soft ROM
-        MOVEQ   r1, #OSROM_ImageSize*1024 ; this much soft ROM
-        BEQ     %FT20
+        BNE     %FT05
+        Push    "r0"
+        MOV     r0, #8
+        SWI     XOS_ReadSysInfo         ; are we softloaded?
+        MOVVS   r1, #0
+        Pull    "r0"
+        AND     r1, r1, r2
+        ANDS    r1, r1, #1:SHL:4
+        MOVNE   r1, #OSROM_ImageSize*1024 ; this much soft ROM
+        B       %FT20
 
 05      TEQ     lr, #1:SHL:8
         MOVEQ   r1, #0

s/Middle

@@ -1881,7 +1881,8 @@ osri6_maxvalue * (.-4-osri6_table) :SHR: 2
 ;     1     = PCI expansion card(s)
 ;     2     = additional processor(s)
 ;     3     = software power off
-;     4..31 reserved (currently undefined)
+;     4     = OS in RAM, else executing in ROM
+;     5..31 reserved (currently undefined)
 ;
 80
  [ HAL

s/NewReset

@@ -855,11 +855,14 @@ checkboot
 
  [ HAL
         ! 0, "Sort out SetBorder for CMOS reset"
+        TST     R7, #KbdFlag_Copy:OR:KbdFlag_Delete
  |
-     SetBorder  R0, R1, 15, 0, 0        ; flash the border as warning!
+        SetBorder  R0, R1, 15, 0, 0     ; flash the border as warning!
+        ASSERT  (Del_Down_Flag - R_Down_Flag) = 2
+        ASSERT  (Copy_Down_Flag - Del_Down_Flag) = 1
+        MOVS    R3, R7, LSR #16         ; full reset or just system?
  ]
 
-        MOVS    R3, R7, LSR #16         ; full reset or just system?
         MOVNE   R3, #-1                 ; Del or Copy does all RAM
         MOVEQ   R3, #UserCMOS           ; R or T just system
     [ ChecksumCMOS

s/vdu/vduplot

@@ -122,14 +122,14 @@ EntryFromSWIPlot
         TST     R6, #ClipBoxEnableBit
         BLNE    DoPlotClipBox
 
+	BIC	R11, R2, #2_111		; ARMv4 says we have to keep bits 1:0 of PC =0
  [ No26bitCode
         ADR     R14, CTidy              ; set up return address
  |
         ADR     R14, CTidy + SVC_mode   ; set up return address
  ]
                                         ; R0=X, R1=Y, R2=plot code
-        ADD     PC, PC, R2, LSR #1      ; jump to branch (bottom 2 bits of the
-                                        ; result are ignored!)
+        ADD     PC, PC, R11, LSR #1     ; jump to branch
         &       0                       ; dummy word
 
  B LineDrawSolid           ;   0 - Solid line

s/vdu/vduwrch

@@ -370,6 +370,7 @@ FastCLS ROUT
         MOV     R13, R11
         TEQ     R4, #GraphicsV_Complete
         Pull    PC, EQ
+        LDR     R0, [WsPtr, #TextBgColour]
 15
  ]
         LDR     R8, [WsPtr, #ScreenStart]