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Commit bdc4f843 authored by Mike Stephens's avatar Mike Stephens
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Reimplement Lazy task swapping, an amusing idea from Ursula, would have done... 

Reimplement Lazy task swapping, an amusing idea from Ursula, would have done it sooner but couldn't be bothered (humour).

Currently activates for all ARMs flagged as base-restored
abort model. No handling of eg. StrongARM pre-revT bug, but
then the kernel no longer runs on StrongARM (progress).
Still some details to fix: all aborts in current app space
assumed to be missing pages, but this must be fixed to
handle abort code in app space, things like debuggers
marking code read only.

Plus, small fixes:
  OS_Memory 8 returns vaguely useful info for RAM,VRAM
  in HAL build (temporary partial implementation)
  Broken handling of old BBC commands with (fx,tv etc)
  with no spaces fixed (fudgeulike code from Ursula,
  now 32-bit).

Version 5.35, 4.79.2.31. Tagged as 'Kernel-5_35-4_79_2_31'
parent 390c26e8
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Showing with 105 additions and 36 deletions
VersionASM
View file @ bdc4f843
......@@ -13,12 +13,12 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.30"
Module_Date SETS "17 May 2001"
Module_ApplicationDate2 SETS "17-May-01"
Module_ApplicationDate4 SETS "17-May-2001"
Module_MinorVersion SETS "4.79.2.31"
Module_Date SETS "22 May 2001"
Module_ApplicationDate2 SETS "22-May-01"
Module_ApplicationDate4 SETS "22-May-2001"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.30)"
Module_HelpVersion SETS "5.35 (17 May 2001) 4.79.2.30"
Module_FullVersion SETS "5.35 (4.79.2.31)"
Module_HelpVersion SETS "5.35 (22 May 2001) 4.79.2.31"
END
VersionNum
View file @ bdc4f843
......@@ -4,19 +4,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.30
#define Module_Date_CMHG 17 May 2001
#define Module_MinorVersion_CMHG 4.79.2.31
#define Module_Date_CMHG 22 May 2001
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.30"
#define Module_Date "17 May 2001"
#define Module_MinorVersion "4.79.2.31"
#define Module_Date "22 May 2001"
#define Module_ApplicationDate2 "17-May-01"
#define Module_ApplicationDate4 "17-May-2001"
#define Module_ApplicationDate2 "22-May-01"
#define Module_ApplicationDate4 "22-May-2001"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.30)"
#define Module_HelpVersion "5.35 (17 May 2001) (4.79.2.30)"
#define Module_FullVersion "5.35 (4.79.2.31)"
#define Module_HelpVersion "5.35 (22 May 2001) (4.79.2.31)"
hdr/Options
View file @ bdc4f843
......@@ -243,7 +243,7 @@ ARM6support SETL {TRUE}
GBLL ChocolateSysVars ;whether to do performance improvements in system variable handling
GBLL ChocolateOscli ;whether to do performance improvements in Oscli command stuff
GBLL ChocolateService ;whether to implement fast module service call distribution (uses table introduced
;into module format by Ursula API
;into module format by Ursula API)
;possibly enabled at run time for some ARMs only
;
......@@ -254,7 +254,7 @@ ChocolateOSMod SETL {TRUE}
ChocolateSysVars SETL {TRUE}
ChocolateOscli SETL {TRUE}
ChocolateService SETL {TRUE}
ChocolateAMB SETL {TRUE}
ChocolateAMB SETL {TRUE} :LAND: No26bitCode ; not implemented for 26bit kernel at present
[ ChocolateSysHeap
GBLA MaxChocolateCBBlocks ;max quick CallBack blocks available at any one time (else ordinary heap nodes used)
GBLA MaxChocolateSVBlocks ;max quick Software Vector blocks available at any one time (else ordinary heap nodes used)
......
s/AMBControl/main
View file @ bdc4f843
......@@ -90,12 +90,11 @@ AMBControl_Init
STR R1,[R1,#AMBNode_prev] ;anchor prev initially -> anchor (empty list)
STR R1,[R1,#AMBNode_next] ;anchor next initially -> anchor (empty list)
[ AMB_LazyMapIn
; currently always disable, need to sort out when abort fix up is supported
; and for which ARMs
;
! 0, "AMBControl currently always disables LazyMapIn (needs abort handler hooks)"
;
MOV R1,#AMBFlag_LazyMapIn_disable
MOV R0,#0
LDR R0,[R0,#ProcessorFlags]
TST R0,#CPUFlag_BaseRestored
MOVEQ R1,#AMBFlag_LazyMapIn_disable ;laziness not supported if we can't trivially restart after abort (because we're lazy!)
MOVNE R1,#0 ;yipee, laziness enabled (and not suspended)
STR R1,AMBFlags
]
MOV R0,#AMBControl_ws
......
s/AMBControl/memmap
View file @ bdc4f843
......@@ -56,11 +56,9 @@
;
; entry: r0 = aborting address (data address for data abort, instruction address
; for prefetch abort), r1-r7 trashable, no stack
; exit: r0 = non-zero if abort was expected and fixed up, zero if not
; exit: r0 = non-zero (NE status) if abort was expected and fixed up, zero (EQ status) if not
;
AMB_LazyFixUp ROUT
; not hooked in yet!
! 0, "AMB_LazyFixUp needs hooking into abort handlers"
MOV r7,r12
MOV r12,#AMBControl_ws
LDR r12,[r12]
......@@ -82,7 +80,6 @@ AMB_LazyFixUp ROUT
ADD r1,r1,#AMBNode_pages
ADD r1,r1,r0,LSL #2 ;r1 -> page involved, in node page list
LDR r2,AMBPhysBin
! 0, "AMB_LazyFixup a symbol for L2PT protection bits would be handy"
MOV r3,#&FF0
ORR r3,r3,#&E ;&FFE = L2PT protection bits for ordinary page
LDR r4,[r1]
......@@ -111,15 +108,15 @@ AMB_LazyFixUp ROUT
MOV r5,#0
LDR r5,[r5,#CamEntriesPointer]
ADD r5,r5,r6,LSL #3 ;r5 -> CAM entry affected
MOV r0,r0,LSL #Log2PageSize ;address is now ordinary again, and must be non-zero
MOVS r0,r0,LSL #Log2PageSize ;address is now ordinary again, and must be non-zero
MOV r1,#0 ;0 = AP for ordinary page
STMIA r5,{r0,r1} ;update CAM entry
MOV r12,r7
MOV pc,lr ;r0 is non-zero
MOV pc,lr ;r0 is non-zero, NE status
20
MOV r0,#0
MOVS r0,#0
MOV r12,r7
MOV pc,lr
MOV pc,lr ;r0 is zero, EQ status
] ;AMB_LazyMapIn
......
s/ARM600
View file @ bdc4f843
......@@ -2439,6 +2439,22 @@ UndPreVeneer ROUT
Pull "r0-r7, pc",,^ ; exit to handler, restoring sp_undef and entering SVC26 mode
]
[ No26bitCode :LAND: ChocolateAMB
; Instruction fetch abort pre-veneer, just to field possible lazy AMB aborts
;
PAbPreVeneer ROUT
Push "r0-r7, lr" ; wahey, we have an abort stack
SUB r0, lr_abort, #4 ; aborting address
BL AMB_LazyFixUp ; can trash r0-r7, returns NE status if claimed and fixed up
Pull "r0-r7, lr", NE ; restore regs and
SUBNES pc, lr_abort, #4 ; restart aborting instruction if fixed up
LDR lr, [sp, #8*4] ; (not a lazy abort) restore lr
LDR r0, =PAbHan ; we want to jump to PAb handler, in abort mode
LDR r0, [r0]
STR r0, [sp, #8*4]
Pull "r0-r7, pc"
]
[ :LNOT:No26bitCode
; Instruction fetch abort pre-veneer
......@@ -2494,6 +2510,15 @@ DAbPreVeneer ROUT
STMIA r13_abort, {r0-r7} ; save unbanked registers anyway
STR lr_abort, [r13_abort, #15*4] ; save old PC, ie instruction address
[ ChocolateAMB
ARM_read_FAR r0 ; aborting address
BL AMB_LazyFixUp ; can trash r0-r7, returns NE status if claimed and fixed up
LDR lr_abort, [r13_abort, #15*4] ; restore lr_abort
LDMIA r13_abort, {r0-r7} ; restore regs
ADDNE r13_abort, r13_abort, #17*4 ; if fixed up, restore r13_abort
SUBNES pc, lr_abort, #8 ; and restart aborting instruction
]
MRS r0, SPSR ; r0 = PSR when we aborted
MRS r1, CPSR ; r1 = CPSR
ADD r2, r13_abort, #8*4 ; r2 -> saved register bank for r8 onwards
......
s/ChangeDyn
View file @ bdc4f843
......@@ -2915,8 +2915,16 @@ CheckAppSpace Entry "r0-r3"
SWI XOS_UpCall
CMP r0, #UpCall_Claimed ; if upcall claimed
[ ChocolateAMB
BNE %FT05
BL Do_AMB_MakeUnsparse ; then ok to move memory, so undo laziness and exit
CLRV
EXIT
|
EXIT EQ ; then OK to move memory, so exit (V=0 from CMP)
]
05
ADR r0, ErrorBlock_ChDynamCAO
10
[ International
......@@ -2935,9 +2943,21 @@ CheckAppSpace Entry "r0-r3"
CMP r1, #Service_Serviced
ADREQ r0, ErrorBlock_AplWSpaceInUse ; if service claimed, then return error
BEQ %BT10
[ ChocolateAMB
BL Do_AMB_MakeUnsparse ; undo laziness
]
CLRV ; else OK
EXIT
[ ChocolateAMB
Do_AMB_MakeUnsparse ROUT
Push "r0, lr"
MOVS r0, r10
RSBMI r0, r0, #0
BL AMB_MakeUnsparse ;shrinking AppSpace, so make sure unsparse over area of shrink
Pull "r0, pc"
] ;ChocolateAMB
MakeErrorBlock AplWSpaceInUse
MakeErrorBlock ChDynamCAO
......
s/Kernel
View file @ bdc4f843
......@@ -460,8 +460,12 @@ DefaultPreVeneers
[ No26bitCode
UndPreVeneer * ProcVecPreVeneers+(.-DefaultPreVeneers)
LDR PC, DefaultPreVeneers-ProcVecPreVeneers+UndHan
[ ChocolateAMB
DCD 0
|
PAbPreVeneer * ProcVecPreVeneers+(.-DefaultPreVeneers)
LDR PC, DefaultPreVeneers-ProcVecPreVeneers+PAbHan
]
DCD 0
|
DCD 0
......
s/MemInfo
View file @ bdc4f843
......@@ -557,6 +557,29 @@ MemoryAmounts ROUT
[ HAL
! 0, "Sort out MemoryAmounts"
;
;temp bodge for DRAM,VRAM
;
BICS lr, r0, #&FF ; Get type of memory required (leave bits 12-31, non-zero => error).
BEQ %FT30 ; Don't understand 0 (so the spec says).
TEQ lr, #1:SHL:8
BNE %FT10
MOV r1, #0
LDR r1, [r1, #RAMLIMIT] ; assume 0 VRAM
B %FT20
10
TEQ lr, #2:SHL:8
BNE %FT40 ; not implementing anything else in this bodge
MOV r1, #0 ; assume 0 VRAM
20
MOV r1, r1, LSR #12 ; Return as number of pages.
MOV r2, #4*1024 ; Return page size.
EXIT
30
ADRL r0, ErrorBlock_BadParameters
SETV
40
EXIT
|
BICS lr, r0, #&FF ; Get type of memory required (leave bits 12-31, non-zero => error).
BEQ %FT30 ; Don't understand 0 (so the spec says).
......@@ -602,8 +625,8 @@ MemoryAmounts ROUT
30
ADRL r0, ErrorBlock_BadParameters
SETV
]
EXIT
]
;----------------------------------------------------------------------------------------
......
s/Oscli
View file @ bdc4f843
......@@ -1126,7 +1126,8 @@ esm001 BL expandsyntaxmessage
; r4 is command pointer
FindItem ROUT
Push "R4, R6"
Push "R4, R6, R7"
MRS R7, CPSR ; to remember C flag (32-bit clean)
ADD R2, R2, R1
LDRB R4, [R2]
CMP R4, #0
......@@ -1144,9 +1145,9 @@ FindItem ROUT
CMP R4, R5
ADDEQ R3, R3, #1
BEQ %BT01
CMP R4, #"." ; success if abbreviation
CMP R4, #"." ; success if abbreviation
BEQ %FT02
TST lr, #C_bit
TST R7, #C_bit ; C flag on entry
BEQ %FT07 ; nomatch
CMP R5, #32
BGT %FT07
......@@ -1163,7 +1164,7 @@ FindItem ROUT
CMP R5, #0
BNE %BT05
FindItem_EOTab
Pull "R4, R6"
Pull "R4, R6, R7"
CLC
MOV PC, lr ; back with not found.
......@@ -1205,7 +1206,7 @@ Up_ItAndTerm_Check_Table
CMP R5, #0
BEQ %BT06 ; not a command
STR r6, [stack] ; return r4
Pull "R4, R6"
Pull "R4, R6, R7"
SUB R2, R2, R1 ; get back to offset.
SEC
MOV PC, lr
......
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