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Commit 96e77d80 authored by Jeffrey Lee's avatar Jeffrey Lee
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Add new HAL call, HAL_IRQMax, to allow the kernel to determine the number of... 

Add new HAL call, HAL_IRQMax, to allow the kernel to determine the number of IRQ lines/devices at runtime

Detail:
  hdr/HALEntries - Reuse the old HAL_MonitorLeadID call number for HAL_IRQMax
  hdr/KernelWS - Rearrange CursorChunkAddress workspace a bit. Removed unused OldOscliBuffs and a couple of pre-HAL allocations, and made DefIRQ1Vspace the same size for all build configs. Add an IRQMax var to zero page workspace to cache the value returned by HAL_IRQMax.
  s/HAL - Initialise IRQMax shortly after HAL initialisation. Revise ClearPhysRAM comment to reflect which vars are preserved in the current version of the code.
  s/NewIRQs - Strip out a fair bit of pre-HAL code to make the file more readable. Update OS_ClaimDeviceVector/OS_ReleaseDeviceVector to check against IRQMax instead of the MaxInterrupts compile-time limit.
Admin:
  Tested on BB-xM, Iyonix, RiscPC, Pi
  Although the OS will now nominally adapt at runtime to how many IRQ devices there are, it's still using MaxInterrupts as an upper limit as the device claimant table has a fixed memory allocation.


Version 5.35, 4.79.2.182. Tagged as 'Kernel-5_35-4_79_2_182'
parent 66b9745b
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VersionASM
View file @ 96e77d80
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.181"
Module_Date SETS "17 Jan 2013"
Module_ApplicationDate SETS "17-Jan-13"
Module_MinorVersion SETS "4.79.2.182"
Module_Date SETS "22 Jan 2013"
Module_ApplicationDate SETS "22-Jan-13"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.181)"
Module_HelpVersion SETS "5.35 (17 Jan 2013) 4.79.2.181"
Module_FullVersion SETS "5.35 (4.79.2.182)"
Module_HelpVersion SETS "5.35 (22 Jan 2013) 4.79.2.182"
END
VersionNum
View file @ 96e77d80
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.181
#define Module_Date_CMHG 17 Jan 2013
#define Module_MinorVersion_CMHG 4.79.2.182
#define Module_Date_CMHG 22 Jan 2013
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.181"
#define Module_Date "17 Jan 2013"
#define Module_MinorVersion "4.79.2.182"
#define Module_Date "22 Jan 2013"
#define Module_ApplicationDate "17-Jan-13"
#define Module_ApplicationDate "22-Jan-13"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.181)"
#define Module_HelpVersion "5.35 (17 Jan 2013) 4.79.2.181"
#define Module_FullVersion "5.35 (4.79.2.182)"
#define Module_HelpVersion "5.35 (22 Jan 2013) 4.79.2.182"
#define Module_LibraryVersionInfo "5:35"
hdr/HALEntries
View file @ 96e77d80
......@@ -155,7 +155,7 @@ EntryNo_HAL_PhysInfo # 1 ; 105
EntryNo_HAL_USBControllerInfo # 1 ; 106
# 1 ; 107 (was HAL_MonitorLeadID)
EntryNo_HAL_IRQMax # 1 ; 107 (was HAL_MonitorLeadID)
EntryNo_HAL_VideoRender # 1 ; 108
......
hdr/KernelWS
View file @ 96e77d80
......@@ -1267,6 +1267,7 @@ ProcVecPreVeneersSize * 4*4 ; Space for preveneers for loading handl
ProcVecPreVeneers # ProcVecPreVeneersSize
RTCFitted # 4 ; =0 no RTC, <2048 = address of I2C RTC, >=2048 = HALDevice_RTC ptr
IRQMax # 4 ; from HAL_IRQMax
[ :DEF: ShowWS
! 0, "Free space before DebuggerSpace = ":CC::STR:(&300-@)
......@@ -1772,8 +1773,10 @@ EconetDebugSpace |#| &20 * 4 ; Thirty two words (&7F80)
; *****************************************************************************
; *** Cursor, Sound DMA, SWI, and OSCLI workspace. ***
[ :LNOT: HAL32
; *** Sits in the 32K above 31M, ie. &01F000000..&01F07FFF ***
; *** Has the physical address &02078000, ie. 32M + 512K - 32K ***
]
; *****************************************************************************
TopOfDMAPhysRAM * &80000 ; OFFSET in physram
......@@ -1804,6 +1807,10 @@ Export_SoundWorkSpace |#| SoundWorkSpaceSize + SoundEvtSize
; Note that cursor data memory is expected to be uncacheable, since HAL may use it
; directly for h/w DMA. This may not be true since RO 3.7, but should be sorted
; eventually for next generation RO
;
; Currently (Jan 2013) only the sound DMA buffers are mapped in uncacheable.
; This means CursorData is mapped in cacheable, despite the OS treating it as
; uncacheable.
CursorDataSize * &600 ; four defined shapes, plus 2 holding shapes
CursorData |#| CursorDataSize
......@@ -1856,47 +1863,18 @@ Sound3Buff |#| Sound3BuffSize
SpeechBuff |#| SpeechBuffSize
MouseBuff |#| MouseBuffSize
; Oscli buffering
; IRQ despatch
[ LongCommandLines
OldOscliBuffs |#| (16+1)*&100 ;spare
|
OscliBuffSize * &100
OscliNoBuffs * 16
OscliCircBuffLimit |#| 0
OscliCircBuffStart |#| OscliBuffSize * OscliNoBuffs
RedirectBuff |#| OscliBuffSize
]
MaxInterrupts * 160 ; 160 needed by OMAP4. Increase in future if necessary.
DefIRQ1Vspace * 12*MaxInterrupts+128
; Default IRQ despatch moved here as a result of IOMD having an extra
; 6 interrupts for I/O and sound DMA (this is really IOMD specific, not
; ARM600/700 specific but for the moment it is assumed that they are
; used on the same machines).
[ HAL :LAND: M_CortexA9
DefIRQ1Vspace * 12*160+128
|
[ MorrisSupport
DefIRQ1Vspace * 12*4+12*23+2*256+64 + 7*4+12*16+32+256 ;Morris adds 2 more IRQ registers
|
DefIRQ1Vspace * 12*4+12*23+2*256+64 ; for size checking in MOS
]
] ; HAL :LAND: M_CortexA9
DefaultIRQ1V |#| DefIRQ1Vspace
[ AssemblingArthur :LAND: :DEF: ShowWS
! 0, "Aligning IRQ stack from ":CC::STR:@
]
[ @-7*4 :AND: 15 <> 0
|#| (@-7*4):AND:15
]
[ :LNOT: HAL32
IRQSTK # 0 ; Overflow will give abort
[ AssemblingArthur :LAND: :DEF: ShowWS
! 0, "IRQ stack size ":CC::STR:(IRQSTK-CursorChunkAddress)
]
! 0, "CursorChunkAddress free ":CC::STR:(@-CursorChunkAddress)
]
ASSERT @ > ( CursorChunkAddress + &1000 ) ; Check minimum stack
ASSERT @ >= CursorChunkAddress
; *****************************************************************************
; High system workspace
......
s/HAL
View file @ 96e77d80
......@@ -874,9 +874,15 @@ MMUon_nol1ptoverlap
DebugTX "HAL initialised"
LDR a1, =ZeroPage
LDR v1, [a1, #InitUsedBlock]
LDR v2, [a1, #InitUsedEnd]
MOV a1, #64 ; Old limit prior to OMAP3 port
CallHAL HAL_IRQMax
CMP a1, #MaxInterrupts
MOVHI a1, #MaxInterrupts ; Avoid catastrophic failure if someone forgot to increase MaxInterrupts
LDR a2, =ZeroPage
STR a1, [a2, #IRQMax]
LDR v1, [a2, #InitUsedBlock]
LDR v2, [a2, #InitUsedEnd]
; Start timer zero, at 100 ticks per second
MOV a1, #0
......@@ -907,14 +913,18 @@ MMUon_nol1ptoverlap
LDR v7, [v8, #MaxCamEntry]
LDR a1, [v8, #HAL_StartFlags]
LDR v8, [v8, #IRQMax]
TST a1, #OSStartFlag_RAMCleared
; Clear the memory.
BLEQ ClearPhysRAM
; Put it back
MOV a1, v8
LDR v8, =ZeroPage
STR v4, [v8, #ROMPhysAddr]
STR v5, [v8, #RAMLIMIT]
STR v7, [v8, #MaxCamEntry]
STR a1, [v8, #IRQMax]
; Set v4 to XCB bits for default cacheable+bufferable
LDR v4, [v8, #MMU_PCBTrans]
......@@ -1906,14 +1916,8 @@ Init_PageTablesChanged
; This routine must work in 32-bit mode.
; in: r7 = memory speed
; r8 = page size
; r9 = MEMC control register
; r13 = total RAM size
;
; None of the above are actually used by this routine
;
; out: r7-r9, r13 preserved
; out: r4-r11, r13 preserved
;
ClearPhysRAM ROUT
......
s/NewIRQs
View file @ 96e77d80
......@@ -124,25 +124,19 @@ Initial_IRQ_Code ROUT
; Now copied to RAM, together with vector entries and device tables
ASSERT HAL ; Pre-HAL code is gone. Sorry!
^ 0
[ HAL
IRQDesp_Link # 4
IRQDesp_R12Val # 4
IRQDesp_CallAddr # 4
IRQDesp_Link_Unshared * 1 ; flag in Link (for _this_ node)
|
IRQDesp_R12Val # 4
IRQDesp_CallAddr # 4
IRQDesp_Link # 4
]
ASSERT IRQDesp_CallAddr = IRQDesp_R12Val + 4
ALIGN 32
ASSERT IRQDesp_CallAddr = IRQDesp_R12Val + 4
DefaultIRQ1Vcode ROUT
[ HAL
Push "r9,lr"
[ ZeroPage = 0
MOV r9, #0
......@@ -150,15 +144,11 @@ DefaultIRQ1Vcode ROUT
LDR r9, %FT02
]
AddressHAL r9 ; modifies r9
; MOV r11, r14 ; r11 trashable
CallHAL HAL_IRQSource
Pull "r9"
ADR r2, Devices
ADD r1, r0, r0, LSL #1 ; multiply by 3
; MOV r14, r11
ADD r11, r2, r1, LSL #2 ; so table contains DevNo * 3
; ASSERT IRQDesp_R12Val = 4
; LDMIB r1, {r12, pc}
01 MOV lr, pc
LDMIA r11, {r11, r12, pc}
TST r11, #IRQDesp_Link_Unshared
......@@ -168,38 +158,6 @@ DefaultIRQ1Vcode ROUT
02
DCD ZeroPage
]
|
MOV r3, #IOC ; base for IOC and IOMD
LDRB r0, [r3, #IOMD_DMAREQ]
TEQ r0, #0
ADRNE r1, IrqDMADevnos
LDREQB r0, [r3, #IOCIRQREQB] ; if not DMA then assume IRQB until we know otherwise
ADREQ r1, IrqReqBDevnos
[ MorrisSupport
;>>>RCM Says should we use separate Morris specific code, cos Morris doesn't support
;>>>RCM all IOMD_DMAREQ bits and non Morris machines don't have IOMD_IRQRQD.
;>>>RCM Look at use of NoInterrupt.
ADREQ r12, DeviceTables ; can't reach these tables with ADR
TEQEQ r0, #0
LDREQB r0, [r3, #IOMD_IRQRQD]
ADDEQ r1, r12, #IrqReqDDevnos-DeviceTables
TEQEQ r0, #0
LDREQB r0, [r3, #IOMD_IRQRQC]
ADDEQ r1, r12, #IrqReqCDevnos-DeviceTables
] ; MorrisSupport
TEQEQ r0, #0
LDREQB r0, [r3, #IOCIRQREQA] ; not DMA and not IRQB so assume IRQA
ADREQ r1, IrqReqADevnos
LDRB r0, [r1, r0] ; pick up offset in device despatcher
ADD r1, pc, r0, LSL #2 ; so table contains DevNo * 3
ASSERT IRQDesp_R12Val = 0
LDMIA r1, {r12, pc}
] ; HAL
; ******* IRQ device handlers entered with r0-r3,r11,r12,r14 trashable *******
; r0 = device number (if HAL)
......@@ -207,562 +165,16 @@ DefaultIRQ1Vcode ROUT
; r12 = what they asked for
; r14 = return address to MOS IRQ exit sequence
[ HAL
DefaultIRQ1Vcode_end
Devices * DefaultIRQ1Vcode_end + 12
NoInterrupt * -1
[ M_CortexA9
MaxInterrupts * 160
|
MaxInterrupts * 96
] ; M_CortexA9
DevicesEnd * Devices + MaxInterrupts * 12
ASSERT DevicesEnd - DefaultIRQ1Vcode <= DefIRQ1Vspace
| ; HAL
[ MorrisSupport
NoInterrupt * 38 ; Morris has IOMD's extra interrupts plus 16 of its own
|
NoInterrupt * 22 ; IOMD has 6 more interrupts for DMA
]
Devices
; Register A devices
; pbusy handler
& 0 ; R12 value
& IRQ ; call address
& 0 ; link
; ringing handler
& 0
& IRQ
& 0
; printer acknowledge
& 0
& IRQ
& 0
; vsync handler
& OsbyteVars
& VsyncIRQ
& 0
; power on reset: this can't happen, but call IRQ2V if it does.
& 0
& IRQ
& 0
; timer0
& OsbyteVars
& TickOne
& 0
; timer1
& 0
& IRQ
& 0
; FIQ downgrade
& 0
& IRQ
& 0
; register B devices
; PFIQ downgrade
& PFIQasIRQ_Chain - (PodDesp_Link-PodDesp_R12Val)
& PFIQasIRQ_Despatch
& 0
; sound
& 0
& IRQ
& 0
; serial
& 0
& IRQ
& 0
; winnie IRQ
& 0
& IRQ
& 0
; Disc changed
& 0
& IRQ
& 0
; podule IRQ
& PIRQ_Chain - (PodDesp_Link-PodDesp_R12Val)
& PIRQ_Despatch
& 0
; serial TX (Keyboard serial transmit register empty)
& IOC
[ Keyboard_Type = "A1A500"
& IrqTx
|
& IRQ
]
& 0
; serial RX (Keyboard serial receive register full)
& IOC
[ Keyboard_Type = "A1A500"
& IrqRx
|
& IRQ
]
& 0
; IOMD DMA devices
; DMA channel 0
& 0
& IRQ
& 0
; DMA channel 1
& 0
& IRQ
& 0
; DMA channel 2
& 0
& IRQ
& 0
; DMA channel 3
& 0
& IRQ
& 0
; Sound DMA channel 0
& 0
& IRQ
& 0
; Sound DMA channel 1
& 0
& IRQ
& 0
[ MorrisSupport
; register D devices
; Mouse port Rx full
& IOC
& IRQ
& 0
; Mouse port Tx empty
& IOC
& IRQ
& 0
; AtoD (Joystick)
& 0
& IRQ
& 0
; Nevent1
& 0
& IRQ
& 0
; Nevent2
& 0
& IRQ
& 0
; The following are just place fillers in case IRQD bits 5 to 7 are ever used.
; NoInterrupt
& 0
& IRQ
& 0
; NoInterrupt
& 0
& IRQ
& 0
; NoInterrupt
& 0
& IRQ
& 0
; register C devices
; Bit0
& 0
& IRQ
& 0
; Bit1
& 0
& IRQ
& 0
; Bit2
& 0
& IRQ
& 0
; Bit3
& 0
& IRQ
& 0
; Bit4
& 0
& IRQ
& 0
; Bit5
& 0
& IRQ
& 0
; Bit6
& 0
& IRQ
& 0
; Bit7
& 0
& IRQ
& 0
]
; Neither A or B is interrupting, which is impossible: just call IRQ2V anyway
& 0
& IRQ
& 0
DevicesEnd
; Following tables encode the priority of the devices within each register
;
DeviceTables
; Prioritised IOMD DMA device numbers
IrqDMAPrio0 * 1:SHL:5
IrqDMADev0 * IOMD_DMASound1_DevNo
IrqDMAPrio1 * 1:SHL:4
IrqDMADev1 * IOMD_DMASound0_DevNo
IrqDMAPrio2 * 1:SHL:3
IrqDMADev2 * IOMD_DMAChannel3_DevNo
IrqDMAPrio3 * 1:SHL:2
IrqDMADev3 * IOMD_DMAChannel2_DevNo
IrqDMAPrio4 * 1:SHL:1
IrqDMADev4 * IOMD_DMAChannel1_DevNo
IrqDMAPrio5 * 1:SHL:0
IrqDMADev5 * IOMD_DMAChannel0_DevNo
GBLA DTabC
DTabC SETA 1
IrqDMADevnos
= NoInterrupt*3
; Top 2 bits are always 0 so table need only be 64 bytes
WHILE DTabC <64
[ (DTabC:AND:IrqDMAPrio5)<>0
= IrqDMADev5*3
|
[ (DTabC:AND:IrqDMAPrio4)<>0
= IrqDMADev4*3
|
[ (DTabC:AND:IrqDMAPrio3)<>0
= IrqDMADev3*3
|
[ (DTabC:AND:IrqDMAPrio2)<>0
= IrqDMADev2*3
|
[ (DTabC:AND:IrqDMAPrio1)<>0
= IrqDMADev1*3
|
[ (DTabC:AND:IrqDMAPrio0)<>0
= IrqDMADev0*3
]
]
]
]
]
]
DTabC SETA DTabC+1
WEND
; generic IRQA bits
IrqReqAPrio0 * por_bit
IrqReqADev0 * PowerOn_DevNo
IrqReqAPrio4 * timer1_bit
IrqReqADev4 * Timer1_DevNo
IrqReqAPrio5 * vsync_bit
IrqReqADev5 * VSync_DevNo
IrqReqAPrio6 * timer0_bit
IrqReqADev6 * Timer0_DevNo
IrqReqAPrio7 * force_bit
IrqReqADev7 * FIQDowngrade_DevNo
; Machine specific IRQB bits (devices 0-2)
IrqReqAPrio1 * 1:SHL:1 ; not used
IrqReqADev1 * 1
[ ReassignedIOMDInterrupts
ASSERT IOMDr_PrinterIRQ_DevNo = 2
IrqReqAPrio2 * IOMDr_printer_IRQ_bit
IrqReqADev2 * IOMDr_PrinterIRQ_DevNo
IrqReqAPrio3 * 1:SHL:0 ; not used
IrqReqADev3 * 0
|
ASSERT IOMD_PrinterIRQ_DevNo = 0
ASSERT IOMD_FloppyIndex_DevNo = 2
IrqReqAPrio2 * IOMD_printer_IRQ_bit
IrqReqADev2 * IOMD_PrinterIRQ_DevNo
IrqReqAPrio3 * IOMD_floppy_index_bit
IrqReqADev3 * IOMD_FloppyIndex_DevNo
]
DTabC SETA 1
IrqReqADevnos
= NoInterrupt*3
WHILE DTabC <256
[ (DTabC:AND:IrqReqAPrio7)<>0
= IrqReqADev7*3
|
[ (DTabC:AND:IrqReqAPrio6)<>0
= IrqReqADev6*3
|
[ (DTabC:AND:IrqReqAPrio5)<>0
= IrqReqADev5*3
|
[ (DTabC:AND:IrqReqAPrio4)<>0
= IrqReqADev4*3
|
[ (DTabC:AND:IrqReqAPrio3)<>0
= IrqReqADev3*3
|
[ (DTabC:AND:IrqReqAPrio2)<>0
= IrqReqADev2*3
|
[ (DTabC:AND:IrqReqAPrio1)<>0
= IrqReqADev1*3
|
[ (DTabC:AND:IrqReqAPrio0)<>0
= IrqReqADev0*3
]
]
]
]
]
]
]
]
DTabC SETA DTabC+1
WEND
; generic IRQB bits
IrqReqBPrio2 * podule_FIQ_as_IRQ_bit
IrqReqBDev2 * PFIQasIRQ_DevNo
IrqReqBPrio3 * serial_Tx_bit
IrqReqBDev3 * SerialTx_DevNo
IrqReqBPrio4 * serial_Rx_bit
IrqReqBDev4 * SerialRx_DevNo
IrqReqBPrio5 * podule_IRQ_bit
IrqReqBDev5 * Podule_DevNo
; Machine specific IRQB bits
[ ReassignedIOMDInterrupts
IrqReqBPrio0 * IOMDr_MPEGAudio_IRQ_bit
IrqReqBDev0 * IOMDr_MPEGAudio_DevNo
IrqReqBPrio1 * IOMDr_MPEGVideo_IRQ_bit
IrqReqBDev1 * IOMDr_MPEGVideo_DevNo
IrqReqBPrio6 * IOMDr_Network_IRQ_bit
IrqReqBDev6 * IOMDr_Network_DevNo
IrqReqBPrio7 * IOMDr_serial_IRQ_bit
IrqReqBDev7 * IOMDr_Serial_DevNo
|
IrqReqBPrio0 * IOMD_floppy_IRQ_bit
IrqReqBDev0 * DiscChanged_DevNo
IrqReqBPrio1 * IOMD_HardDisc_IRQ_bit
IrqReqBDev1 * Sound_DevNo
IrqReqBPrio6 * IOMD_Network_IRQ_bit
IrqReqBDev6 * WinnieIRQ_DevNo
IrqReqBPrio7 * IOMD_serial_IRQ_bit
IrqReqBDev7 * IOMD_Serial_DevNo
]
DTabC SETA 1
IrqReqBDevnos
= NoInterrupt*3
WHILE DTabC <256
[ (DTabC:AND:IrqReqBPrio7)<>0
= IrqReqBDev7*3
|
[ (DTabC:AND:IrqReqBPrio6)<>0
= IrqReqBDev6*3
|
[ (DTabC:AND:IrqReqBPrio5)<>0
= IrqReqBDev5*3
|
[ (DTabC:AND:IrqReqBPrio4)<>0
= IrqReqBDev4*3
|
[ (DTabC:AND:IrqReqBPrio3)<>0
= IrqReqBDev3*3
|
[ (DTabC:AND:IrqReqBPrio2)<>0
= IrqReqBDev2*3
|
[ (DTabC:AND:IrqReqBPrio1)<>0
= IrqReqBDev1*3
|
[ (DTabC:AND:IrqReqBPrio0)<>0
= IrqReqBDev0*3
]
]
]
]
]
]
]
]
DTabC SETA DTabC+1
WEND
[ MorrisSupport
; Prioritised IRQD device numbers
IrqReqDPrio0 * 1:SHL:4
IrqReqDDev0 * IOMD_Event2_DevNo
IrqReqDPrio1 * 1:SHL:3
IrqReqDDev1 * IOMD_Event1_DevNo
IrqReqDPrio2 * 1:SHL:2
IrqReqDDev2 * IOMD_AtoD_DevNo
IrqReqDPrio3 * 1:SHL:1
IrqReqDDev3 * IOMD_MouseTxEmpty_DevNo
IrqReqDPrio4 * 1:SHL:0
IrqReqDDev4 * IOMD_MouseRxFull_DevNo
DTabC SETA 1
IrqReqDDevnos
= NoInterrupt*3
; Top 3 bits are always 0 so table need only be 32 bytes (this will
; need to change if bits 5 to 7 are ever used).
WHILE DTabC <32
[ (DTabC:AND:IrqReqDPrio4)<>0
= IrqReqDDev4*3
|
[ (DTabC:AND:IrqReqDPrio3)<>0
= IrqReqDDev3*3
|
[ (DTabC:AND:IrqReqDPrio2)<>0
= IrqReqDDev2*3
|
[ (DTabC:AND:IrqReqDPrio1)<>0
= IrqReqDDev1*3
|
[ (DTabC:AND:IrqReqDPrio0)<>0
= IrqReqDDev0*3
]
]
]
]
]
DTabC SETA DTabC+1
WEND
; Prioritised IRQC device numbers. We have to handle ALL interrupts
; using specific device numbers as we don't know what the IO pins
; are connected to and the NOIRQ code has to know what bit to clear
; when an unknown interrupt is triggered.
IrqReqCPrio0 * 1:SHL:0
IrqReqCDev0 * IOMD_C_Bit0_DevNo
IrqReqCPrio1 * 1:SHL:1
IrqReqCDev1 * IOMD_C_Bit1_DevNo
IrqReqCPrio2 * 1:SHL:2
IrqReqCDev2 * IOMD_C_Bit2_DevNo
IrqReqCPrio3 * 1:SHL:3
IrqReqCDev3 * IOMD_C_Bit3_DevNo
IrqReqCPrio4 * 1:SHL:4
IrqReqCDev4 * IOMD_C_Bit4_DevNo
IrqReqCPrio5 * 1:SHL:5
IrqReqCDev5 * IOMD_C_Bit5_DevNo
IrqReqCPrio6 * 1:SHL:6
IrqReqCDev6 * IOMD_C_Bit6_DevNo
IrqReqCPrio7 * 1:SHL:7
IrqReqCDev7 * IOMD_C_Bit7_DevNo
DTabC SETA 1
IrqReqCDevnos
= NoInterrupt*3
WHILE DTabC <256
[ (DTabC:AND:IrqReqCPrio7)<>0
= IrqReqCDev7*3
|
[ (DTabC:AND:IrqReqCPrio6)<>0
= IrqReqCDev6*3
|
[ (DTabC:AND:IrqReqCPrio5)<>0
= IrqReqCDev5*3
|
[ (DTabC:AND:IrqReqCPrio4)<>0
= IrqReqCDev4*3
|
[ (DTabC:AND:IrqReqCPrio3)<>0
= IrqReqCDev3*3
|
[ (DTabC:AND:IrqReqCPrio2)<>0
= IrqReqCDev2*3
|
[ (DTabC:AND:IrqReqCPrio1)<>0
= IrqReqCDev1*3
|
[ (DTabC:AND:IrqReqCPrio0)<>0
= IrqReqCDev0*3
]
]
]
]
]
]
]
]
DTabC SETA DTabC+1
WEND
]
DefaultIRQ1Vcode_end
ASSERT DefaultIRQ1Vcode_end - DefaultIRQ1Vcode <= DefIRQ1Vspace
] ; :LNOT: HAL
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
InitialiseIRQ1Vtable
......@@ -780,7 +192,6 @@ CopyDefaultIRQ1V
CMP a2, a3
BNE CopyDefaultIRQ1V
[ HAL
AddressHAL
ADD v1, a1, #12
ADD a3, v1, #MaxInterrupts*12
......@@ -811,12 +222,6 @@ FillInDefaultIRQ1VDevices
ADDNE a1, a1, a1, LSL #1
ADDNE a1, v1, a1, LSL #2
STMNEIB a1, {a2, a3}
; BNE %ft1
; ; here if no vsync handler .. fudge it from tickerv
; MOV a1, #TickerV
; LDR a2, =FalseVsyncIRQ
; LDR a3, =OsbyteVars
; SWI XOS_Claim
1
[ CDVPoduleIRQs
......@@ -854,7 +259,7 @@ FillInDefaultIRQ1VDevices
ADD v3, v3, #1
CMP v3, #IICBus_Count
BNE %BT80
]
Pull "v1-v3,sb,pc"
......@@ -964,7 +369,9 @@ DeviceVector_Claim ROUT
[ HAL
BIC r0, r0, #CDV_Flags
]
CMP r0, #MaxInterrupts
LDR lr, =ZeroPage
LDR lr, [lr, #IRQMax]
CMP r0, lr
BHS DV_Fail_NaffDevNo
[ HAL:LAND:{FALSE}
......@@ -1099,7 +506,9 @@ DeviceVector_Release ROUT
[ HAL
BIC r0, r0, #CDV_Flags
]
CMP r0, #MaxInterrupts
LDR lr, =ZeroPage
LDR lr, [lr, #IRQMax]
CMP r0, lr
BHS DV_Fail_NaffDevNo
WritePSRc SVC_mode + I_bit, r12 ; IRQs off while holding context
......
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