Add workaround for Cortex-A7 errata 814220

Detail:
  s/ARMops, s/HAL - Errata 814220 states that the Cortex-A7 set/way cache maintenance operations violate the usual operation ordering rules, such that an L2 maintenance operation which is started after an L1 operation may actually complete before it, causing data corruption if the L1 data was to be evicted to the L2 entry. Implement the suggested workaround of performing a DSB when switching cache levels, rather than just at the end of the combined L1+L2 group of operations.
Admin:
  Tested on Raspberry Pi 2


Version 5.35, 4.79.2.257. Tagged as 'Kernel-5_35-4_79_2_257'

VersionASM

@@ -13,11 +13,11 @@
                         GBLS    Module_ComponentPath
 Module_MajorVersion     SETS    "5.35"
 Module_Version          SETA    535
-Module_MinorVersion     SETS    "4.79.2.256"
-Module_Date             SETS    "02 Feb 2015"
-Module_ApplicationDate  SETS    "02-Feb-15"
+Module_MinorVersion     SETS    "4.79.2.257"
+Module_Date             SETS    "07 Feb 2015"
+Module_ApplicationDate  SETS    "07-Feb-15"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.35 (4.79.2.256)"
-Module_HelpVersion      SETS    "5.35 (02 Feb 2015) 4.79.2.256"
+Module_FullVersion      SETS    "5.35 (4.79.2.257)"
+Module_HelpVersion      SETS    "5.35 (07 Feb 2015) 4.79.2.257"
                         END

VersionNum

@@ -5,19 +5,19 @@
  *
  */
 #define Module_MajorVersion_CMHG        5.35
-#define Module_MinorVersion_CMHG        4.79.2.256
-#define Module_Date_CMHG                02 Feb 2015
+#define Module_MinorVersion_CMHG        4.79.2.257
+#define Module_Date_CMHG                07 Feb 2015
 
 #define Module_MajorVersion             "5.35"
 #define Module_Version                  535
-#define Module_MinorVersion             "4.79.2.256"
-#define Module_Date                     "02 Feb 2015"
+#define Module_MinorVersion             "4.79.2.257"
+#define Module_Date                     "07 Feb 2015"
 
-#define Module_ApplicationDate          "02-Feb-15"
+#define Module_ApplicationDate          "07-Feb-15"
 
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.35 (4.79.2.256)"
-#define Module_HelpVersion              "5.35 (02 Feb 2015) 4.79.2.256"
+#define Module_FullVersion              "5.35 (4.79.2.257)"
+#define Module_HelpVersion              "5.35 (07 Feb 2015) 4.79.2.257"
 #define Module_LibraryVersionInfo       "5:35"

s/ARMops

@@ -1970,11 +1970,11 @@ MMU_ChangingUncachedEntries_WB_Cal_LD ROUT
         BGE     %BT30
         SUBS    r7, r7, #1 ; decrement the way number
         BGE     %BT20
+        myDSB   ,r7        ; Cortex-A7 errata 814220: DSB required when changing cache levels when using set/way operations. This also counts as our end-of-maintenance DSB.
 40 ; Skip
         ADD     r8, r8, #2
         CMP     r3, r8
         BGT     %BT10
-        myDSB   ,r0
 50 ; Finished
         MEND
 

s/HAL

@@ -1415,6 +1415,7 @@ HAL_InvalidateCache_ARMvF
         BGE     %BT30
         SUBS    r8, r8, #1 ; decrement the way number
         BGE     %BT20
+        myDSB   ,r8        ; Cortex-A7 errata 814220: DSB required when changing cache levels when using set/way operations. This also counts as our end-of-maintenance DSB.
         MRC     p15, 0, r8, c0, c0, 1
 40 ; Skip
         ADD     r11, r11, #2
@@ -1425,7 +1426,6 @@ HAL_InvalidateCache_ARMvF
 50 ; Finished
         ; Wait for clean to complete
         MOV     r8, #0
-        myDSB   ,r8,,y
         MCR     p15, 0, r8, c7, c5, 0           ; invalidate instruction cache
         MCR     p15, 0, r8, c8, c7, 0           ; invalidate TLBs
         MCR     p15, 0, r8, c7, c5, 6           ; invalidate branch target predictor