Skip to content

GitLab

Commit 5e11e665 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

OS_ChangeDynamicArea performance optimisations 

Detail:
  s/ChangeDyn:
    - Apply various optimisations to OS_ChangeDynamicArea to reduce the execution time when performing large grows/shrinks.
    - Optimisations can be toggled on/off with FastCDA_* flags for debugging.
    - On a 1GHz 512MB BB-xM, the initial *FreePool call now takes 0.15s instead of 13.46s. On a 512MB Iyonix the time has dropped from 1.18s to 0.23s.
    - Growing screen memory (on BB-xM) has also seen significant gains - between 2x and 4x speedup, depending on what state the source pages are in.
    - Added/updated documentation for a few functions and made more use of ROUTs for safety
  s/ARM600, s/VMSAv6:
    - Update BangCamUpdate, etc. to add support for the PageFlags_Unsafe flag that OS_ChangeDynamicArea uses to bypass cache/TLB maintenance in some situations
    - Avoid BangCamUpdate calling BangL2PT to map out the page if the page isn't mapped in (avoids unnecessary cache/TLB flush)
  s/ArthurSWIs:
    - Add extra ASSERT for safety
  s/AMBcontrol/memory
    - Fix incorrect assumption that the usable size of a heap block is always 8 less than the value stored in the header. Even with the old 8 byte aligned allocations the usable size will always be 4 bytes less than the value in the header. This code would have resulted in some slight memory wasteage, as AMBcontrol will have always tried growing the block four bytes bigger than needed.
Admin:
  Tested on Iyonix & BB-xM


Version 5.35, 4.79.2.146. Tagged as 'Kernel-5_35-4_79_2_146'
parent 8e91915b
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 417 additions and 36 deletions
VersionASM
View file @ 5e11e665
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.145"
Module_Date SETS "08 Apr 2012"
Module_ApplicationDate SETS "08-Apr-12"
Module_MinorVersion SETS "4.79.2.146"
Module_Date SETS "15 Apr 2012"
Module_ApplicationDate SETS "15-Apr-12"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.145)"
Module_HelpVersion SETS "5.35 (08 Apr 2012) 4.79.2.145"
Module_FullVersion SETS "5.35 (4.79.2.146)"
Module_HelpVersion SETS "5.35 (15 Apr 2012) 4.79.2.146"
END
VersionNum
View file @ 5e11e665
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.145
#define Module_Date_CMHG 08 Apr 2012
#define Module_MinorVersion_CMHG 4.79.2.146
#define Module_Date_CMHG 15 Apr 2012
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.145"
#define Module_Date "08 Apr 2012"
#define Module_MinorVersion "4.79.2.146"
#define Module_Date "15 Apr 2012"
#define Module_ApplicationDate "08-Apr-12"
#define Module_ApplicationDate "15-Apr-12"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.145)"
#define Module_HelpVersion "5.35 (08 Apr 2012) 4.79.2.145"
#define Module_FullVersion "5.35 (4.79.2.146)"
#define Module_HelpVersion "5.35 (15 Apr 2012) 4.79.2.146"
#define Module_LibraryVersionInfo "5:35"
s/AMBControl/Memory
View file @ 5e11e665
......@@ -50,7 +50,7 @@ AMB_BlockResize ROUT
ADD r3,r3,#AMBblockQ - 1
BIC r3,r3,#AMBblockQ - 1
LDR r1,[r2,#-4] ;pick up OS_Heap's size word (naughty!)
SUB r1,r1,#8 ;heap size will be 8 more than quantised size
SUB r1,r1,#4 ;heap size will be (at least) 4 more than quantised size
SUBS r3,r3,r1 ;required size change
MOVNE r0, #HeapReason_ExtendBlock
BLNE DoSysHeapOpWithExtension
......
s/ARM600
View file @ 5e11e665
......@@ -218,7 +218,8 @@ BangCamUpdate ROUT
LDR r1, [r1, #CamEntriesPointer]
ADD r1, r1, r2, LSL #3 ; point at cam entry (logaddr, PPL)
LDMIA r1, {r0, r6} ; r0 = current logaddress, r6 = current PPL
STMIA r1, {r3, r11} ; store new address, PPL
BIC r4, r11, #PageFlags_Unsafe
STMIA r1, {r3, r4} ; store new address, PPL
Push "r0, r6" ; save old logical address, PPL
LDR r1, =ZeroPage+PhysRamTable ; go through phys RAM table
MOV r6, r2 ; make copy of r2 (since that must be preserved)
......@@ -248,11 +249,15 @@ BangCamUpdate ROUT
TEQ r4, r0, LSR #12 ; if equal to physical address of page being moved
BNE %FT20 ; if not there, then just put in new page
AND r4, r11, #PageFlags_Unsafe
Push "r0, r3, r11, r14" ; save phys.addr, new log.addr, new PPL, lr
ADD r3, sp, #4*4
LDMIA r3, {r3, r11} ; reload old logical address, old PPL
LDR r0, =DuffEntry ; Nothing to do if wasn't mapped in
ORR r11, r11, r4
TEQ r3, r0
MOV r0, #0 ; cause translation fault
BL BangL2PT ; map page out
BLNE BangL2PT ; map page out
Pull "r0, r3, r11, r14"
20
ADD sp, sp, #8 ; junk old logical address, PPL
......@@ -340,6 +345,9 @@ BangL2PT ; internal entry point used only
Push "lr"
MOV r6, r0
TST r11, #PageFlags_Unsafe
BNE %FT30
TST r11, #DynAreaFlags_DoublyMapped
BNE BangL2PT_sledgehammer ;if doubly mapped, don't try to be clever
......
s/ArthurSWIs
View file @ 5e11e665
......@@ -1083,6 +1083,7 @@ fakeservicecall
MOV r0, r0
LDR r10, =ZeroPage
LDRB r9, [r10, #FIQclaim_interlock]
ASSERT (ZeroPage :AND: 255) = 0
STRB r10, [r10, #FIQclaim_interlock]
[ FIQDebug
......
s/ChangeDyn
View file @ 5e11e665
This diff is collapsed.
s/VMSAv6
View file @ 5e11e665
......@@ -75,7 +75,8 @@ BangCamUpdate ROUT
LDR r1, [r1, #CamEntriesPointer]
ADD r1, r1, r2, LSL #3 ; point at cam entry (logaddr, PPL)
LDMIA r1, {r0, r6} ; r0 = current logaddress, r6 = current PPL
STMIA r1, {r3, r11} ; store new address, PPL
BIC r4, r11, #PageFlags_Unsafe
STMIA r1, {r3, r4} ; store new address, PPL
Push "r0, r6" ; save old logical address, PPL
LDR r1, =ZeroPage+PhysRamTable ; go through phys RAM table
MOV r6, r2 ; make copy of r2 (since that must be preserved)
......@@ -105,11 +106,15 @@ BangCamUpdate ROUT
TEQ r4, r0, LSR #12 ; if equal to physical address of page being moved
BNE %FT20 ; if not there, then just put in new page
AND r4, r11, #PageFlags_Unsafe
Push "r0, r3, r11, r14" ; save phys.addr, new log.addr, new PPL, lr
ADD r3, sp, #4*4
LDMIA r3, {r3, r11} ; reload old logical address, old PPL
LDR r0, =DuffEntry ; Nothing to do if wasn't mapped in
ORR r11, r11, r4
TEQ r3, r0
MOV r0, #0 ; cause translation fault
BL BangL2PT ; map page out
BLNE BangL2PT ; map page out
Pull "r0, r3, r11, r14"
20
ADD sp, sp, #8 ; junk old logical address, PPL
......@@ -197,6 +202,9 @@ BangL2PT ; internal entry point used only
Push "lr"
MOV r6, r0
TST r11, #PageFlags_Unsafe
BNE %FT30
TST r11, #DynAreaFlags_DoublyMapped
BNE BangL2PT_sledgehammer ;if doubly mapped, don't try to be clever
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment