Add compressed ROM support. Make more use of ARMv5+ instructions. Other misc tweaks.

Detail:
  hdr/OSEntries, s/HAL, s/Kernel - Add compressed ROM support.
  With the current scheme, a compressed ROM will have everything except the HAL and kernel compressed.
  During the keyboard scan period the kernel will allocate some temporary decompression workspace and call the decompression stub that was appended to the ROM.
  The decompression stub is expected to perform in-place decompression of the ROM. Once decompression is complete the workspace will be freed and the page tables updated to make the ROM image readonly.
  It's the HAL's responsibility to make sure any compressed ROM is located in an area of physically contiguous RAM large enough to hold the uncompressed image.
  More info here: http://www.riscosopen.org/wiki/documentation/show/Compressed%20ROMs
  Makefile, h/OSEntries - Add C export of hdr/OSEntries
  hdr/HALDevice - Add device ID for Tungsten video device. Convert tabs to spaces for consistency.
  hdr/HALEntries, s/NewReset - Moved KbdFlag_* definitions to hdr/HALEntries so HALs can use them in their keyboard scan code
  s/ArthurSWIs, S/HAL, s/HeapSort, s/Kernel, s/MemInfo, s/Middle, s/NewIRQs, s/TickEvents, s/vdu/vdugrafb - Make use of BLX, BFI and long multiplies if the CPU supports them. Don't support SWI calls from thumb mode if the CPU doesn't support thumb.
  s/HAL - Made the LDMIA in Init_MapInRAM more sensible (register order was backwards). The old code did work, but wasn't doing what the comments described. Removed unused/unfinished HAL_Write0 function. Improve RISCOS_LogToPhys to check L1PT for any section mappings if the logical_to_physical call fails
  s/ModHand - Save one instruction by using ADR instead of MOV+ADD to compute lr
  s/NewReset, s/PMF/key - Pass L1PT to HAL_Reset to allow machines without hardware reset (e.g. IOMD) to perform resets by manually disabling the MMU and restarting the ROM
  s/vdu/vdudriver, s/vdu/vdugrafv - Use GVEntry macro borrowed from NVidia module for setting up the GraphicsV jump table. Make GraphicsV_ReadPaletteEntry call HAL_Video_ReadPaletteEntry if left unclaimed. Fixup GV_Render to only call HAL_Video_Render if the HAL call is implemented.
Admin:
  Tested with OMAP3, IOMD & Tungsten ROMs/softloads.


Version 5.35, 4.79.2.138. Tagged as 'Kernel-5_35-4_79_2_138'

Makefile

@@ -197,9 +197,9 @@ ${C_EXP_HDR}.HALDevice: o.Global.h.HALDevice h.HALDevice
 	${CP} h.HALDevice $@ ${CPFLAGS}
 	print o.Global.h.HALDevice { >> $@ }
 
-${C_EXP_HDR}.OSEntries: hdr.OSEntries
-	${MKDIR} ${C_EXP_HDR}
-	${PERL} Build:Hdr2H hdr.OSEntries $@
+${C_EXP_HDR}.OSEntries: o.Global.h.OSEntries h.OSEntries
+	${CP} h.OSEntries $@ ${CPFLAGS}
+	print o.Global.h.OSEntries { >> $@ }
 
 ${C_EXP_HDR}.Variables: hdr.Variables
 	${MKDIR} ${C_EXP_HDR}
@@ -215,6 +215,12 @@ o.Global.h.HALDevice: hdr.HALDevice
 	${PERL} Build:Hdr2H ^.hdr.HALDevice Global.h.HALDevice
 	back
 
+o.Global.h.OSEntries: hdr.OSEntries
+	${MKDIR} o.Global.h
+	dir o
+	${PERL} Build:Hdr2H ^.hdr.OSEntries Global.h.OSEntries
+	back
+
 BBETYPE = kernel
 bbe-kernel: bbe-generic-resources-get-alias
 	BBE_Export_File_In_Dir Resources.${LOCALE} CmdHelp

VersionASM

@@ -13,11 +13,11 @@
                         GBLS    Module_ComponentPath
 Module_MajorVersion     SETS    "5.35"
 Module_Version          SETA    535
-Module_MinorVersion     SETS    "4.79.2.137"
+Module_MinorVersion     SETS    "4.79.2.138"
 Module_Date             SETS    "25 Feb 2012"
 Module_ApplicationDate  SETS    "25-Feb-12"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.35 (4.79.2.137)"
-Module_HelpVersion      SETS    "5.35 (25 Feb 2012) 4.79.2.137"
+Module_FullVersion      SETS    "5.35 (4.79.2.138)"
+Module_HelpVersion      SETS    "5.35 (25 Feb 2012) 4.79.2.138"
                         END

VersionNum

@@ -5,12 +5,12 @@
  *
  */
 #define Module_MajorVersion_CMHG        5.35
-#define Module_MinorVersion_CMHG        4.79.2.137
+#define Module_MinorVersion_CMHG        4.79.2.138
 #define Module_Date_CMHG                25 Feb 2012
 
 #define Module_MajorVersion             "5.35"
 #define Module_Version                  535
-#define Module_MinorVersion             "4.79.2.137"
+#define Module_MinorVersion             "4.79.2.138"
 #define Module_Date                     "25 Feb 2012"
 
 #define Module_ApplicationDate          "25-Feb-12"
@@ -18,6 +18,6 @@
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.35 (4.79.2.137)"
-#define Module_HelpVersion              "5.35 (25 Feb 2012) 4.79.2.137"
+#define Module_FullVersion              "5.35 (4.79.2.138)"
+#define Module_HelpVersion              "5.35 (25 Feb 2012) 4.79.2.138"
 #define Module_LibraryVersionInfo       "5:35"

h/OSEntries

+/* Copyright 2012 Castle Technology Ltd
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef GLOBAL_OSENTRIES_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+typedef struct {
+  uint32_t Magic;
+  uint32_t Flags;
+  uint32_t ImageSize;
+  uint32_t Entries;
+  uint32_t NumEntries;
+  uint32_t CompressedSize;
+  uint32_t DecompressHdr;
+  uint32_t CompressOffset;
+} OSHdr;
+
+typedef struct {
+  uint32_t WSSize;
+  uint32_t Code;
+} OSDecompHdr;
+
+#define OSHdr_Magic_Value (0x6d49534f) /* 'OSIm' */
+
+#endif
+/* In the exported copy of this file, the Hdr2H translation of hdr.OSEntries will follow. */

hdr/HALDevice

@@ -106,38 +106,39 @@ HALDeviceInterconnectBus_L4  *  1 :SHL: 24
                                 ^       0
 HALDeviceID_AudC_M5451          #       1
 HALDeviceID_AudC_TPS65950       #       1
-HALDeviceID_AudC_TWL6040	#	1
+HALDeviceID_AudC_TWL6040        #       1
 
                                 ^       0
 HALDeviceID_Mixer_STAC9750      #       1
 HALDeviceID_Mixer_TPS65950      #       1
-HALDeviceID_Mixer_TWL6040	#	1
+HALDeviceID_Mixer_TWL6040       #       1
 
                                 ^       0
 HALDeviceID_DMAC_M1535          #       1
 HALDeviceID_DMAC_M5229          #       1
 HALDeviceID_DMAC_OMAP3          #       1
-HALDeviceID_DMAC_OMAP4		#	1
+HALDeviceID_DMAC_OMAP4          #       1
 
                                 ^       0
 HALDeviceID_DMAB_M1535          #       1
 HALDeviceID_DMAB_OMAP3          #       1
-HALDeviceID_DMAB_OMAP4		#	1
+HALDeviceID_DMAB_OMAP4          #       1
 
                                 ^       0
 HALDeviceID_DMAL_M5229          #       1
 
                                 ^       0
 HALDeviceID_RTC_TPS65950        #       1
-HALDeviceID_RTC_TWL6030		#	1
+HALDeviceID_RTC_TWL6030         #       1
 
                                 ^       0
 HALDeviceID_CPUClk_OMAP3        #       1
-HALDeviceID_CPUClk_OMAP4	#	1
+HALDeviceID_CPUClk_OMAP4        #       1
 
                                 ^       0
 HALDeviceID_VDU_OMAP3           #       1
-HALDeviceID_VDU_OMAP4		#	1
+HALDeviceID_VDU_OMAP4           #       1
+HALDeviceID_VDU_Tungsten        #       1
 
                                 ^       0
 HALDeviceID_EtherNIC_SMSC9221   #       1
@@ -145,7 +146,7 @@ HALDeviceID_EtherNIC_DM9000     #       1
 
                                 ^       0
 HALDeviceID_GPIO_OMAP3          #       1
-HALDeviceID_GPIO_OMAP4		#	1
+HALDeviceID_GPIO_OMAP4          #       1
 
                                 ^       0
 HALDeviceID_SDIO_SDHCI          #       1

hdr/HALEntries

@@ -194,4 +194,15 @@ IICFlag_Background      * 1:SHL:4
 IICFlag_Fast            * 1:SHL:16
 IICFlag_HighSpeed       * 1:SHL:17
 
+; Keyboard scan
+
+KbdFlag_Ctrl    * 1:SHL:0
+KbdFlag_Shift   * 1:SHL:1
+KbdFlag_R       * 1:SHL:4
+KbdFlag_T       * 1:SHL:5
+KbdFlag_Delete  * 1:SHL:6
+KbdFlag_Copy    * 1:SHL:7
+KbdFlag_Present * 1:SHL:30
+KbdFlag_Done    * 1:SHL:31
+
         END

hdr/OSEntries

@@ -26,13 +26,19 @@ OS_IICOpV       #       1
 HighestOSEntry  *       :INDEX: @ - 1
 
 ; The layout of the OS header
-                ^       0
-OSHdr_Magic     #       4
-OSHdr_Flags     #       4
-OSHdr_ImageSize #       4
-OSHdr_Entries   #       4
-OSHdr_NumEntries #      4
-OSHdr_size      #       0
+                     ^  0
+OSHdr_Magic          #  4 ; = "OSIm"
+OSHdr_Flags          #  4
+OSHdr_ImageSize      #  4 ; Size of image after decompression
+OSHdr_Entries        #  4 ; Offset from header start to entry point table
+OSHdr_NumEntries     #  4
+OSHdr_CompressedSize #  4 ; Same as OSHdr_ImageSize if not compressed
+OSHdr_DecompressHdr  #  4 ; Offset from header start to decompression header. 0 if not compressed.
+OSHdr_CompressOffset #  4 ; Offset at which compression should be performed
+OSHdr_size           #  0
+
+OSHdrFlag_SupportsCompression * 1 ; OS supports compressed images
+OSHdr_ValidFlags              * 1 ; Mask of all valid flags
 
 ; Parameters/flag for various calls
 
@@ -42,4 +48,10 @@ OSStartFlag_CMOSReset       * 1:SHL:2	; CMOS reset (if POR and not inhibited)
 OSStartFlag_NoCMOS  	    * 1:SHL:3	; There's no real NVRAM, only cache
 OSStartFlag_RAMCleared      * 1:SHL:4   ; RAM has been cleared to zero
 
+; Decompression header block
+                    ^  0
+OSDecompHdr_WSSize  #  4 ; Required workspace size (multiple of 4K)
+OSDecompHdr_Code    #  4 ; Offset from header start to decompression code
+OSDecompHdr_size    #  0
+
                 END

s/ArthurSWIs

@@ -243,7 +243,7 @@ Read64BitNumberInBase ALTENTRY
 10      BL      GetCharForReadNumber
         BNE     %BT50           ; Finished ?
 
-      [ :LNOT: NoARMv4
+      [ :LNOT: NoARMM
         TST     r5, #&F8000000  ; If EQ, can't possibly overflow in any base up to 26
         MULEQ   r5, r4, r5      ; r0,r5 = new_digit + (old_msw * base)<<32
         UMLALEQ r0, r5, r4, r2  ; r0,r5 += old_lsw * base
@@ -870,8 +870,12 @@ Issue_Service ROUT             ; R1 is service number, R2 may be a parameter
        MOVNE    R1,R9                           ; else pass R1 value from chain (will be service index)
        LDR      R12,[R11,#ServEntry_WSpace]
        LDR      R9,[R11,#ServEntry_Code]
+     [ NoARMv5
        MOV      lr, pc                          ; link inc. PSR, mode
        MOV      pc, R9
+     |
+       BLX      R9
+     ]
        CMP      R1, #Service_Serviced
        MOVNE    R1,R10                          ; restore R1 unless claimed
        Pull     "R10"
@@ -916,8 +920,12 @@ Issue_Service ROUT             ; R1 is service number, R2 may be a parameter
        BHS      %FT01
        LDR      R12,[R11,#ServEntry_WSpace]
        LDR      R9,[R11,#ServEntry_Code]
+     [ NoARMv5
        MOV      lr, pc                          ; link inc. PSR, mode
        MOV      pc, R9
+     |
+       BLX      R9
+     ]
        CMP      R1, #Service_Serviced
        BEQ      %FT01
        ADD      R11,R11,#ServEntry_SIZEOF
@@ -949,8 +957,12 @@ Issue_Service ROUT             ; R1 is service number, R2 may be a parameter
        ]
 
        ADD      R12, R11, #Incarnation_Workspace
+     [ NoARMv5
        MOV      lr, pc               ; link inc. PSR, mode
        MOV      pc, R9
+     |
+       BLX      R9
+     ]
 
        [ DebugNeil
        ! 0, "Debug code included to check R7-R11 are preserved over services"
@@ -1188,9 +1200,14 @@ CallAVector_SWI  ; R9 is the vector number (!!)
        BL        CallVector
        MRS       r10, CPSR              ; restore CCs
        LDR       lr, [sp], #4
+     [ NoARMT2
        AND       r10, r10, #&F0000000
        BIC       lr, lr, #&F0000000
        ORR       lr, lr, r10
+     |
+       MOV       r10, r10, LSR #28
+       BFI       lr, r10, #28, #4
+     ]
        ExitSWIHandler
 
 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

s/HAL

@@ -587,7 +587,10 @@ RISCOS_Start
         ADD     a3, a3, ip
         ADD     a4, a4, ip
         STMIB   sp, {a3, a4}
-        MOV     a3, #(AP_ROM * L2X_APMult) + L2_C + L2_B
+        LDR     a3, [v5, #OSHdr_DecompressHdr]  ; check if ROM is compressed, and if so, make writeable
+        CMP     a3, #0
+        MOVNE   a3, #(AP_Full * L2X_APMult) + L2_C + L2_B
+        MOVEQ   a3, #(AP_ROM * L2X_APMult) + L2_C + L2_B
         SUB     a4, v7, v6
         BL      Init_MapIn
         MOV     a3, v6
@@ -613,7 +616,10 @@ RISCOS_Start
         ADD     a3, a3, ip
         STR     a3, [sp, #4]
         SUB     a4, v7, v5
-        MOV     a3, #(AP_ROM * L2X_APMult) + L2_C + L2_B
+        LDR     a3, [v5, #OSHdr_DecompressHdr]
+        CMP     a3, #0
+        MOVNE   a3, #(AP_Full * L2X_APMult) + L2_C + L2_B
+        MOVEQ   a3, #(AP_ROM * L2X_APMult) + L2_C + L2_B
         BL      Init_MapIn
         MOV     a3, v5
 75
@@ -631,7 +637,7 @@ RISCOS_Start
         ; Set up a reset IRQ handler (used during RAM clear for keyboard
         ; scan, and later for IIC CMOS access)
         MSR     CPSR_c, #IRQ32_mode + I32_bit + F32_bit
-        LDR     sp_irq, =ScratchSpace + ScratchSpaceSize/2
+        LDR     sp_irq, =ScratchSpace + 1024    ; 1K is plenty since Reset_IRQ_Handler now runs in SVC mode
         MSR     CPSR_c, #SVC32_mode + I32_bit + F32_bit
         LDR     a2, =Reset_IRQ_Handler
         STR     a2, [a1, #InitIRQHandler]
@@ -940,6 +946,134 @@ MMUon_nol1ptoverlap
         ADD     sp, sp, #5*4
 
 20
+; Decompress the ROM
+        LDR     a1, =RISCOS_Header
+        LDR     a2, [a1, #OSHdr_DecompressHdr]
+        CMP     a2, #0
+        BEQ     %FT30
+        ADD     ip, a1, a2
+        ASSERT  OSDecompHdr_WSSize = 0
+        ASSERT  OSDecompHdr_Code = 4
+        LDMIA   ip, {a3-a4}
+        ADRL    a2, SyncCodeAreas
+        CMP     a3, #0 ; Any workspace required?
+        ADD     a4, a4, ip
+   [ DebugHALTX
+        BNE     %FT25
+        DebugTX "Decompressing ROM, no workspace required"
+      [ NoARMv5
+        MOV     lr, pc
+        MOV     pc, a4
+      |
+        BLX     a4
+      ]
+        DebugTX "Decompression complete"
+        B       %FT27
+25
+   |
+        ADREQ   lr, %FT27
+        MOVEQ   pc, a4
+   ]
+        Push    "a1-a4,v1-v2,v5-v7"
+; Allocate workspace for decompression code
+; Workspace is located at a 4MB-aligned log addr, and is a multiple of 1MB in
+; size. This greatly simplifies the code required to free the workspace, since
+; we can guarantee it will have been section-mapped, and won't hit any
+; partially-allocated L2PT blocks (where 4 L1PT entries point to subsections of
+; the same L2PT page)
+; This means all we need to do to free the workspace is zap the L1PT entries
+; and rollback v1 & v2
+; Note: This is effectively a MB-aligned version of Init_MapInRAM
+        DebugTX "Allocating decompression workspace"
+        LDR     v5, =(1<<20)-1
+        ADD     v7, a3, v5
+        BIC     v7, v7, v5 ; MB-aligned size
+        STR     v7, [sp, #8] ; Overwrite stacked WS size
+        MOV     v6, #4<<20 ; Current log addr
+26
+        ADD     v2, v2, v5
+        BIC     v2, v2, v5 ; MB-aligned physram
+        LDMIA   v1, {a2, a3}
+        SUB     a2, v2, a2 ; Amount of bank used
+        SUB     a2, a3, a2 ; Amount of bank remaining
+        MOVS    a2, a2, ASR #20 ; Round down to nearest MB
+        LDRLE   v2, [v1, #8]! ; Move to next bank if 0MB left
+        BLE     %BT26
+        CMP     a2, v7, LSR #20
+        MOVHS   a4, v7
+        MOVLO   a4, a2, LSL #20 ; a4 = amount to take
+        MOV     a1, v2 ; set up parameters for MapIn call
+        MOV     a2, v6
+        ORR     a3, v4, #AP_None * L2X_APMult
+        SUB     v7, v7, a4 ; Decrease amount to allocate
+        ADD     v2, v2, a4 ; Increase physram ptr
+        ADD     v6, v6, a4 ; Increase logram ptr
+        BL      Init_MapIn
+        CMP     v7, #0
+        BNE     %BT26
+        Pull    "a1-a2,v1-v2" ; Pull OS header, IMB func ptr, workspace size, decompression code
+        MOV     a3, #4<<20
+        DebugTX "Decompressing ROM"
+      [ NoARMv5
+        MOV     lr, pc
+        MOV     pc, v2
+      |
+        BLX     v2
+      ]
+        DebugTX "Decompression complete"
+; Before we free the workspace, make sure we zero it
+        MOV     a1, #4<<20
+        MOV     a2, #0
+        MOV     a3, v1
+        BL      memset
+; Flush the workspace from the cache & TLB so we can unmap it
+        MOV     a1, #4<<20
+        MOV     a2, v1, LSR #12
+        ARMop   MMU_ChangingEntries
+; Zero each L1PT entry
+        LDR     a1, =L1PT+(4<<2)
+        MOV     a2, #0
+        MOV     a3, v1, LSR #18
+        BL      memset
+; Pop our registers and we're done
+        Pull    "v1-v2,v5-v7"
+        DebugTX "ROM decompression workspace freed"
+27
+; Now that the ROM is decompressed we need to change the ROM page mapping to
+; read-only. The easiest way to do this is to make another call to Init_MapIn.
+; But before we can do that we need to work out if the HAL+OS are contiguous in
+; physical space. To do this we can just check if the L1PT entry for the OS is a
+; section mapping.
+        LDR     a1, =L1PT+(ROM>>18)
+        LDR     a1, [a1]
+        ASSERT  L1_Section = 2
+        ASSERT  L1_Page = 1
+        TST     a1, #2
+; Section mapped, get address from L1PT
+        MOVNE   a1, a1, LSR #20
+        MOVNE   a1, a1, LSL #20
+        MOVNE   a2, #ROM
+        MOVNE   a4, #OSROM_ImageSize*1024
+        BNE     %FT29
+; Page/large page mapped, get address from L2PT
+        LDR     a2, =RISCOS_Header
+        LDR     a1, =L2PT
+        LDR     a1, [a1, a2, LSR #10]
+        LDR     a4, [a2, #OSHdr_ImageSize]
+        MOV     a1, a1, LSR #12
+        MOV     a1, a1, LSL #12
+29
+        Push    "a2,a4"
+        MOV     a3, #(AP_ROM * L2X_APMult) + L2_C + L2_B
+        BL      Init_MapIn
+; Flush & invalidate cache/TLB to ensure everything respects the new page access
+; Putting a flush here also means the decompression code doesn't have to worry
+; about IMB'ing the decompressed ROM
+        Pull    "a1,a2"
+        MOV     a2, a2, LSR #12
+        ARMop   MMU_ChangingEntries
+        DebugTX "ROM access changed to read-only"
+30
 ; Allocate the CAM
         LDR     a3, [v8, #SoftCamMapSize]
         ORR     a2, v4, #AP_None * L2X_APMult
@@ -1350,7 +1484,7 @@ Init_ClaimPhysicalPage
 ; On entry:
 ;    a1 = logical address
 ;    a2 = access permissions (see Init_MapIn)
-;    a3 = length
+;    a3 = length (4K multiple)
 ;    v1 -> current entry in PhysRamTable
 ;    v2 = next physical address
 ;    v3 -> L1PT
@@ -1365,9 +1499,9 @@ Init_MapInRAM ROUT
         MOV     v5, a3                          ; v5 = amount of memory required
         MOV     v6, a1                          ; v6 = logical address
         MOV     v7, a2                          ; v7 = access permissions
-10      LDMIA   v1, {ip, v4}                    ; ip = addr of bank, v4 = len
-        SUB     ip, v2, ip                      ; ip = amount of bank used
-        SUBS    v4, v4, ip                      ; v4 = amount of bank left
+10      LDMIA   v1, {v4, ip}                    ; v4 = addr of bank, ip = len
+        SUB     v4, v2, v4                      ; v4 = amount of bank used
+        SUBS    v4, ip, v4                      ; v4 = amount of bank left
         LDREQ   v2, [v1, #8]!                   ; move to next bank if 0 left
         BEQ     %BT10
 
@@ -1403,7 +1537,7 @@ Init_MapInRAM ROUT
 ;    a3 = access permissions+C+B bits (bits 11-2 of an L2 extended small page)
 ;           (also set bit 31 to indicate that P bit in L1PT should
 ;            be set)
-;    a4 = area size
+;    a4 = area size (4K multiple)
 ;    v1 -> current entry in PhysRamTable
 ;    v2 = last used physical address
 ;    v3 -> L1PT (or 0 if MMU on)
@@ -1757,14 +1891,6 @@ Init_PageTablesChanged
         MOV     pc, a3
 
 
-HAL_Write0
-        Push    "v1, lr"
-        MOV     v1, a1
-        LDRB    a1, [v1], #1
-        TEQ     a1, #0
-
-
-
 
 
 ;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -2114,13 +2240,33 @@ RISCOS_AddDevice
         B       HardwareDeviceAdd_Common
 
 ; uint32_t RISCOS_LogToPhys(const void *log)
-RISCOS_LogToPhys
+RISCOS_LogToPhys ROUT
         Push    "r4,r5,r8,r9,lr"
         MOV     r4, a1
         LDR     r8, =L2PT
         BL      logical_to_physical
         MOVCC   a1, r5
-        MOVCS   a1, #-1
+        BCC     %FT10
+        ; Try checking L1PT for any section mappings (logical_to_physical only
+        ; deals with regular 4K page mappings)
+        ; TODO - Add large page support
+        LDR     r9, =L1PT
+        MOV     r5, r4, LSR #20
+        LDR     a1, [r9, r5, LSL #2]
+        ASSERT  L1_Section = 2
+        EOR     a1, a1, #2
+        TST     a1, #3
+        MOVNE   a1, #-1
+        BNE     %FT10
+        ; Apply offset from bits 0-19 of logical addr
+      [ NoARMT2
+        MOV     a1, a1, LSR #20
+        ORR     a1, a1, r4, LSL #12
+        MOV     a1, a1, ROR #12
+      |
+        BFI     a1, r4, #0, #20
+      ]
+10
         Pull    "r4,r5,r8,r9,pc"
 
 ; kernel_oserror *RISCOS_IICOpV(IICDesc *descs, uint32_t ndesc_and_bus)
@@ -2184,8 +2330,12 @@ HardwareCall
         ADR     v7, NullHALEntry
         TEQ     ip, v7
         BEQ     HardwareBadEntry2
+      [ NoARMv5
         MOV     lr, pc
         MOV     pc, ip
+      |
+        BLX     ip
+      ]
         ADD     sp, sp, #4*4
         Pull    "sb,lr"
         ExitSWIHandler

s/HeapSort

@@ -168,8 +168,12 @@ h5      LDR     r0, [hs_array, hs_j, LSL #2]
         ADD     r14, hs_j, #1
         LDR     r1, [hs_array, r14, LSL #2]
 
+      [ NoARMv5
         MOV     lr, pc                  ; r0, r1 for comparison
         MOV     pc, hs_procadr
+      |
+        BLX     hs_procadr
+      ]
 
         ADDLT   hs_j, hs_j, #1          ; Assumes signed comparison done <<<<<<
 
@@ -177,8 +181,12 @@ h5      LDR     r0, [hs_array, hs_j, LSL #2]
 h6      MOV     r0, hs_K                ; IF K >= K(R(j)) THEN h8
         LDR     r1, [hs_array, hs_j, LSL #2]
 
+      [ NoARMv5
         MOV     lr, pc                  ; r0, r1 for comparison
         MOV     pc, hs_procadr
+      |
+        BLX     hs_procadr
+      ]
 
         LDRLT   r14, [hs_array, hs_j, LSL #2] ; R(i) = R(j)
         STRLT   r14, [hs_array, hs_i, LSL #2]

s/Kernel

@@ -275,13 +275,19 @@ v8      RN      11
         LDR$cond pc, [sb, #-(EntryNo_$rout+1) * 4]
         MEND
 
-; Checks whether a HAL routine exists. If it does, a1 points to it (probably
-; not useful), and Z is clear. lr corrupted.
+; Checks whether a HAL routine exists. If it does, $ptr points to it, and Z is
+; clear. lr corrupted.
         MACRO
-        CheckHAL $rout
+        CheckHAL $rout, $ptr
+      [ "$ptr"=""
         LDR     a1, [sb, #-(EntryNo_$rout+1) * 4]
         ADRL    lr, NullHALEntry
         TEQ     a1, lr
+      |
+        LDR     $ptr, [sb, #-(EntryNo_$rout+1) * 4]
+        ADRL    lr, NullHALEntry
+        TEQ     $ptr, lr
+      ]
         MEND
 
 
@@ -362,27 +368,23 @@ KernelBase
 ;
 ; *****************************************************************************
 
-  [ HAL
-;        ORG     ROM + OSROM_HALSize
-  |
-;        ORG     ROM
-  ]
-
         GBLS    DoMorrisROMHeader
         GBLS    DoTestThings
 DoMorrisROMHeader SETS ""
 DoTestThings      SETS ""
 
   [ HAL
-;        BIN     HAL.L7200.HAL
-
 ; RISC OS image header
 RISCOS_Header
         =       "OSIm"
-        DCD     0
+        DCD     OSHdrFlag_SupportsCompression
         DCD     OSROM_ImageSize*1024 - OSROM_HALSize
         DCD     RISCOS_Entries - RISCOS_Header
         DCD     (RISCOS_Entries_End - RISCOS_Entries) / 4
+        DCD     OSROM_ImageSize*1024 - OSROM_HALSize
+        DCD     0
+        DCD     EndOfKernel - RISCOS_Header
+        ASSERT  (. - RISCOS_Header) = OSHdr_size
 
 RISCOS_Entries
         DCD     RISCOS_InitARM   - RISCOS_Entries
@@ -623,7 +625,7 @@ SWIRelocationZeroPage
 SVC * {PC}-SWIRelocation
 
         Push    "r10-r12"
- [ No26bitCode
+ [ SupportARMT
         MRS     r12, SPSR               ; r12 = saved PSR
         TST     r12, #T32_bit           ; depending on processor state (ARM/Thumb)
         LDREQ   r11, [r14, #-4]         ; extract SWI number to r11
@@ -1083,8 +1085,7 @@ process_callback_chain ROUT
 
 01
         MSR     CPSR_c, #I32_bit + SVC2632      ; ints off while flag updated
-        LDR     r2, =ZeroPage
-        LDR     r2, [r2, #CallBack_Vector]
+        LDR     r2, [r10, #CallBack_Vector]
         TEQ     r2, #0
       [ No26bitCode
       [ FixCallBacks
@@ -1098,25 +1099,15 @@ process_callback_chain ROUT
         Pull   "r0-r6, r10-r12, PC",EQ,^
       ]
 
-        LDMIA   r2, {r10, r11, r12}             ; link, addr, r12
+        LDMIA   r2, {r1, r11, r12}             ; link, addr, r12
         MOV     r0, #HeapReason_Free
-      [ ZeroPage = 0
-        STR     r10, [r0, #CallBack_Vector-HeapReason_Free] ; Keep head valid
-      |
-        LDR     r1, =ZeroPage
-        STR     r10, [r1, #CallBack_Vector] ; Keep head valid
-      ]
+        STR     r1, [r10, #CallBack_Vector] ; Keep head valid
 
         MSR     CPSR_c, #SVC2632                ; enable ints for long bits
 
   [ ChocolateSysHeap
         ASSERT  ChocolateCBBlocks = ChocolateBlockArrays + 0
-      [ ZeroPage = 0
-        MOV     r1,#ChocolateBlockArrays
-        LDR     r1,[r1,#0]
-      |
-        LDR     r1, [r1, #ChocolateBlockArrays]
-      ]
+        LDR     r1, [r10, #ChocolateBlockArrays]
         BL      FreeChocolateBlock
         LDRVS   r1, =SysHeapStart
         SWIVS   XOS_Heap
@@ -1124,9 +1115,12 @@ process_callback_chain ROUT
         LDR     r1, =SysHeapStart
         SWI     XOS_Heap
   ]
-
+      [ NoARMv5
         MOV     lr, pc
         MOV     pc, r11                         ; call im, with given r12
+      |
+        BLX     r11                             ; call im, with given r12
+      ]
 
         B       %BT01                           ; loop
 
@@ -1306,9 +1300,14 @@ VectorUserSWI                   ; Not in a module, so call vec
         Pull    "r9,lr"
  ]
         MRS     r10, CPSR
+      [ NoARMT2
         BIC     lr, lr, #&FF000000      ; Can mangle any/all of punter flags
         AND     r10, r10, #&FF000000
         ORR     lr, lr, r10
+      |
+        MOV     r10, r10, LSR #24
+        BFI     lr, r10, #24, #8        ; Can mangle any/all of punter flags
+      ]
         B       SLVK
 
 ; ....................... default owner of UKSWIV .............................
@@ -1464,10 +1463,16 @@ VecSwiDespatch ROUT
 
   [ No26bitCode
         MRS     r11, CPSR
+      [ NoARMT2
         AND     r14, r14, #&F0000000    ; extract caller's CCs
         BIC     r11, r11, #&F0000000    ; mask out ours
         BIC     r11, r11, #I32_bit      ; enable IRQs
         ORR     r11, r11, r14           ; add in CCs
+      |
+        MOV     r14, r14, LSR #28
+        BIC     r11, r11, #I32_bit      ; enable IRQs
+        BFI     r11, r14, #28, #4       ; add in caller's CCs
+      ]
         MSR     CPSR_cf, r11            ; and set it all up
   |
         ORR     r14, lr, #SVC_mode
@@ -1496,10 +1501,16 @@ NoIrqVecSwiDespatch ROUT
         MOV     r10, r11                ; SWI number from R11->R10
   [ No26bitCode
         MRS     r11, CPSR
+      [ NoARMT2
         AND     r14, r14, #&F0000000    ; extract caller's CCs
         BIC     r11, r11, #&F0000000    ; mask out ours
         ORR     r11, r11, #I32_bit      ; disable IRQs
         ORR     r11, r11, r14           ; add in CCs
+      |
+        MOV     r14, r14, LSR #28
+        BIC     r11, r11, #I32_bit      ; enable IRQs
+        BFI     r11, r14, #28, #4       ; add in caller's CCs
+      ]
         MSR     CPSR_cf, r11            ; and set it all up
   |
         ORR     r14, lr, #SVC_mode+I_bit ; Disable IRQ

s/Middle

@@ -24,9 +24,15 @@ ReadLineSWI
         Pull    "r4,lr"
         ; Pass back NZCV bits
         MRS     r11, CPSR
+      [ NoARMT2
         BIC     lr,  lr,  #N_bit+Z_bit+C_bit+V_bit
         AND     r11, r11, #N_bit+Z_bit+C_bit+V_bit
         ORR     lr, lr, r11
+      |
+        ASSERT (N_bit+Z_bit+C_bit+V_bit)=&F0000000
+        MOV     r11, r11, LSR #28
+        BFI     lr, r11, #28, #4
+      ]
         B       SLVK
 
 ReadLine32SWI
@@ -1016,10 +1022,16 @@ DoAnUpCall ROUT
         Push    lr                  ; better have one of these to pull later !
  [ No26bitCode
         MRS     r12, CPSR
+      [ NoARMT2
         BIC     r12, r12, #&F0000000
         BIC     r12, r12, #I32_bit:OR:F32_bit
         AND     r10, lr, #&F0000000 ; copy user flags (I bit clear)
         ORR     r10, r10, r12
+      |
+        MOV     lr, lr, LSR #28
+        BIC     r10, r12, #I32_bit:OR:F32_bit
+        BFI     r10, lr, #28, #4 ; copy user flags (I bit clear)
+      ]
         MSR     CPSR_cf, r10        ; ints on, stay in SVC mode, flags in psr
  |
         AND     r10, lr, #&F0000000 ; copy user flags (I_bit clear)
@@ -1027,15 +1039,23 @@ DoAnUpCall ROUT
  ]
         MOV     r10, #UpCallV
         BL      CallVector
+ [ NoARMT2
         Pull    lr
         BIC     lr, lr, #&F0000000
- [ No26bitCode
+   [ No26bitCode
         MRS     R10, CPSR
         MOV     R10, R10, LSR #(32-4)
- |
+   |
         MOV     R10, PC, LSR #(32-4)
- ]
+   ]
         ORR     lr, lr, R10, LSL #(32-4)
+ |
+        ASSERT  No26bitCode
+        MRS     R10, CPSR
+        Pull    lr
+        MOV     R10, R10, LSR #28
+        BFI     lr, R10, #28, #4
+ ]
         ExitSWIHandler
 
 ; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -2122,6 +2142,8 @@ RSI_DebugRX
 ; Current tags:
 ;
 ; 0     ROM build date, stored as 5-byte time (length = 5)
+; 1     Compressed ROM softload hint (length = 8). First word is negative
+;       checksum of uncompressed image, second word is OS header offset.
 ;
 
 ExtendedROMFooter_Find  ROUT

s/ModHand

@@ -365,8 +365,12 @@ InitialiseROMModule Entry "r0-r12"
         LDR     r6, [r11, #ROMModule_BaseAddress]
         LDR     r7, [r12, #ROMModule_PoduleNumber]
         ADRL    r1, crstring
+      [ No26bitCode
+        ADR     lr, %FT20
+      |
         MOV     lr, pc                                  ; ADRS lr, %FT10
         ADD     lr, lr, #%FT20-%FT10                    ; ADRS lr, %FT20
+      ]
 10
         Push    "r0-r7,r9,lr"
         LDR     r1, [r11, #ROMModule_Size]

s/NewIRQs

@@ -887,8 +887,12 @@ SubInterrupt_Despatch
         Push    "r0,r1,r12,lr"
         MOV     r0, r3
         MOV     r12, r3
+      [ NoARMv5
         MOV     lr, pc
         MOV     pc, r2
+      |
+        BLX     r2
+      ]
         TEQ     r0, #0
         Pull    "r0,r1,r12,lr"
         BEQ     %BT01

s/NewReset

@@ -41,15 +41,6 @@ CMOSLimit       * &F0
 KbdScanActive   # 1
                 # 2
 KbdFlags        # 4
-
-KbdFlag_Ctrl    * 1:SHL:0
-KbdFlag_Shift   * 1:SHL:1
-KbdFlag_R       * 1:SHL:4
-KbdFlag_T       * 1:SHL:5
-KbdFlag_Delete  * 1:SHL:6
-KbdFlag_Copy    * 1:SHL:7
-KbdFlag_Present * 1:SHL:30
-KbdFlag_Done    * 1:SHL:31
  |
 CTRL_Down_Flag  # 1
 SHIFT_Down_Flag # 1
@@ -245,6 +236,7 @@ CmosScreenWillDo
 CONT_Break
         AddressHAL
         MOV     a1, #1
+        LDR     a2, =L1PT
         CallHAL HAL_Reset
   ]
 

s/PMF/key

@@ -718,6 +718,7 @@ PerformReset
         |
         AddressHAL
         MOV     a1, #0
+        LDR     a2, =L1PT
         CallHAL HAL_Reset
         ]
 15

s/TickEvents

@@ -157,8 +157,12 @@ ProcessTickEventChain  ROUT
         LDMIA   r1, {r2, r10, r11, r12}         ; load next ptr, redo state,
                                                 ;     address and R12val
         STR     r2, [r3]                        ; de-link from chain
+      [ NoARMv5
         MOV     lr, pc
         MOV     pc, r11                         ; call event handler
+      |
+        BLX     r11                             ; call event handler
+      ]
 
         LDR     r0, [r1, #TickNodeRedo]
         CMP     r0, #0                          ; CallEvery?

s/vdu/vdudriver

@@ -180,6 +180,9 @@ VduInit ROUT
         mjsAddressHAL
         MOV     r4, r12                       ; temp WsPtr
         mjsCallHAL HAL_Video_Features
+        ; Set bit 31 of features if HAL_Video_Render supported
+        CheckHAL HAL_Video_Render, r1
+        ORREQ   r0, r0, #1:SHL:31
         STR     r0, [r4, #HALVideoFeatures]
  [ :LNOT:UseGraphicsV
         mjsCallHAL HAL_Video_PixelFormats

s/vdu/vdugrafb

@@ -1072,6 +1072,7 @@ GenSegParmB10                           ;Line does not cross X axis, so..
 
 DoubleMulDivSquareRoot ROUT
         Push    "R8-R11,R14"
+    [ NoARMM
         MOV     R2, R3, LSR #16                 ; R2 = ah
         EOR     R7, R3, R2, LSL #16             ; R7 = al
         MOV     R9, R8, LSR #16                 ; R9 = bh
@@ -1084,10 +1085,19 @@ DoubleMulDivSquareRoot ROUT
 
         ADDS    R3, R3, R14, LSL #16            ; R3 = lower 32 bits of a.b
         ADC     R8, R8, R14, LSR #16            ; R8 = upper 32 bits of a.b
-
+    |
+        ; Use UMULL
+      [ NoARMv6
+        ; Rn can't be RdLo/RdHi in ARMv5 and below
+        MOV     R2, R3
+        UMULL   R3, R8, R2, R8
+      |
+        UMULL   R3, R8, R3, R8
+      ]
+    ]
 ; now do divide of a.b by c
 ; we know that a.b < 2^61, so no problem with top bit of a.b
-
+      [ NoARMv5
         MOV     R9, R11                         ; R9 = low 32 bits of shifted c
         MOV     R10, #0                         ; R10 = hi 32 bits of shifted c
 10
@@ -1096,6 +1106,22 @@ DoubleMulDivSquareRoot ROUT
         CMP     R9, R3                          ; compare R9,R10 with a.b
         SBCS    R14, R10, R8
         BCC     %BT10                           ; if lower then loop
+      |
+        CLZ     R9, R11
+        TEQ     R8, #0
+        CLZNE   R2, R8
+        CLZEQ   R2, R3
+        ADDNE   R9, R9, #32
+        SUBS    R2, R9, R2                      ; R2 = how many bits to shift R11 left
+        MOVLT   R3, #0
+        Pull    "R8-R11,PC",LT
+
+        MOV     R9, R11, LSL R2
+        SUBS    R2, R2, #32
+        MOVGE   R10, R11, LSL R2
+        RSBLT   R2, R2, #0
+        MOVLT   R10, R11, LSR R2
+      ]
 
         MOV     R7, #0                          ; zero result
 20

s/vdu/vdugrafv

@@ -25,40 +25,32 @@
 
  [ UseGraphicsV
 
-        ASSERT  GraphicsV_VSync = 1
-        ASSERT  GraphicsV_SetMode = 2
-        ASSERT  GraphicsV_SetInterlace = 3
-        ASSERT  GraphicsV_SetBlank = 4
-        ASSERT  GraphicsV_UpdatePointer = 5
-        ASSERT  GraphicsV_SetDMAAddress = 6
-        ASSERT  GraphicsV_VetMode = 7
-        ASSERT  GraphicsV_DisplayFeatures = 8
-        ASSERT  GraphicsV_WritePaletteEntry = 10
-        ASSERT  GraphicsV_WritePaletteEntries = 11
-        ASSERT  GraphicsV_Render = 13
-        ASSERT  GraphicsV_IICOp = 14
-
+        MACRO
+        GVEntry $name
+        ASSERT  . - MOSGraphicsV_Table = GraphicsV_$name * 4
+        B       GV_$name
+        MEND
 
 MOSGraphicsV ROUT
         CMP     r4, #(MOSGraphicsV_TableEnd - MOSGraphicsV_Table) / 4
         ADDLS   pc, pc, r4, LSL #2
-MOSGraphicsV_Table
         MOV     pc, lr                  ; reason code not known, so pass it on
+MOSGraphicsV_Table
         MOV     pc, lr                  ; 0
-        B       GV_VSync                ; 1
-        B       GV_SetMode              ; 2
-        B       GV_SetInterlace         ; 3
-        B       GV_SetBlank             ; 4
-        B       GV_UpdatePointer        ; 5
-        B       GV_SetAddress           ; 6
-        B       GV_VetMode              ; 7
-        B       GV_Features             ; 8
+        GVEntry VSync                   ; 1
+        GVEntry SetMode                 ; 2
+        GVEntry SetInterlace            ; 3
+        GVEntry SetBlank                ; 4
+        GVEntry UpdatePointer           ; 5
+        GVEntry SetDMAAddress           ; 6
+        GVEntry VetMode                 ; 7
+        GVEntry DisplayFeatures         ; 8
         MOV     pc, lr                  ; 9
-        B       GV_WritePaletteEntry    ; 10
-        B       GV_WritePaletteEntries  ; 11
-        MOV     pc, lr                  ; 12
-        B       GV_Render               ; 13
-        B       GV_IICOp                ; 14
+        GVEntry WritePaletteEntry       ; 10
+        GVEntry WritePaletteEntries     ; 11
+        GVEntry ReadPaletteEntry        ; 12
+        GVEntry Render                  ; 13
+        GVEntry IICOp                   ; 14
 MOSGraphicsV_TableEnd
 
 GV_VSync        ROUT
@@ -118,7 +110,7 @@ GV_UpdatePointer
         mjsCallHAL HAL_Video_UpdatePointer
         Pull    "r0-r3, r9, pc"
 
-GV_SetAddress
+GV_SetDMAAddress
         Push    "r0-r3, r9, lr"
         mjsAddressHAL WsPtr
         MOV     r4, #0
@@ -132,7 +124,7 @@ GV_VetMode
         mjsCallHAL HAL_Video_VetMode
         Pull    "r1-r3, r9, pc"
 
-GV_Features
+GV_DisplayFeatures
         Push    "r0,r1,r3, r9, lr"
         mjsAddressHAL WsPtr
         MOV     r4, #0
@@ -158,10 +150,25 @@ GV_WritePaletteEntries
         mjsCallHAL HAL_Video_WritePaletteEntries
         Pull    "r0-r3, r9, pc"
 
+GV_ReadPaletteEntry
+        Push    "r0,r2-r3, r9, lr"
+        mjsAddressHAL WsPtr
+        CheckHAL HAL_Video_ReadPaletteEntry, r3
+        Pull    "r0,r2-r3, r9, pc", EQ
+        MOV     r4, #0
+      [ NoARMv5
+        MOV     lr, pc
+        MOV     pc, r3
+      |
+        BLX     r3
+      ]
+        MOV     r1,r0
+        Pull    "r0,r2-r3, r9, pc"
+
 GV_Render
         VDWS    WsPtr
         LDR     WsPtr, [WsPtr, #HALVideoFeatures]
-        TST     WsPtr, #1:SHL:4
+        TST     WsPtr, #1:SHL:31 ; Fake flag set during VduInit
         MOVEQ   pc, lr
         Push    "r0-r3, r9, lr"
         ORR     r0, r0, #1:SHL:31