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Commit 534344d9 authored by Robert Sprowson's avatar Robert Sprowson
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Move Cache_Lx_ info inside SkippedTable region of workspace 

ClearPhysRAM runs after ARM_Analyse and would wipe out the RAM copies of the various CP15 registers defining which caches are present, leading to the IMB_Full and IMB_Range operations skipping most of their job.
Space freed below DebuggerSpace by moving the RAM copies of the processor vectors up a bit.
Tested with a nobbled HAL which doesn't do the RAM clear, inspecting the workspace in a debugger to see it's preserved (only affects VSMAv6 models).

Version 5.35, 4.79.2.214. Tagged as 'Kernel-5_35-4_79_2_214'
parent 7b6ae685
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Showing with 30 additions and 32 deletions
VersionASM
View file @ 534344d9
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.213"
Module_Date SETS "28 Mar 2014"
Module_ApplicationDate SETS "28-Mar-14"
Module_MinorVersion SETS "4.79.2.214"
Module_Date SETS "29 Mar 2014"
Module_ApplicationDate SETS "29-Mar-14"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.213)"
Module_HelpVersion SETS "5.35 (28 Mar 2014) 4.79.2.213"
Module_FullVersion SETS "5.35 (4.79.2.214)"
Module_HelpVersion SETS "5.35 (29 Mar 2014) 4.79.2.214"
END
VersionNum
View file @ 534344d9
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.213
#define Module_Date_CMHG 28 Mar 2014
#define Module_MinorVersion_CMHG 4.79.2.214
#define Module_Date_CMHG 29 Mar 2014
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.213"
#define Module_Date "28 Mar 2014"
#define Module_MinorVersion "4.79.2.214"
#define Module_Date "29 Mar 2014"
#define Module_ApplicationDate "28-Mar-14"
#define Module_ApplicationDate "29-Mar-14"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.213)"
#define Module_HelpVersion "5.35 (28 Mar 2014) 4.79.2.213"
#define Module_FullVersion "5.35 (4.79.2.214)"
#define Module_HelpVersion "5.35 (29 Mar 2014) 4.79.2.214"
#define Module_LibraryVersionInfo "5:35"
hdr/KernelWS
View file @ 534344d9
......@@ -1235,6 +1235,9 @@ Proc_MMU_ChangingUncachedEntry # 4
Proc_MMU_ChangingEntries # 4
Proc_MMU_ChangingUncachedEntries # 4
Cache_Lx_Info # 4 ; Cache level ID register
Cache_Lx_DTable # 4*7 ; Data/unified cache layout for all 7 levels
Cache_Lx_ITable # 4*7 ; Instruction cache layout for all 7 levels
]
......@@ -1245,23 +1248,7 @@ IOAllocLimit # 4 ; current lowest allowed I/O space (DA c
SkippedTablesEnd # 0
ProcVec_Start # 0 ; Start of processor vector table
ProcVec_Branch0 # 4 ; Branch through zero
ProcVec_UndInst # 4 ; Undefined instruction vector
ProcVec_SWI # 4 ; SWI vector
ProcVec_PrefAb # 4 ; Prefetch abort vector
ProcVec_DataAb # 4 ; Data abort vector
ProcVec_AddrEx # 4 ; not used (was Address exception vector on 26-bit-only ARMs)
ProcVec_IRQ # 4 ; IRQ vector
ProcVec_End # 0
ProcVecPreVeneersSize * 4*4 ; Space for preveneers for loading handler addresses from 0 page.
ProcVecPreVeneers # ProcVecPreVeneersSize
IRQMax # 4 ; from HAL_IRQMax
[ :DEF: ShowWS
[ :DEF: ShowWS
! 0, "Free space before DebuggerSpace = ":CC::STR:(&300-@)
]
......@@ -1296,14 +1283,25 @@ FreePoolDANode # DANode_NodeSize ; Area node for free pool
SysHeapDANode # DANode_NodeSize ; Area node for system heap
CDASemaphore # 4 ; Semaphore for OS_ChangeDynamicArea - non-zero => routine threaded
MMUControlSoftCopy # 4 ; Soft copy of ARM control register
IRQMax # 4 ; from HAL_IRQMax
[ HAL
DeviceCount # 4 ; size of our table of devices in the system heap
DeviceTable # 4 ; pointer to table
Cache_Lx_Info # 4 ; Cache level ID register
Cache_Lx_DTable # 4*7 ; Data/unified cache layout for all 7 levels
Cache_Lx_ITable # 4*7 ; Instruction cache layout for all 7 levels
]
ProcVec_Start # 0 ; Start of processor vector table
ProcVec_Branch0 # 4 ; Branch through zero
ProcVec_UndInst # 4 ; Undefined instruction vector
ProcVec_SWI # 4 ; SWI vector
ProcVec_PrefAb # 4 ; Prefetch abort vector
ProcVec_DataAb # 4 ; Data abort vector
ProcVec_AddrEx # 4 ; not used (was Address exception vector on 26-bit-only ARMs)
ProcVec_IRQ # 4 ; IRQ vector
ProcVec_End # 0
ProcVecPreVeneersSize * 4*4 ; Space for preveneers for loading handler addresses from 0 page.
ProcVecPreVeneers # ProcVecPreVeneersSize
AplWorkSize * AppSpaceDANode + DANode_Size
[ :LNOT: LongCommandLines
......
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