Switch default NCB cache policy to MergingIdempotent (i.e. Normal, non-cacheable)

Detail:
  s/ARMops - Change VMSAv6 cache policy mapping so that default NCB policy maps to Normal, non-cacheable memory rather than Device memory. This allows unaligned accesses to work, and also delivers some major performance improvements for some activities (write performance seems about 2x better than Device)
  Docs/HAL/ARMop_API - Wrap the new barrier ARMop description text to match the rest of the file
Admin:
  Tested on ARM11, Cortex-A7, -A8, -A9
  Note - relaxed memory consistency rules for Normal vs. Device mean that now more than ever, developers authoring device drivers for ARMv6+ need to be careful to use memory barriers in all the right places (preferably the new ARMop barriers exposed by OS_MMUControl 2 to ensure compatibility with all machines)


Version 5.35, 4.79.2.280. Tagged as 'Kernel-5_35-4_79_2_280'

Docs/HAL/ARMop_API

@@ -282,7 +282,8 @@ This call is roughly equivalent to the ARMv7 "DSB SY" instruction:
 
  * Writebuffers are drained
  * Full read/write barrier - no data load/store will cross the instruction
- * Instructions following the barrier will only begin execution once the barrier is passed - but any prefetched instructions are not flushed
+ * Instructions following the barrier will only begin execution once the
+   barrier is passed - but any prefetched instructions are not flushed
 
    entry: -
    exit:  -
@@ -294,7 +295,8 @@ This call is roughly equivalent to the ARMv7 "DSB ST" instruction:
 
  * Writebuffers are drained
  * Write barrier - reads may cross the instruction
- * Instructions following the barrier will only begin execution once the barrier is passed - but any prefetched instructions are not flushed
+ * Instructions following the barrier will only begin execution once the
+   barrier is passed - but any prefetched instructions are not flushed
 
    entry: -
    exit:  -
@@ -302,10 +304,14 @@ This call is roughly equivalent to the ARMv7 "DSB ST" instruction:
 
 -- DSB_Read
 
-There is no direct equivalent to this in ARMv7 (barriers are either W or RW). However it's useful to define a read barrier, as (e.g.) on Cortex-A9 a RW barrier would require draining the write buffer of the external PL310 cache, while a R barrier can simply be an ordinary DSB instruction.
+There is no direct equivalent to this in ARMv7 (barriers are either W or RW).
+However it's useful to define a read barrier, as (e.g.) on Cortex-A9 a RW
+barrier would require draining the write buffer of the external PL310 cache,
+while a R barrier can simply be an ordinary DSB instruction.
 
  * Read barrier - writes may cross the instruction
- * Instructions following the barrier will only begin execution once the barrier is passed - but any prefetched instructions are not flushed
+ * Instructions following the barrier will only begin execution once the
+   barrier is passed - but any prefetched instructions are not flushed
 
    entry: -
    exit:  -
@@ -317,12 +323,19 @@ This call is roughly equivalent to the ARMv7 "DMB SY" instruction:
 
  * Ensures in-order operation of data load/store instructions
  * Does not stall instruction execution
- * Does not guarantee that any preceeding memory operations complete in a timely manner (or at all)
+ * Does not guarantee that any preceeding memory operations complete in a
+   timely manner (or at all)
 
    entry: -
    exit:  -
 
-Although this call doesn't guarantee that any memory operation completes, it's usually all that's required when interacting with hardware devices which use memory-mapped IO. E.g. fill a buffer with data, issue a DMB, then write to a hardware register to start some external DMA. The writes to the buffer will have been guaranteed to complete by the time the write to the hardware register completes.
+Although this call doesn't guarantee that any memory operation completes, it's
+usually all that's required when interacting with hardware devices which use
+memory-mapped IO. E.g. fill a buffer with data, issue a DMB, then write to a
+hardware register to start some external DMA. The writes to the buffer will
+have been guaranteed to complete by the time the write to the hardware register
+completes.
+
 
 -- DMB_Write
 
@@ -330,26 +343,40 @@ This call is roughly equivalent to the ARMv7 "DMB ST" instruction:
 
  * Ensures in-order operation of data store instructions
  * Does not stall instruction execution
- * Does not guarantee that any preceeding memory operations complete in a timely manner (or at all)
+ * Does not guarantee that any preceeding memory operations complete in a
+   timely manner (or at all)
 
    entry: -
    exit:  -
 
-Although this call doesn't guarantee that any memory operation completes, it's usually all that's required when interacting with hardware devices which use memory-mapped IO. E.g. fill a buffer with data, issue a DMB, then write to a hardware register to start some external DMA. The writes to the buffer will have been guaranteed to complete by the time the write to the hardware register completes.
+Although this call doesn't guarantee that any memory operation completes, it's
+usually all that's required when interacting with hardware devices which use
+memory-mapped IO. E.g. fill a buffer with data, issue a DMB, then write to a
+hardware register to start some external DMA. The writes to the buffer will
+have been guaranteed to complete by the time the write to the hardware register
+completes.
 
 
 -- DMB_Read
 
-There is no direct equivalent to this in ARMv7 (barriers are either W or RW). However it's useful to define a read barrier, as (e.g.) on Cortex-A9 a RW barrier would require draining the write buffer of the external PL310 cache, while a R barrier can simply be an ordinary DMB instruction.
+There is no direct equivalent to this in ARMv7 (barriers are either W or RW).
+However it's useful to define a read barrier, as (e.g.) on Cortex-A9 a RW
+barrier would require draining the write buffer of the external PL310 cache,
+while a R barrier can simply be an ordinary DMB instruction.
 
  * Ensures in-order operation of data load instructions
  * Does not stall instruction execution
- * Does not guarantee that any preceeding memory operations complete in a timely manner (or at all)
+ * Does not guarantee that any preceeding memory operations complete in a
+   timely manner (or at all)
 
    entry: -
    exit:  -
 
-Although this call doesn't guarantee that any memory operation completes, it's usually all that's required when interacting with hardware devices which use memory-mapped IO. E.g. after reading a hardware register to detect that a DMA write to RAM has completed, issue a read barrier to ensure that any reads from the data buffer see the final data.
+Although this call doesn't guarantee that any memory operation completes, it's
+usually all that's required when interacting with hardware devices which use
+memory-mapped IO. E.g. after reading a hardware register to detect that a DMA
+write to RAM has completed, issue a read barrier to ensure that any reads from
+the data buffer see the final data.
 
 
 TLB ARMops

VersionASM

@@ -13,11 +13,11 @@
                         GBLS    Module_ComponentPath
 Module_MajorVersion     SETS    "5.35"
 Module_Version          SETA    535
-Module_MinorVersion     SETS    "4.79.2.279"
-Module_Date             SETS    "14 Aug 2015"
-Module_ApplicationDate  SETS    "14-Aug-15"
+Module_MinorVersion     SETS    "4.79.2.280"
+Module_Date             SETS    "15 Aug 2015"
+Module_ApplicationDate  SETS    "15-Aug-15"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.35 (4.79.2.279)"
-Module_HelpVersion      SETS    "5.35 (14 Aug 2015) 4.79.2.279"
+Module_FullVersion      SETS    "5.35 (4.79.2.280)"
+Module_HelpVersion      SETS    "5.35 (15 Aug 2015) 4.79.2.280"
                         END

VersionNum

@@ -5,19 +5,19 @@
  *
  */
 #define Module_MajorVersion_CMHG        5.35
-#define Module_MinorVersion_CMHG        4.79.2.279
-#define Module_Date_CMHG                14 Aug 2015
+#define Module_MinorVersion_CMHG        4.79.2.280
+#define Module_Date_CMHG                15 Aug 2015
 
 #define Module_MajorVersion             "5.35"
 #define Module_Version                  535
-#define Module_MinorVersion             "4.79.2.279"
-#define Module_Date                     "14 Aug 2015"
+#define Module_MinorVersion             "4.79.2.280"
+#define Module_Date                     "15 Aug 2015"
 
-#define Module_ApplicationDate          "14-Aug-15"
+#define Module_ApplicationDate          "15-Aug-15"
 
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.35 (4.79.2.279)"
-#define Module_HelpVersion              "5.35 (14 Aug 2015) 4.79.2.279"
+#define Module_FullVersion              "5.35 (4.79.2.280)"
+#define Module_HelpVersion              "5.35 (15 Aug 2015) 4.79.2.280"
 #define Module_LibraryVersionInfo       "5:35"

s/ARMops

@@ -3194,7 +3194,7 @@ L2_Dev_nS   * 2:SHL:L2_TEXShift             ; Device, non-shareable
 ; than needed if the hardware downgrades some areas to NC.
 
 XCBTableVMSAv6                                     ; C+B        CNB   NCB         NCNB
-        = L2_Nrm_WBRA, L2_SO_S, L2_Dev_S,  L2_SO_S ;        Default
+        = L2_Nrm_WBRA, L2_SO_S, L2_Nrm_NC, L2_SO_S ;        Default
         = L2_Nrm_WT,   L2_SO_S, L2_Dev_S,  L2_SO_S ; WT,         WT, Non-merging, X
         = L2_Nrm_WBRA, L2_SO_S, L2_Dev_S,  L2_SO_S ; WB/RA,      WB, Merging,     X
         = L2_Nrm_WBWA, L2_SO_S, L2_Nrm_NC, L2_SO_S ; WB/WA,      X,  Idempotent,  X
@@ -3205,7 +3205,7 @@ XCBTableVMSAv6                                     ; C+B        CNB   NCB
         ; This second set of entries deals with when pages are made
         ; temporarily uncacheable - we need to change the cacheability without
         ; changing the memory type.
-        = L2_Nrm_NC,   L2_SO_S, L2_Dev_S,  L2_SO_S ;        Default
+        = L2_Nrm_NC,   L2_SO_S, L2_Nrm_NC, L2_SO_S ;        Default
         = L2_Nrm_NC,   L2_SO_S, L2_Dev_S,  L2_SO_S ; WT,         WT, Non-merging, X
         = L2_Nrm_NC,   L2_SO_S, L2_Dev_S,  L2_SO_S ; WB/RA,      WB, Merging,     X
         = L2_Nrm_NC,   L2_SO_S, L2_Nrm_NC, L2_SO_S ; WB/WA,      X,  Idempotent,  X