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Commit 3758c6a1 authored by Robert Sprowson's avatar Robert Sprowson
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Retire single use of DebugROMErrors 

hdr/Options: Switch removed
s/Modhand: Switch removed, now considered equivalent to DebugROMInit. DebugROMInit changed so that the callback ordering is as expected, batched up until "callbacks" is hit after Service_PostInit.
PMF/osbyte: Redundant RISC OS 2.01 code deleted

Version 5.35, 4.79.2.184. Tagged as 'Kernel-5_35-4_79_2_184'
parent 21dd9813
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Showing with 33 additions and 33 deletions
VersionASM
View file @ 3758c6a1
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.183"
Module_Date SETS "27 Jan 2013"
Module_ApplicationDate SETS "27-Jan-13"
Module_MinorVersion SETS "4.79.2.184"
Module_Date SETS "24 Mar 2013"
Module_ApplicationDate SETS "24-Mar-13"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.183)"
Module_HelpVersion SETS "5.35 (27 Jan 2013) 4.79.2.183"
Module_FullVersion SETS "5.35 (4.79.2.184)"
Module_HelpVersion SETS "5.35 (24 Mar 2013) 4.79.2.184"
END
VersionNum
View file @ 3758c6a1
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.183
#define Module_Date_CMHG 27 Jan 2013
#define Module_MinorVersion_CMHG 4.79.2.184
#define Module_Date_CMHG 24 Mar 2013
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.183"
#define Module_Date "27 Jan 2013"
#define Module_MinorVersion "4.79.2.184"
#define Module_Date "24 Mar 2013"
#define Module_ApplicationDate "27-Jan-13"
#define Module_ApplicationDate "24-Mar-13"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.183)"
#define Module_HelpVersion "5.35 (27 Jan 2013) 4.79.2.183"
#define Module_FullVersion "5.35 (4.79.2.184)"
#define Module_HelpVersion "5.35 (24 Mar 2013) 4.79.2.184"
#define Module_LibraryVersionInfo "5:35"
hdr/Options
View file @ 3758c6a1
......@@ -274,16 +274,13 @@ RMTidyDoesNowt SETL {TRUE} ; should really be "machine has
RogerEXEY SETL {FALSE} ; Marketing don't like it!
GBLL DebugROMInit
GBLL DebugROMErrors
GBLL DebugHALTX
[ FreezeDevRel
DebugROMInit SETL {FALSE}
DebugROMErrors SETL {FALSE}
DebugHALTX SETL {FALSE}
|
DebugROMInit SETL (Version :AND: 1) = 1 ; Yes for odd numbered development
DebugROMErrors SETL (Version :AND: 1) = 1 ; Yes for odd numbered development
DebugHALTX SETL (Version :AND: 1) = 1 ; Yes for odd numbered development
]
......@@ -302,7 +299,7 @@ DebugHeaps SETL {FALSE} ; (may slow things down unaccept
GBLL DebugCDA2 ; ChangeDynamicArea and related options
DebugCDA2 SETL {FALSE}
[ DebugHeaps :LOR: DebugROMInit :LOR: DebugROMPostInit :LOR: DebugROMErrors :LOR: DebugCDA2
[ DebugHeaps :LOR: DebugROMInit :LOR: DebugROMPostInit :LOR: DebugCDA2
! 0, "*** WARNING *** Debugging assembled in"
]
......
s/ModHand
View file @ 3758c6a1
......@@ -300,28 +300,36 @@ ModuleInit Entry "r0-r12" ; call here on system st
; not an extension ROM, so initialise the newest version (r11) of this module
70
[ DebugROMInit
[ DebugROMInit ; print names in ROM module init for debugging
SWI XOS_WriteS
= "init mod ",0
ALIGN
LDR r0, [r11, #ROMModule_Name]
SWI XOS_Write0
SWI XOS_NewLine ; VDU driver processes callbacks on LF
|
! 0, "Temporarily doing callbacks like the VDU driver would"
LDR R0, =ZeroPage
LDRB R14, [R0, #CallBack_Flag]
TST R14, #CBack_VectorReq
BLNE process_callback_chain ; Process callbacks here too then
]
BL InitialiseROMModule
[ DebugROMErrors ; print errors in ROM module init for debugging
BVC %FT80
[ DebugROMInit
BVC %FT79
SWI XOS_WriteS
= " error: ",0
= " => error: ",0
ALIGN
ADDVC r0, r0, #4
SWIVC XOS_Write0
SWIVC XOS_NewLine
79
WritePSRc SVC_mode+I_bit,r14 ; this bit of gymnastis ensures that requested
LDR r0, =ZeroPage ; callbacks don't fire when doing the page scroll check
LDRB r1, [r0, #CallBack_Flag] ; in the VDU driver because of the new line. Otherwise,
BIC r14, r1, #CBack_VectorReq ; callbacks scheduled during ROM init are ordered
STRB r14, [r0, #CallBack_Flag] ; differently for DebugROMInit {TRUE} than {FALSE}
SWI XOS_NewLine ; enables interrupts itself
WritePSRc SVC_mode+I_bit,r14
TST r1, #CBack_VectorReq
LDRNEB r1, [r0, #CallBack_Flag]
ORRNE r1, r1, #CBack_VectorReq ; re-insert that request
STRNEB r1, [r0, #CallBack_Flag]
WritePSRc SVC_mode,r14
]
80
LDR r12, [r12, #ROMModule_Link]
......
s/PMF/osbyte
View file @ 3758c6a1
......@@ -855,7 +855,6 @@ Osbyte7C7D
LDMIA R12, {R12, PC}
Exit7D
TEQ R12, #1
[ Version >= 201
Pull "R11, PC", NE
MRS R11, CPSR ; Preserve old processor state
......@@ -867,10 +866,6 @@ Exit7D
MSR CPSR_c, R11 ; Switch back to original mode, with V_bit intact from SWI
Pull "R11, PC"
|
STREQB R12, [R12, #IRQ_CallBack_Flag-1]
]
Pull "R11, PC"
; Acknowledge ESCAPE
Osbyte7E ROUT
......
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