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Commit 2b17314a authored by Mike Stephens's avatar Mike Stephens
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partial video changes for kernel/HAL split near-HAL code for VIDC/IOMD in... 

partial video changes for kernel/HAL split near-HAL code for VIDC/IOMD in vdu.vduhint briefly tested in Ursula desktop build still some kernel workspace dependency in near-HAL code

Version 5.35, 4.79.2.3. Tagged as 'Kernel-5_35-4_79_2_3'
parent 3cd8d7bb
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MkRom,fd7
View file @ 2b17314a
......@@ -14,5 +14,5 @@
|
Dir <Obey$Dir>
time
amu_machine rom debug THROWBACK=-throwback
do amu_machine rom debug THROWBACK=-throwback
time
VersionASM
View file @ 2b17314a
......@@ -11,10 +11,10 @@
GBLS Module_HelpVersion
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.2"
Module_Date SETS "02 Oct 2000"
Module_ApplicationDate2 SETS "02-Oct-00"
Module_ApplicationDate4 SETS "02-Oct-2000"
Module_FullVersion SETS "5.35 (4.79.2.2)"
Module_HelpVersion SETS "5.35 (02 Oct 2000) 4.79.2.2"
Module_MinorVersion SETS "4.79.2.3"
Module_Date SETS "03 Oct 2000"
Module_ApplicationDate2 SETS "03-Oct-00"
Module_ApplicationDate4 SETS "03-Oct-2000"
Module_FullVersion SETS "5.35 (4.79.2.3)"
Module_HelpVersion SETS "5.35 (03 Oct 2000) 4.79.2.3"
END
VersionNum
View file @ 2b17314a
......@@ -4,16 +4,16 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.2
#define Module_Date_CMHG 02 Oct 2000
#define Module_MinorVersion_CMHG 4.79.2.3
#define Module_Date_CMHG 03 Oct 2000
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.2"
#define Module_Date "02 Oct 2000"
#define Module_MinorVersion "4.79.2.3"
#define Module_Date "03 Oct 2000"
#define Module_ApplicationDate2 "02-Oct-00"
#define Module_ApplicationDate4 "02-Oct-2000"
#define Module_ApplicationDate2 "03-Oct-00"
#define Module_ApplicationDate4 "03-Oct-2000"
#define Module_FullVersion "5.35 (4.79.2.2)"
#define Module_HelpVersion "5.35 (02 Oct 2000) (4.79.2.2)"
#define Module_FullVersion "5.35 (4.79.2.3)"
#define Module_HelpVersion "5.35 (03 Oct 2000) (4.79.2.3)"
hdr/KernelWS
View file @ 2b17314a
......@@ -485,6 +485,21 @@ OSBYTEVarSize * @-OSBYTEFirstVar
; End of variables' space
; *** layout of a descriptor block for a display pointer shape ***
^ 0
PointerBlkHAL # 0 ; fields up to private part passed to HAL
PointerWidth # 1 ; actual (unpadded) shape width in bytes (from OS_Word 21)
PointerHeight # 1 ; shape height in pixels
# 2 ; alignment padding
PointerBuffLA # 4 ; logical address of shape buffer (up to 8 * 32 bytes)
PointerBuffPA # 4 ; physical address of shape buffer
PointerBlkPrivate # 0 ; fields below here not used by HAL
PointerActiveX # 1 ; active x in pixels from left
PointerActiveY # 1 ; active y in pixels from top
# 2 ; alignment padding
PointerBlkSize # 0
; ***********************************
; *** Main Vdu Driver Workspace ***
......@@ -571,7 +586,7 @@ BitsPerPix # 4 ; Bits per pixel (1,2,4,8)
BytesPerChar # 4 ; Bytes per 8 pixels of character
; (same as BitsPerPix except in double pixel modes)
CursorFudgeFactor # 4 ; Factor for horizontal cursor positioning
# 4 ; SPARE (avoiding changes of exported addresses for now)
RowMult # 4 ; Row multiplier for text manipulation
......@@ -688,13 +703,9 @@ EndMask # 4
FontOffset # 4
TempPlain # 16 ; only used for MODE 10
VIDCClockSpeed # 4 ; current VIDC clock speed in kHz
CurrentMonitorType # 4 ; initialised from configured one
[ STB
PixelRate # 4 ; Pixel Rate in kHz
]
GraphicWs # 300 ; All graphics workspace is overlaid here
EndGraphicWs # 0
......@@ -720,13 +731,33 @@ TCharSpacing # 0
TCharSpaceX # 4 ; horizontal spacing between VDU 4 chars in pixels
TCharSpaceY # 4 ; vertical ------------------""-----------------
HLineAddr # 4 ; address of exported HLine
HLineAddr # 4 ; address of exported HLine
GcolOraEorAddr # 4 ; address of FgEcfOraEor etc
FirPalSetting # 4*28 ; First palette settings (not used on VIDC20)
FirPalAddr * FirPalSetting ; Address of block for first palette setting (only used on VIDC20)
SecPalSetting # 4*28 ; Second palette settings (not used on VIDC20)
SecPalAddr * SecPalSetting ; Address of block for second palette setting (only used on VIDC20)
BlankPalAddr # 4 ; address of block for blank palette
FirPalAddr # 4 ; address of block for first flash state palette
SecPalAddr # 4 ; address of block for second flash state palette
PointerShapes # 0
PointerShape1 # 4 ; pointers to defined shapes 1 to 4
PointerShape2 # 4
PointerShape3 # 4
PointerShape4 # 4
PointerShapesH # 0
PointerShapeH1 # 4 ; pointers to holding shapes 1 and 2 (so updates never hit shape given to HAL)
PointerShapeH2 # 4
PointerShapeBlocks # 6*PointerBlkSize ; room for the 6 shape descriptors themselves
PointerShapeLA # 4 ; logical address of current shape buffer (owned by HAL)
PointerShapeNumber # 1 ; includes bit 7 linkage flag
# 3 ; alignment padding
PointerX # 4 ; co-ordinates of pointer (not always = mouse)
PointerY # 4
! 0, "PointerShapes @ ":CC::STR:(PointerShapes)
# 43*4 - 6*PointerBlkSize ; SPARE (avoiding changes of exported addresses for now)
TextFgColour # 4 ; Fg/Bg colour stored as a colour number, computed on VDU 18 and re-poked!
TextBgColour # 4 ;
......@@ -739,8 +770,7 @@ TextBgColour # 4 ;
TextExpandArea # 4 ; Pointer to Text expand area (in system heap)
TextExpandArea_Size * (8*1024)
HSWRSoftCopy # 4 ; soft copy of h.sync width register (for DPMS)
VSWRSoftCopy # 4 ; soft copy of v.sync width register (for DPMS)
# 2*4 ; SPARE (avoiding changes of exported addresses for now)
;ScreenBlankFlag # 1 ; 0 => unblanked, 1 => blanked
......@@ -786,17 +816,7 @@ SpAreaStart # 4 ; Start of sprite area
SpChooseName # 16 ; No comment says Richard
SpChoosePtr # 4
PointerHeights # 4 ; 4 x 1 byte
PointerActiveXs # 4 ; 4 x 1 byte
PointerActiveYs # 4 ; 4 x 1 byte
PointerShapeNumber # 1 ; includes bit 7 linkage flag
PointerShapeChanged # 1 ; non-zero: change shape next vsync
# 2
PointerX # 4 ; co-ordinates of pointer (not always = mouse)
PointerY # 4
VIDCControlCopy # 4 ; Soft copy of VIDC control register
VertAdjust # 4 ; offset to add to vertical VIDC registers
# 8*4 ; SPARE (avoiding changes of exported addresses for now)
TeletextOffset # 4 ; Offset to current teletext flash bank
......@@ -874,9 +894,7 @@ ClipBoxTRow # 4
FgPattern # 4*8 ; foreground pattern as defined by OS_SetColour
BgPattern # 4*8 ; background pattern as defined by OS_SetColour
VIDCExternalSoftCopy # 4 ; soft copy of VIDCExternal
VIDCFSynSoftCopy # 4 ; soft copy of VIDCFSyn
VIDCControlSoftCopy # 4 ; soft copy of VIDCControl
# 3*4 ; SPARE (avoiding changes of exported addresses for now)
KernelModeSelector # 4 ; pointer to block in system heap where
; current mode selector is copied
......@@ -1149,8 +1167,8 @@ ProcVecPreVeneers # ProcVecPreVeneersSize
Export_DebuggerSpace # 16*8 ; Debugger module needs some zero page
[ E2ROMSupport
NVRamSize # 1 ; Size of NVRam (E2ROM & CMOS) fitted in 256byte units
RTCFitted # 1 ; flag =1 iff RTC is fitted
NVRamSize # 1 ; Size of NVRam (E2ROM & CMOS) fitted in 256byte units
RTCFitted # 1 ; flag =1 iff RTC is fitted
]
[ E2ROMSupport
......@@ -1173,14 +1191,14 @@ AplWorkSize * AppSpaceDANode + DANode_Size
EnvString # 256
! 0, "Free space after EnvString = ":CC::STR:(&500-@)
! 0, "Free space after EnvString = ":CC::STR:(&500-@)
ASSERT @ <= &500 ; a convenient address to remember
# (&500-@)
CamMapCorruptDebugBlock # &40 ; somewhere to dump registers in case of emergency
! 0, "Free space after CamMap debug block = ":CC::STR:((JordanWS+256*4)-@)
! 0, "Free space after CamMap debug block = ":CC::STR:((JordanWS+256*4)-@)
ASSERT @ <= JordanWS+256*4
# (JordanWS+256*4-@) ; pad out to original size
......@@ -1243,8 +1261,15 @@ ChocolateMSBlocks # 4 ; -> array of blocks for module SWI hash n
! 0, "ChocolateMRBlocks at ":CC::STR:(ChocolateMRBlocks)
! 0, "ChocolateMABlocks at ":CC::STR:(ChocolateMABlocks)
! 0, "ChocolateMSBlocks at ":CC::STR:(ChocolateMSBlocks)
[ {TRUE}
mjs_tempHALworkspace # 4 ; required only temporarily for semi-HALised code still in RO kernel
! 0, "*** mjs_tempHALworkspace should be removed when kernel/HAL split permits"
; !!!! Free Space (36 bytes)
OldSWIHashspace # 9*4
|
; !!!! Free Space (40 bytes)
OldSWIHashspace # 10*4
]
|
; !!!! Free Space (64 bytes)
OldSWIHashspace # 16*4
......@@ -1598,12 +1623,18 @@ Export_SoundWorkSpace |#| SoundWorkSpaceSize + SoundEvtSize
]
; Cursor
; mjs Sep 2000, Kernel/HAL split
; Note that cursor data memory is expected to be uncacheable, since HAL may use it
; directly for h/w DMA. This may not be true since RO 3.7, but should be sorted
; eventually for next generation RO
CursorDataSize * &800
CursorDataSize * &600 ; four defined shapes, plus 2 holding shapes
CursorData |#| CursorDataSize
CursorSoundRAM * CursorData
CursorSoundPhysRAM * CursorSoundRAM + OffsetLogicalToPhysical
SPARE_oldCursorSpace |#| &200 ; padding to avoid changing exported addresses for now
; SWI despatcher
Export_BranchToSWIExit |#| 4
......
s/ARM600
View file @ 2b17314a
This diff is collapsed.
s/GetAll
View file @ 2b17314a
......@@ -174,15 +174,9 @@ AlwaysClearRAM SETL {TRUE}
GBLL CacheCMOSRAM ; Whether to keep a RAM copy of CMOS RAM for faster access
CacheCMOSRAM SETL MEMM_Type = "ARM600" ; (Space only allocated on ARM600 versions)
GBLL GammaCorrection
GammaCorrection SETL (VIDC_Type = "VIDC20") :LAND: {TRUE}
GBLL LCDInvert
LCDInvert SETL (VIDC_Type = "VIDC20") :LAND: {TRUE} :LAND: :LNOT: STB
GBLL VIDCListType3
VIDCListType3 SETL (VIDC_Type = "VIDC20") :LAND: {TRUE}
GBLL ExpandedCamMap ; two words per entry instead of one
ExpandedCamMap SETL MEMM_Type = "ARM600" ; NB ARM600 code assumes expanded map
......@@ -220,13 +214,11 @@ OnlyKernelCanAccessHardwareVectors SETL {TRUE} ; if true, only the Kernel is pe
; and the Shared C Library - eg any memcpy!)
GBLL StrongARM
GBLL SAWBbroken ;whether StrongARM Write Buffer is broken (pass 1 silicon only)
GBLL SAcleanflushbroken ;whether StrongARM single MCR for DC clean+flush broken (is always for SA110)
GBLL SASTMhatbroken ;whether ROM must support SA110's with broken STM^ (revision 3 should fix this)
GBLL StrongARM_POST ;whether to run POST for StrongARM (and possibly ARM8)
GBLL ARM810support ;StrongARM must also be true for this to be useful
GBLL ARM810bpbroken ;whether branch predict is broken
GBLL ARM810cleanflushbroken ;whether single MCR for IDC clean+flush broken (a la StrongARM!)
GBLL ARM810fastclock ;whether to attempt to use fast clock (false means bus clock)
GBLL ARM810usePLL ;whether to use PLL for fast clock (else RefClk pin)
......@@ -235,13 +227,11 @@ OnlyKernelCanAccessHardwareVectors SETL {TRUE} ; if true, only the Kernel is pe
GBLL ARM6support
StrongARM SETL {TRUE}
SAWBbroken SETL {FALSE} :LAND: StrongARM
SAcleanflushbroken SETL {TRUE} :LAND: StrongARM
SASTMhatbroken SETL {TRUE} :LAND: StrongARM
StrongARM_POST SETL {TRUE} :LAND: StrongARM
ARM810support SETL {FALSE} :LAND: StrongARM
ARM810bpbroken SETL {TRUE} :LAND: ARM810support
ARM810cleanflushbroken SETL {TRUE} :LAND: ARM810support
ARM810fastclock SETL {FALSE} :LAND: ARM810support
ARM810usePLL SETL {TRUE} :LAND: ARM810fastclock
......@@ -446,7 +436,7 @@ GetFlashROM SETS ""
GetKernelMEMC SETS "GET s.ARM600"
GetMemInfo SETS "GET s.MemInfo"
GetPalette SETS "GET s.Vdu.VduPal20"
GetPalette SETS "GET s.vdu.vdupalxx"
[ HAL
GetHAL SETS "GET s.HAL"
|
......@@ -605,6 +595,7 @@ MaxSwi * OS_NVMemory+1
$GetMemInfo
! 0, "Main kernel size = &" :CC: :STR: (.-KernelBase)
StartOfVduDriver
GET s.vdu.vduhint
GET s.vdu.VduDriver
GET s.vdu.VduSWIs
GET s.vdu.VduPalette
......
s/Kernel
View file @ 2b17314a
......@@ -673,15 +673,16 @@ JTABLE & SWIWriteC ; this entry never gets used (see ^)
& NoSuchSWI
]
; The following SWIs are not available in this kernel.
& NoSuchSWI ; SpecialControl
& NoSuchSWI ; EnterUSR32SWI
& NoSuchSWI ; EnterUSR26SWI
& NoSuchSWI ; SpecialControl
& NoSuchSWI ; EnterUSR32SWI
& NoSuchSWI ; EnterUSR26SWI
; End of unavailable SWIs.
; Should not cause any problems on any machine. STB flag just to be safe though.
[ STB :LAND: {TRUE}
& VIDCDividerSWI
[ STB :LAND: {FALSE}
& VIDCDividerSWI
|
& NoSuchSWI
! 0, "mjsHAL - VIDCDividerSWI not implemented"
& NoSuchSWI
]
& NVMemorySWI
......
s/PMF/i2cutils
View file @ 2b17314a
......@@ -161,7 +161,7 @@ ReadC1C0 ROUT
Pull "sb,pc"
|
MOV a3, #IOC
LDRB a3, [a3, #IOCControl]
LDRB a1, [a3, #IOCControl]
MOV a2, a1, LSR #1
AND a1, a1, #1
AND a2, a2, #1
......
s/PMF/osbyte
View file @ 2b17314a
......@@ -707,11 +707,9 @@ Osbyte6A
BHI %FT90 ; ignore change if too high
TEQ R1, R3
STRNEB R1, [R0, #PointerShapeNumber]
MOVNE R1, #1
STRNEB R1, [R0, #PointerShapeChanged]
BEQ %FT90 ; same as old
; the shape will change on the next vsync
STRB R1, [R0, #PointerShapeNumber] ; will take effect on next vsync (UpdatePointer)
90 MOV R1, R3
MyOsbyte
......
s/vdu/vdu23
View file @ 2b17314a
......@@ -1523,13 +1523,11 @@ Vdu23_0_8 ROUT
TST R1, #1
EORNE R0, R0, #1 ; toggle if *TV n,1 and number +ve
10
LDR R1, [WsPtr, #VIDCControlCopy]
BIC R1, R1, #CR_Interlace
TST R0, #1
ORRNE R1, R1, #CR_Interlace ; zero => no interlace
Push "R0-R3, R9, R12, LR"
mjsAddressHAL
mjsCallHAL HAL_Video_SetInterlace
Pull "R0-R3, R9, R12, LR"
MOV R0, #VIDC
STR R1, [R0] ; program VIDC
MOV PC, R14
[ DoVdu23_0_12
......
s/vdu/vdudecl
View file @ 2b17314a
......@@ -43,145 +43,6 @@ Link RN 14
; Manifest constants
; ==================
;
[ VIDC_Type = "VIDC20"
; Registers
VIDCPalAddress * &10000000 ; used in palette programming
LCDOffsetRegister0 * &30000000
LCDOffsetRegister1 * &31000000
HorizCycle * &80000000
HorizSyncWidth * &81000000
HorizBorderStart * &82000000
HorizDisplayStart * &83000000
HorizDisplayEnd * &84000000
HorizBorderEnd * &85000000
HorizCursorStart * &86000000 ; used in pointer programming
HorizInterlace * &87000000
VertiCycle * &90000000
VertiSyncWidth * &91000000 ; Needed to set up FSIZE register in IOMD
VertiBorderStart * &92000000 ; First register affected by *TV
VertiDisplayStart * &93000000
VertiDisplayEnd * &94000000
VertiBorderEnd * &95000000
VertiCursorStart * &96000000
VertiCursorEnd * &97000000 ; Last register affected by *TV
VIDCExternal * &C0000000
VIDCFSyn * &D0000000
VIDCControl * &E0000000
VIDCDataControl * &F0000000
; Pseudo-registers used to return additional information to kernel
PseudoRegisters * 5 ; number of pseudo-register entries at end of table
PseudoRegister_HClockSpeed * &FB000000 ; used to indicate VIDC hclock speed (and use it)
PseudoRegister_ClockSpeed * &FC000000 ; used to indicate real VIDC rclock speed
PseudoRegister_DPMSState * &FD000000 ; used to return desired DPMS state
[ ChrontelSupport
PseudoRegister_PixelRate * &FE000000 ; used to indicate the required pixel rate
]
; Bits in VCSR, VCER
CursorSinglePanel * 0 :SHL: 13
CursorTopPanel * 1 :SHL: 13
CursorBottomPanel * 1 :SHL: 14
CursorStraddle * 3 :SHL: 13
; Bits in external register
Ext_HSYNCbits * 3 :SHL: 16
Ext_InvertHSYNC * 1 :SHL: 16
Ext_CompHSYNC * 2 :SHL: 16
Ext_InvertCompHSYNC * 3 :SHL: 16
Ext_VSYNCbits * 3 :SHL: 18
Ext_InvertVSYNC * 1 :SHL: 18
Ext_CompVSYNC * 2 :SHL: 18
Ext_InvertCompVSYNC * 3 :SHL: 18
Ext_HiResMono * 1 :SHL: 14
Ext_LCDGrey * 1 :SHL: 13
Ext_DACsOn * 1 :SHL: 12
Ext_PedsOn * 7 :SHL: 8
Ext_PedsShift * 8
Ext_ERegShift * 4
Ext_ECKOn * 1 :SHL: 2
Ext_ERegBits * 3 :SHL: 0
Ext_ERegRed * 0 :SHL: 0
Ext_ERegGreen * 1 :SHL: 0
Ext_ERegBlue * 2 :SHL: 0
Ext_ERegExt * 3 :SHL: 0 ; use this for lowest power
; Bits in Frequency Synthesizer Register
FSyn_VShift * 8
FSyn_RShift * 0
FSyn_ClearV * 1 :SHL: 15
FSyn_ForceLow * 1 :SHL: 14
FSyn_ClearR * 1 :SHL: 7
FSyn_ForceHigh * 1 :SHL: 6
FSyn_ResetValue * FSyn_ClearV :OR: FSyn_ClearR :OR: FSyn_ForceLow :OR: (63 :SHL: FSyn_RShift) :OR: (0 :SHL: FSyn_VShift) ; value to get PLL working properly
; Bits in Control Register
CR_DualPanel * 1 :SHL: 13
CR_Interlace * 1 :SHL: 12
CR_FIFOLoadShift * 8
CR_LBPP0 * 0 :SHL: 5
CR_LBPP1 * 1 :SHL: 5
CR_LBPP2 * 2 :SHL: 5
CR_LBPP3 * 3 :SHL: 5
CR_LBPP4 * 4 :SHL: 5
CR_LBPP5 * 6 :SHL: 5 ; spot the gap!
CR_PixelDivShift * 2
CR_VCLK * 0 :SHL: 0
CR_HCLK * 1 :SHL: 0
CR_RCLK * 2 :SHL: 0
; Bits in Data Control Register
DCR_VRAMOff * 0 :SHL: 18
DCR_VRAMDiv1 * 1 :SHL: 18
DCR_VRAMDiv2 * 2 :SHL: 18
DCR_VRAMDiv4 * 3 :SHL: 18
DCR_BusBits * 3 :SHL: 16
DCR_Bus31_0 * 1 :SHL: 16
DCR_Bus63_32 * 2 :SHL: 16
DCR_Bus63_0 * 3 :SHL: 16
DCR_HDis * 1 :SHL: 13
DCR_Sync * 1 :SHL: 12
DCR_HDWRShift * 0
|
; Registers
HorizDisplayStart * &8C000000 ; used in mode change code
HorizCursorStart * &98000000 ; used in pointer programming
VertiBorderStart * &A8000000 ; First register affected by *TV
VertiDisplayStart * &AC000000
VertiCursorStart * &B8000000
VertiCursorEnd * &BC000000 ; Last register affected by *TV
SoundFrequency * &C0000000
VIDCControl * &E0000000
; Bits in control register
CR_Interlace * &40 ; 0 - no interlace, 64 - interlace
CompSync * &80 ; Controls sync signal on CS/VS pin
; 0 - output vertical sync, 128 - composite sync.
; Other bits
SupBit * &1000 ; Supremacy bit in palette
]
PhysCursorStartAdr * CursorSoundPhysRAM
......
s/vdu/vdudriver
View file @ 2b17314a
This diff is collapsed.
s/vdu/vduhint 0 → 100644
View file @ 2b17314a
This diff is collapsed.
s/vdu/vdumodes
View file @ 2b17314a
......@@ -19,13 +19,12 @@
; pixel rate specifiers
[ VIDC_Type = "VIDC20"
MACRO
Moduli $pixrate, $v, $r, $d
[ ChrontelSupport
CRPix_$pixrate * CR_HCLK :OR: ((1-1) :SHL: CR_PixelDivShift)
FSyn_$pixrate * (63 :SHL: FSyn_VShift) :OR: ((64-1):SHL:FSyn_RShift)
CRPix_$pixrate * CR_HCLK :OR: ((1-1) :SHL: CR_PixelDivShift)
FSyn_$pixrate * (63 :SHL: FSyn_VShift) :OR: ((64-1):SHL:FSyn_RShift)
|
[ ($v=$r)
CRPix_$pixrate * CR_RCLK :OR: ($d-1) :SHL: CR_PixelDivShift
......@@ -43,23 +42,23 @@ FSyn_$pixrate * (($v-1):SHL:FSyn_VShift) :OR: (($r-1):SHL:FSyn_RShift)
MACRO
Moduli32 $pixrate, $v, $r, $d
[ ChrontelSupport
CRPix32_$pixrate * CR_HCLK :OR: ((1-1) :SHL: CR_PixelDivShift)
FSyn32_$pixrate * (63 :SHL: FSyn_VShift) :OR: ((64-1):SHL:FSyn_RShift)
CRPix32_$pixrate * CR_HCLK :OR: ((1-1) :SHL: CR_PixelDivShift)
FSyn32_$pixrate * (63 :SHL: FSyn_VShift) :OR: ((64-1):SHL:FSyn_RShift)
|
[ {FALSE}
[ $pixrate >= 12500
CRPix32_$pixrate * CR_HCLK :OR: (1-1) :SHL: CR_PixelDivShift ; if pixrate > 12.5MHz then use divide-by-1, and HCLK
CRPix32_$pixrate * CR_HCLK :OR: (1-1) :SHL: CR_PixelDivShift ; if pixrate > 12.5MHz then use divide-by-1, and HCLK
|
CRPix32_$pixrate * CR_HCLK :OR: (2-1) :SHL: CR_PixelDivShift ; else use divide-by-2, and HCLK
CRPix32_$pixrate * CR_HCLK :OR: (2-1) :SHL: CR_PixelDivShift ; else use divide-by-2, and HCLK
]
FSyn32_$pixrate * ((2-1):SHL:FSyn_VShift) :OR: ((64-1):SHL:FSyn_RShift) ; moduli irrelevant, so set to min V, max R
FSyn32_$pixrate * ((2-1):SHL:FSyn_VShift) :OR: ((64-1):SHL:FSyn_RShift) ; moduli irrelevant, so set to min V, max R
|
[ ($v=$r)
CRPix32_$pixrate * CR_RCLK :OR: ($d-1) :SHL: CR_PixelDivShift
FSyn32_$pixrate * ((64-1):SHL:FSyn_VShift) :OR: ((64-1):SHL:FSyn_RShift)
CRPix32_$pixrate * CR_RCLK :OR: ($d-1) :SHL: CR_PixelDivShift
FSyn32_$pixrate * ((64-1):SHL:FSyn_VShift) :OR: ((64-1):SHL:FSyn_RShift)
|
CRPix32_$pixrate * CR_VCLK :OR: ($d-1) :SHL: CR_PixelDivShift
FSyn32_$pixrate * (($v-1):SHL:FSyn_VShift) :OR: (($r-1):SHL:FSyn_RShift)
CRPix32_$pixrate * CR_VCLK :OR: ($d-1) :SHL: CR_PixelDivShift
FSyn32_$pixrate * (($v-1):SHL:FSyn_VShift) :OR: (($r-1):SHL:FSyn_RShift)
]
]
]
......@@ -89,7 +88,7 @@ FSyn32_$pixrate * (($v-1):SHL:FSyn_VShift) :OR: (($r-1):SHL:FSyn_RShift)
;
; Updated by TMD 28-Jan-94 to use new VCO range 55-110MHz
;
; Values suitable for any machine with rclk=24MHz (eg Medussa)
; Values suitable for any machine with rclk=24MHz (eg Medusa)
;
Moduli 24000, 2, 2, 1
Moduli 16000, 8, 2, 6
......@@ -108,186 +107,119 @@ FSyn32_$pixrate * (($v-1):SHL:FSyn_VShift) :OR: (($r-1):SHL:FSyn_RShift)
Moduli 17600, 11, 3, 5 ; 17.6
Moduli 35200, 22, 5, 3 ; 35.2
| ; VIDC_Type = "VIDC20"
CRPix_24000 * 3 :OR: (0 :SHL: ClockControlShift)
CRPix_16783 * 2 :OR: (1 :SHL: ClockControlShift)
CRPix_16000 * 2 :OR: (0 :SHL: ClockControlShift)
CRPix_12587 * 1 :OR: (1 :SHL: ClockControlShift)
CRPix_12000 * 1 :OR: (0 :SHL: ClockControlShift)
CRPix_8392 * 0 :OR: (1 :SHL: ClockControlShift)
CRPix_8000 * 0 :OR: (0 :SHL: ClockControlShift)
CRPix_25175 * 3 :OR: (1 :SHL: ClockControlShift)
CRPix_36000 * 3 :OR: (2 :SHL: ClockControlShift)
]
; mjs Kernel/HAL split
;
; BigVIDCTable is now in hardware independent format, ie. a VIDC list type 3
;
; Macro VIDC_List10 removed - hardware specific, and very old anyway! (VIDC1 is pre Medusa)
; Macro VIDC_List20 removed - hardware specific, not needed in HAL either
; Macro VIDC_ListT3 newly defined
MACRO
$label VIDC_List $lbpp,$hsync,$hbpch,$hlbdr,$hdisp,$hrbdr,$hfpch, $vsync,$vbpch,$vlbdr,$vdisp,$vrbdr,$vfpch,$pixrate,$sp
[ VIDC_Type = "VIDC20"
$label VIDC_List20 $lbpp,$hsync,$hbpch,$hlbdr,$hdisp,$hrbdr,$hfpch, $vsync,$vbpch,$vlbdr,$vdisp,$vrbdr,$vfpch,$pixrate,$sp
|
$label VIDC_List10 $lbpp,$hsync,$hbpch,$hlbdr,$hdisp,$hrbdr,$hfpch, $vsync,$vbpch,$vlbdr,$vdisp,$vrbdr,$vfpch,$pixrate,$sp
]
$label VIDC_ListT3 $lbpp,$hsync,$hbpch,$hlbdr,$hdisp,$hrbdr,$hfpch, $vsync,$vbpch,$vlbdr,$vdisp,$vrbdr,$vfpch,$pixrate,$sp
MEND
; VIDC1 format VIDC list
MACRO
$label VIDC_List10 $lbpp,$hsync,$hbpch,$hlbdr,$hdisp,$hrbdr,$hfpch, $vsync,$vbpch,$vlbdr,$vdisp,$vrbdr,$vfpch,$pixrate,$sp
$label
LCLA sub
LCLA sp
LCLA syncpol
LCLA hbpch
LCLA hfpch
[ :LNOT: AssemblingArthur
& 0 ; VIDC list type (default)
& 0 ; base mode (irrelevant, all entries overwritten)
]
[ $lbpp = 3
sub SETA 5
]
[ $lbpp = 2
sub SETA 7
]
[ $lbpp = 1
sub SETA 11
]
[ $lbpp = 0
sub SETA 19
]
[ "$sp"=""
syncpol SETA 0 :SHL: SyncControlShift ; normal sync polarity
|
ASSERT $sp<=3
syncpol SETA $sp :SHL: SyncControlShift
]
;
; format of a VIDC list type 3
;
^ 4
VIDCList3_PixelDepth # 4
VIDCList3_HorizSyncWidth # 4
VIDCList3_HorizBackPorch # 4
VIDCList3_HorizLeftBorder # 4
VIDCList3_HorizDisplaySize # 4
VIDCList3_HorizRightBorder # 4
VIDCList3_HorizFrontPorch # 4
VIDCList3_VertiSyncWidth # 4
VIDCList3_VertiBackPorch # 4
VIDCList3_VertiTopBorder # 4
VIDCList3_VertiDisplaySize # 4
VIDCList3_VertiBottomBorder # 4
VIDCList3_VertiFrontPorch # 4
VIDCList3_PixelRate # 4
VIDCList3_SyncPol # 4 ; sync polarity/flag bits
VIDCList3_ControlList # 0 ; possibly empty list of pairs of index,value words
;
; and VIDCList3 is terminated by a -1 word
;
; Indices in VIDCList3_ControlList
;
^ 1
ControlList_LCDMode # 1
ControlList_LCDDualPanelMode # 1
ControlList_LCDOffset0 # 1
ControlList_LCDOffset1 # 1
ControlList_HiResMode # 1
ControlList_DACControl # 1
ControlList_RGBPedestals # 1
ControlList_ExternalRegister # 1
ControlList_HClockSelect # 1
ControlList_RClockFrequency # 1
ControlList_DPMSState # 1
ControlList_Interlaced # 1
ControlList_InvalidReason # 0
; bits/flags in VIDCList3_SyncPol word:
;
SyncPol_InvertHSync * 1
SyncPol_InvertVSync * 2
SyncPol_InterlaceSpecified * 4 ; if set, interlace bit has been specified, else filled in by kernel
SyncPol_Interlace * 8 ; set=interlaced, either specified by service call claimant or filled in from *TV by kernel
; Note that on VIDC1, hbpch and hfpch must be odd, and on VIDC20 they must be even
; The macro now specifies them as even.
; So increase back porch and reduce front porch by 1
ASSERT ($hsync :AND: 1)=0
ASSERT ($hbpch :AND: 1)=0
hbpch SETA ($hbpch) + 1
ASSERT ($hlbdr :AND: 1)=0
ASSERT ($hdisp :AND: 1)=0
ASSERT ($hrbdr :AND: 1)=0
ASSERT ($hfpch :AND: 1)=0
hfpch SETA ($hfpch) - 1
[ (($hsync+hbpch+$hlbdr+$hdisp+$hrbdr+hfpch) :AND: 3)<>0
! 0, "Warning: mode unsuitable for interlaced use"
]
; Horizontal
& (&80:SHL:24) :OR: ((($hsync+hbpch+$hlbdr+$hdisp+$hrbdr+hfpch -2 )/2) :SHL: 14) ; HCR
& (&84:SHL:24) :OR: ((($hsync -2 )/2) :SHL: 14) ; HSWR
& (&88:SHL:24) :OR: ((($hsync+hbpch -1 )/2) :SHL: 14) ; HBSR
& (&8C:SHL:24) :OR: ((($hsync+hbpch+$hlbdr -sub)/2) :SHL: 14) ; HDSR
& (&90:SHL:24) :OR: ((($hsync+hbpch+$hlbdr+$hdisp -sub)/2) :SHL: 14) ; HDER
& (&94:SHL:24) :OR: ((($hsync+hbpch+$hlbdr+$hdisp+$hrbdr -1 )/2) :SHL: 14) ; HBER
& (&9C:SHL:24) :OR: (((($hsync+hbpch+$hlbdr+$hdisp+$hrbdr+hfpch-2)/2+1)/2):SHL:14); HIR
; Vertical
& (&A0:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr+$vfpch -1) :SHL: 14) ; VCR
& (&A4:SHL:24) :OR: (($vsync -1) :SHL: 14) ; VSWR
& (&A8:SHL:24) :OR: (($vsync+$vbpch -1) :SHL: 14) ; VBSR
& (&AC:SHL:24) :OR: (($vsync+$vbpch+$vlbdr -1) :SHL: 14) ; VDSR
& (&B0:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp -1) :SHL: 14) ; VDER
& (&B4:SHL:24) :OR: (($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr -1) :SHL: 14) ; VBER
; Control Register
& (&E0:SHL:24) :OR: (CRPix_$pixrate) :OR: ($lbpp :SHL: 2) :OR: syncpol
[ ChrontelSupport
& PseudoRegister_PixelRate :OR: $pixrate
]
& -1
MEND
; Macro VIDC_ListT3 - for hardware independent table (using 'VIDC' list type 3 format, see PRM 5a-125)
;
MACRO
$label VIDC_List20 $lbpp,$hsync,$hbpch,$hlbdr,$hdisp,$hrbdr,$hfpch, $vsync,$vbpch,$vlbdr,$vdisp,$vrbdr,$vfpch,$pixrate,$sp
$label VIDC_ListT3 $lbpp,$hsync,$hbpch,$hlbdr,$hdisp,$hrbdr,$hfpch, $vsync,$vbpch,$vlbdr,$vdisp,$vrbdr,$vfpch,$pixrate,$sp
$label
LCLA sp
LCLA syncpol
LCLA dwidth
GBLA framerate
LCLA framepixels
[ :LNOT: AssemblingArthur
& 0 ; VIDC list type (default)
& 0 ; base mode (irrelevant, all entries overwritten)
]
[ "$sp"=""
sp SETA 0 ; normal sync polarity
|
ASSERT $sp<=3
sp SETA $sp
]
syncpol SETA 0
[ (sp :AND: 1) <> 0
syncpol SETA syncpol :OR: Ext_InvertHSYNC
]
[ (sp :AND: 2) <> 0
syncpol SETA syncpol :OR: Ext_InvertVSYNC
]
ASSERT ($hsync :AND: 1)=0
ASSERT ($hbpch :AND: 1)=0
ASSERT ($hlbdr :AND: 1)=0
ASSERT ($hdisp :AND: 1)=0
ASSERT ($hrbdr :AND: 1)=0
ASSERT ($hfpch :AND: 1)=0
ASSERT (($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch) :AND: 3)=0
; just to check width is whole number of words (to suit rendering code)
dwidth SETA $hdisp :SHL: $lbpp
ASSERT (dwidth :AND: 31) = 0
dwidth SETA dwidth / 32
framepixels SETA ($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch)*($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr+$vfpch)
framerate SETA ($pixrate*1000+framepixels/2)/framepixels
F_$label * framerate ; set up frame rate symbol
; Horizontal
& (&80:SHL:24) :OR: ($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch-8) ; HCR
& (&81:SHL:24) :OR: ($hsync -8) ; HSWR
& (&82:SHL:24) :OR: ($hsync+$hbpch -12) ; HBSR
& (&83:SHL:24) :OR: ($hsync+$hbpch+$hlbdr -18) ; HDSR
& (&84:SHL:24) :OR: ($hsync+$hbpch+$hlbdr+$hdisp -18) ; HDER
& (&85:SHL:24) :OR: ($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr -12) ; HBER
& (&87:SHL:24) :OR: ($hsync+$hbpch+$hlbdr+$hdisp+$hrbdr+$hfpch )/2 ; HIR
; Vertical
& (&90:SHL:24) :OR: ($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr+$vfpch -2) ; VCR
& (&91:SHL:24) :OR: ($vsync -2) ; VSWR
& (&92:SHL:24) :OR: ($vsync+$vbpch -2) ; VBSR
& (&93:SHL:24) :OR: ($vsync+$vbpch+$vlbdr -2) ; VDSR
& (&94:SHL:24) :OR: ($vsync+$vbpch+$vlbdr+$vdisp -2) ; VDER
& (&95:SHL:24) :OR: ($vsync+$vbpch+$vlbdr+$vdisp+$vrbdr -2) ; VBER
; Data Control Register
[ MEMC_Type = "IOMD"
; Note: the bus bits get overwritten by the mode change code, to set it up correctly for 1 or 2 MBytes of VRAM
& VIDCDataControl :OR: DCR_VRAMOff :OR: DCR_Bus31_0 :OR: (dwidth :SHL: DCR_HDWRShift) :OR: DCR_Sync
|
& VIDCDataControl :OR: DCR_VRAMOff :OR: DCR_Bus31_0 :OR: (dwidth :SHL: DCR_HDWRShift)
]
; External Register
& VIDCExternal :OR: Ext_DACsOn :OR: Ext_ERegExt :OR: syncpol
; Frequency Synthesizer Register (rclk=24MHz)
& VIDCFSyn :OR: (FSyn_$pixrate)
; Control Register (rclk=24MHz)
& VIDCControl :OR: (4 :SHL: CR_FIFOLoadShift) :OR: (CR_LBPP$lbpp) :OR: (CRPix_$pixrate)
[ ChrontelSupport
& PseudoRegister_PixelRate :OR: $pixrate
]
& -1
[ MorrisSupport
; Frequency Synthesizer Register (32MHz)
& VIDCFSyn :OR: (FSyn32_$pixrate)
; Control Register (32MHz)
& VIDCControl :OR: (4 :SHL: CR_FIFOLoadShift) :OR: (CR_LBPP$lbpp) :OR: (CRPix32_$pixrate)
& -1
]
MEND
;
& 3 ; format (type 3)
& $lbpp ; log2 bits per pixel
; Horizontal (in pixels)
& $hsync ; sync width
& $hbpch ; back porch
& $hlbdr ; left border
& $hdisp ; display size
& $hrbdr ; right border
& $hfpch ; front porch
; Vertical (in rasters)
& $vsync ; sync width
& $vbpch ; back porch
& $vlbdr ; top border
& $vdisp ; display size
& $vrbdr ; bottom border
& $vfpch ; front porch
;
& $pixrate ; pixel rate (kHz)
& sp ; sync polarity
& -1 ; terminator (no video control parameters)
MEND ; MACRO VIDC_ListT3
NumMonitorTypes * 9
NumModes * 50
......@@ -299,27 +231,18 @@ minmode * 0
MACRO
BranchIfKnownMode $reg, $address
[ VIDC_Type = "VIDC20"
CMP $reg, #NumModes
|
CMP $reg, #32 ; if not 32 (EQ => CS)
CMPNE $reg, #NumModes ; and less than ??
]
BCC $address ; then branch
MEND
MACRO
BranchIfNotKnownMode $reg, $address
[ VIDC_Type = "VIDC20"
CMP $reg, #NumModes
|
CMP $reg, #32 ; if not 32 (EQ => CS)
CMPNE $reg, #NumModes ; and less than ??
]
BCS $address ; branch if *NOT* known
MEND
BigVIDCTable
! 0,"BigVIDCTable at ":CC:(:STR:BigVIDCTable)
& VLN_0 - BigVIDCTable ; 0
& VLN_1 - BigVIDCTable ; 1
& VLN_2 - BigVIDCTable ; 2
......@@ -409,11 +332,7 @@ BigVIDCTable
& VLM_29 - BigVIDCTable ; 29
& VLM_30 - BigVIDCTable ; 30
& VLM_31 - BigVIDCTable ; 31
[ VIDC_Type = "VIDC20"
& VLM_32 - BigVIDCTable ; 32
|
& -1 ; 32
]
& VLM_33 - BigVIDCTable ; 33 Ovscn
& VLM_34 - BigVIDCTable ; 34
& VLM_35 - BigVIDCTable ; 35
......@@ -572,11 +491,7 @@ BigVIDCTable
& VLM_29 - BigVIDCTable ; 29
& VLM_30 - BigVIDCTable ; 30
& VLM_31 - BigVIDCTable ; 31
[ VIDC_Type = "VIDC20"
& VLM_32 - BigVIDCTable ; 32
|
& -1 ; 32
]
& -1 ; 33
& -1 ; 34
& -1 ; 35
......@@ -897,9 +812,7 @@ VLM_49 VIDC_List 3, 48, 22, 0, 320, 0, 10, 2,32, 0,480, 0,11,12587,3
; New modes for VIDC20
[ VIDC_Type = "VIDC20"
VLM_32 VIDC_List 3, 72,128, 0, 800, 0, 24, 2,22, 0,600, 0, 1,36000,0 ; MODE 32 (800 x 600 x 8bpp)
]
VLH_23 VIDC_List 2, 52, 46, 2, 288, 2, 2, 3,43, 4,896, 4, 0,24000,0 ; MODE 23
......@@ -934,9 +847,6 @@ VgaX_46 VIDC_List 2, 96, 46, 0, 640, 0,18,2,134, 0,200,0,113,25175,2
; Table of ideal frame rate for each numbered mode, to put in dummy mode selector
; if numbered mode number is not directly available on this monitortype
[ VIDC_Type <> "VIDC20"
F_VLM_32 * 0
]
FrameRateTable
[ HiResTTX
......@@ -1037,13 +947,11 @@ wksize * wkend-wkstart
wkwordsize * (wksize + 3) :AND: :NOT: 3
wklim * wksize-(wkmiddle-wkstart)
[ VIDC_Type = "VIDC20"
VIDCParmsSize * (128*4) ; 128 words from 80xxxxxx to FFxxxxxx step 01000000
|
VIDCParmsSize * (32*4) ; 32 words from 80xxxxxx to FCxxxxxx step 04000000
]
;VIDC list type 3 size (hardware independent video controller list)
;
VIDCList3Size * (64 + 16*8 + 4) ; primary params, up to 16 video control params, terminator
PushedInfoSize * wkwordsize + VIDCParmsSize
PushedInfoSize * wkwordsize + VIDCList3Size
M22S * 1280*976/8 ; screen size
M23S * 1152*896/8
......@@ -1194,11 +1102,7 @@ VW_28 VWSTAB 28,M25S*8,640, 639,479,7,1,1,63, 79, 59,3,3,3,5,0
VW_29 VWSTAB 29,M31S ,100, 799,599,0,1,1, 1, 99, 74,0,0,0,4,0 ; MODE 29
VW_30 VWSTAB 30,M31S*2,200, 799,599,0,1,1, 3, 99, 74,1,1,1,2,0 ; MODE 30
VW_31 VWSTAB 31,M31S*4,400, 799,599,0,1,1,15, 99, 74,2,2,2,3,0 ; MODE 31
[ VIDC_Type = "VIDC20"
VW_32 VWSTAB 32,M31S*8,800, 799,599,0,1,1,63, 99, 74,3,3,3,5,0 ; MODE 32
|
VW_32 * VW_31
]
VW_33 VWSTAB 33, 27K, 96, 767,287,0,1,2, 1, 95, 35,0,0,0,4,0 ; MODE 33
VW_34 VWSTAB 34, 54K,192, 767,287,0,1,2, 3, 95, 35,1,1,1,2,0 ; MODE 34
......
s/vdu/vdupal10
View file @ 2b17314a
......@@ -14,6 +14,8 @@
;
; > VduPal10
; mjs - not used any more (it's pre-Medusa, for goodness sake)
; Palette programming for VIDC10 (ie VIDC1 or VIDC1a)
; *****************************************************************************
......
s/vdu/vdupal20
View file @ 2b17314a
This diff is collapsed.
s/vdu/vdupalxx 0 → 100644
View file @ 2b17314a
This diff is collapsed.
s/vdu/vdupointer
View file @ 2b17314a
This diff is collapsed.
s/vdu/vduswis
View file @ 2b17314a
This diff is collapsed.
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