Deduce CPUFlag_LongMul/Thumb/DSP from the right bitfields

The TST operations for LongMul & Thumb were at odds with the ARM ARM, move those. We can get the DSP flag from an ID register too now, rather than relying on the Q flag being writeable in the PSR.
Fortunately, the fields we were previously TSTing also had set bits - so the OS_PlatformFeatures 0 flags were coming out right anyway on all real ARMv7's.

Version 5.35, 4.79.2.317. Tagged as 'Kernel-5_35-4_79_2_317'

VersionASM

@@ -13,11 +13,11 @@
                         GBLS    Module_ComponentPath
 Module_MajorVersion     SETS    "5.35"
 Module_Version          SETA    535
-Module_MinorVersion     SETS    "4.79.2.316"
-Module_Date             SETS    "14 Apr 2016"
-Module_ApplicationDate  SETS    "14-Apr-16"
+Module_MinorVersion     SETS    "4.79.2.317"
+Module_Date             SETS    "26 Apr 2016"
+Module_ApplicationDate  SETS    "26-Apr-16"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.35 (4.79.2.316)"
-Module_HelpVersion      SETS    "5.35 (14 Apr 2016) 4.79.2.316"
+Module_FullVersion      SETS    "5.35 (4.79.2.317)"
+Module_HelpVersion      SETS    "5.35 (26 Apr 2016) 4.79.2.317"
                         END

VersionNum

@@ -5,19 +5,19 @@
  *
  */
 #define Module_MajorVersion_CMHG        5.35
-#define Module_MinorVersion_CMHG        4.79.2.316
-#define Module_Date_CMHG                14 Apr 2016
+#define Module_MinorVersion_CMHG        4.79.2.317
+#define Module_Date_CMHG                26 Apr 2016
 
 #define Module_MajorVersion             "5.35"
 #define Module_Version                  535
-#define Module_MinorVersion             "4.79.2.316"
-#define Module_Date                     "14 Apr 2016"
+#define Module_MinorVersion             "4.79.2.317"
+#define Module_Date                     "26 Apr 2016"
 
-#define Module_ApplicationDate          "14-Apr-16"
+#define Module_ApplicationDate          "26-Apr-16"
 
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.35 (4.79.2.316)"
-#define Module_HelpVersion              "5.35 (14 Apr 2016) 4.79.2.316"
+#define Module_FullVersion              "5.35 (4.79.2.317)"
+#define Module_HelpVersion              "5.35 (26 Apr 2016) 4.79.2.317"
 #define Module_LibraryVersionInfo       "5:35"

s/ARMops

@@ -980,17 +980,16 @@ ARM_Analyse_Fancy
         STRB    a1, [v6, #ProcessorArch]
 
         MRC     p15, 0, a1, c0, c2, 2
-        TST     a1, #&F000
+        TST     a1, #&FF0000                    ; MultU_instrs OR MultS_instrs
         ORRNE   v5, v5, #CPUFlag_LongMul
 
         MRC     p15, 0, a1, c0, c1, 0
-        TST     a1, #&F000
+        TST     a1, #&F0                        ; State1
         ORRNE   v5, v5, #CPUFlag_Thumb
 
-        MSR     CPSR_f, #Q32_bit
-        MRS     lr, CPSR
-        TST     lr, #Q32_bit
-        ORRNE   v5, v5, #CPUFlag_DSP ; Should we check instruction set attr register 3 for this?
+        MRC     p15, 0, a1, c0, c2, 3
+        TST     a1, #&F                         ; Saturate_instrs
+        ORRNE   v5, v5, #CPUFlag_DSP
 
         MRC     p15, 0, a1, c0, c2, 0
         TST     a1, #&F                         ; Swap_instrs