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Commit 1440f3bb authored by Kevin Bracey's avatar Kevin Bracey
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Wahey! This version gives you a display. 

It says "Abort on data transfer".
parent a89c776b
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Showing with 71 additions and 27 deletions
s/ARM600
View file @ 1440f3bb
......@@ -114,8 +114,8 @@ AbtStack * &02000000
AbtStackSize * 8*1024
ABTSTK * AbtStack + AbtStackSize
]
]
PhysSpace * &80000000 ; Map of MEMC/IOMD physical space (64M/512M in size)
]
; - address for virtual area for StrongARM data cache cleaning (32k, for two 16k areas)
......@@ -2072,7 +2072,9 @@ MemInitTable ; sz, U, C, B, logaddr, (ap, (physaddr))
]
]
[ :LNOT: HAL
MemInitSection PSS, 1, 0, 0, PhysSpace, AP_None, &00000000 ; map of physical space
]
[ ShadowROM
MemInitROMs 2, 1, 1, 1, &FF800000, AP_Read ; ROM
......@@ -3453,12 +3455,30 @@ CheckPage
MOV lr, lr, LSR #10 ; remove domain and U bits
MOV lr, lr, LSL #10
[ HAL
SUB sp, sp, #4
Push "r0-r3,r12"
MOV r0, #0
MOV r1, lr
ADD r2, sp, #5*4
BL RISCOS_AccessPhysicalAddress
MOV lr, r0
Pull "r0-r3,r12"
|
ORR lr, lr, #PhysSpace ; now physical address is converted to a logical one (in physspace)
]
AND r7, r2, #&000FF000 ; extract bits which are to form L2 offset
LDR lr, [lr, r7, LSR #10] ; lr = L2PT entry
ANDS r7, lr, #3 ; 00 => trans.fault, 01 => large page
; 10 => small page, 11 => reserved (fault)
[ HAL
Push "r0-r3,r12,lr"
LDR r0, [sp, #6*4]
BL RISCOS_ReleasePhysicalAddress
Pull "r0-r3,r12,lr"
ADD sp, sp, #4
]
TEQNE r7, #3
BEQ Fault
TEQ r7, #2 ; if small page
......
s/ChangeDyn
View file @ 1440f3bb
......@@ -1184,8 +1184,8 @@ FixedAreasTable ; table of fixed areas (
|
& &03000000, 16*1024*1024 ; I/O + ROM
]
& PhysSpace, 512*1024*1024 ; PhysSpace
[ :LNOT: HAL
& PhysSpace, 512*1024*1024 ; PhysSpace
[ No26bitCode
& AbtStack, AbtStackSize
]
......@@ -2652,14 +2652,29 @@ DoTheGrowPagesSpecified
BEQ %FT76 ; and skip copy and first page move
LDR r0, [r0, lr, LSL #3] ; r0 = log. address for replacement page (NB use logical address to write to, for cache consistency)
[ HAL
SUB sp, sp, #4
Push "r0,r1"
MOV r0, #0
LDR r1, [r8, #8] ; r1 = physical address of src for copy
ADD r2, sp, #8 ; must use physical address, as page may be mapped to nowhere along with others
BL RISCOS_AccessPhysicalAddress
MOV r6, r0 ; r6 = logical address of src for copy
Pull "r0,r1"
|
LDR r6, [r8, #8] ; r6 = physical address of src for copy
ORR r6, r6, #PhysSpace ; must use physical address, as page may be mapped to 01F08000 along with others
ADD lr, r6, r5 ; lr = end src address
]
72
LDMIA r6!, {r2, r3, r4, r7, r9, r10, r11, r12}
STMIA r0!, {r2, r3, r4, r7, r9, r10, r11, r12}
TEQ r6, lr
BNE %BT72
[ HAL
Pull "r0"
BL RISCOS_ReleasePhysicalAddress
]
; now check if page we're replacing is in L2PT, and if so then adjust L1PT entries (4 of these)
......
s/Kernel
View file @ 1440f3bb
......@@ -270,8 +270,10 @@ PhysROM * &00000000 ; and real ROM starts at 0
PhysExtROM * &01000000 ; 2nd ROM bank starts at 16M
]
SAMLength * 512*4 ; SAM length in bytes for 1 bank of VRAM
[ :LNOT: HAL
EASISpacePhys * &08000000
EASISpace * PhysSpace + EASISpacePhys
]
; Manifests
......@@ -529,21 +531,13 @@ SWIReturnWithCallBackFlag * SWIDespatch + {PC}-SVCDespatcher
Pull "r10-r12", EQ
MOVEQS pc, lr
[ HAL
BKPT 2
|
B callback_checking + SVCDespatcher - SWIDespatch
]
! 0,"VSetReturn at ":CC:(:STR:(SWIDespatch + {PC}-SVCDespatcher))
50 TST r12, #Auto_Error_SWI_bit
BNE %BT40
[ HAL
BKPT 2
|
B VSet_GenerateError + SVCDespatcher - SWIDespatch
]
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -575,20 +569,12 @@ SVC * SWIDespatch + {PC}-SVCDespatcher
SVC_CallASWI * SWIDespatch + {PC}-SVCDespatcher ; CallASWI,CallASWIR12 re-entry point
BICS r11, r11, #Auto_Error_SWI_bit
[ HAL
BKPT 2
|
BEQ SWIWriteC + SVCDespatcher - SWIDespatch
]
CMP r11, #OS_WriteI
LDRLO pc, [pc, r11, LSL #2]
[ HAL
BKPT 2
|
B NotMainMOSSwi + SVCDespatcher - SWIDespatch
]
ASSERT {PC}-SVCDespatcher = SWIDespatch_Size
......
s/MemInfo
View file @ 1440f3bb
......@@ -609,8 +609,14 @@ MemoryIOSpace ROUT
SETV
EXIT
[ HAL
! 0, "Sort out OS_Memory 9"
]
controller_types
[ HAL
DCD 0,0,0,0
|
[ IO_Type = "IOMD"
DCD IOMD_Base + IOMD_ECTCR ; Expansion card timing control.
DCD easi_space_table - controller_types
......@@ -637,6 +643,7 @@ easi_space_table
DCD PhysSpace + IOMD_EASI_Base5
DCD PhysSpace + IOMD_EASI_Base6
DCD PhysSpace + IOMD_EASI_Base7
]
]
END
s/NewIRQs
View file @ 1440f3bb
......@@ -120,11 +120,14 @@ Initial_IRQ_Code ROUT
DefaultIRQ1Vcode ROUT
[ HAL
MOV r11, r9 ; r11 trashable - r9 needs to be preserved
Push "r9"
AddressHAL ; modifies r9
MOV r11, r14 ; r11 trashable
CallHAL HAL_IRQSource
ADD r0, r0, r0, LSL #1 ; multiply by 3
MOV r9, r11
Pull "r9"
ADD r1, r0, r0, LSL #1 ; multiply by 3
MOV r14, r11
ADD r1, pc, r1, LSL #2 ; so table contains DevNo * 3
|
[ IO_Type = "IOMD"
MOV r3, #IOC ; base for IOC and IOMD
......@@ -164,12 +167,12 @@ DefaultIRQ1Vcode ROUT
ADRNE r1, IrqReqBDevnos
LDRB r0, [r1, r0] ; pick up offset in device despatcher
] ; IO_Type
] ; HAL
ADD r1, pc, r0, LSL #2 ; so table contains DevNo * 3
] ; HAL
LDMIA r1, {r12, pc}
; ******* IRQ device handlers entered with r0-r3,r11,r12,r14 trashable *******
; r0 = device number (even in old RISC OS!)
; r0 = device number (if HAL)
; r3 -> IOC (not in HAL world, unless IOMD HAL is helpful)
; r12 = what they asked for
; r14 = return address to MOS IRQ exit sequence
......@@ -1243,8 +1246,15 @@ TickOne ROUT
Push r14
[ HAL
MOV r11, r9
AddressHAL
CallHAL HAL_IRQClear
MOV r9, r11
|
MOV R0, #timer0_bit
STRB R0, [R3, #IOCIRQCLRA] ; clear timer 0 interrupt
]
MOV R1, #0
LDR R0, [R1, #MetroGnome]
......
s/NewReset
View file @ 1440f3bb
......@@ -1816,7 +1816,9 @@ furtherpoke_notSA
BEQ SkipHardResetPart2
; HardResetPart2
[ :LNOT: HAL
BL L1L2PTenhancements ; little tricks on cacheability etc for performance
]
BL InitVariables
BL AMBControl_Init ; initialise AMBControl section
BL ModuleInit ; initialise modules
......
s/PMF/i2cutils
View file @ 1440f3bb
......@@ -634,6 +634,7 @@ Write
Pull "R12,sb"
Pull "R0-R4,PC"
20
Pull "R12,sb"
]
......@@ -991,6 +992,7 @@ Read
Pull "R1,R2,PC"
20
Pull "R4, sb"
]
[ E2ROMSupport
......
s/PMF/osinit
View file @ 1440f3bb
......@@ -556,7 +556,7 @@ oldirqowner & IRQ
ReadMachineType Entry "r0-r12"
[ HAL
MOV r2, #4_3333
MOV r2, #4_3330
MOV r1, #0
STRB r2, [r1, #MonitorLeadType]
......
s/vdu/vdupalxx
View file @ 1440f3bb
......@@ -106,10 +106,12 @@ PV_SetDefaultPalette ROUT
LDR r2, [r1, r0, LSL #2] ; offset from r1 to start of table
ADD r0, r0, #1 ; point to next item
LDR r5, [r1, r0, LSL #2] ; offset from r1 to end of table +1
ADDS r2, r2, r1 ; r2 -> start of table
BICMI pc, r2, #&80000000 ; if negative then it's a routine
TST r2, #&80000000 ; if bit 31 set, it's a routine
BIC r2, r2, #&80000000 ; clear that flag
ADD r2, r2, r1 ; r2 -> start of table
MOVNE pc, r2 ; or call routine
BIC r5, r5, #&80000000 ; clear routine flag
ADD r5, r5, r1 ; r5 -> end of table
BIC r5, r5, #&80000000
MOV r0, #0 ; start at palette index 0
MOV r1, #3 ; set both halves
10
......
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