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Commit 0ff2f2dd authored by Ben Avison's avatar Ben Avison
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Kernel updates to support Cortex-A9 CPUs 

Detail:
  hdr.ARMops
    added Cortex_A9
  hdr.HALDevice
    added OMAP4 specific device IDs
  hdr.KernelWS
    changed definition of DefIRQ1Vspace for M_CortexA9
  s.ARMops
    added CortexA9 specific code for enabling L2 cache
    added CPUDesc Cortex_A9
  s.NewIRQs
    added CortexA9 specific definition of MaxInterrupts
  s.NewReset
    added M_CortexA9 options
    line 1444: corrected typo
    line 187: commented out unnecessary operation
Admin:
  Submission from Willi Theiß

Version 5.35, 4.79.2.98.2.50. Tagged as 'Kernel-5_35-4_79_2_98_2_50'
parent 20c93a96
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Showing with 64 additions and 25 deletions
VersionASM
View file @ 0ff2f2dd
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.98.2.49"
Module_Date SETS "22 Aug 2011"
Module_ApplicationDate SETS "22-Aug-11"
Module_MinorVersion SETS "4.79.2.98.2.50"
Module_Date SETS "12 Sep 2011"
Module_ApplicationDate SETS "12-Sep-11"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.98.2.49)"
Module_HelpVersion SETS "5.35 (22 Aug 2011) 4.79.2.98.2.49"
Module_FullVersion SETS "5.35 (4.79.2.98.2.50)"
Module_HelpVersion SETS "5.35 (12 Sep 2011) 4.79.2.98.2.50"
END
VersionNum
View file @ 0ff2f2dd
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.98.2.49
#define Module_Date_CMHG 22 Aug 2011
#define Module_MinorVersion_CMHG 4.79.2.98.2.50
#define Module_Date_CMHG 12 Sep 2011
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.98.2.49"
#define Module_Date "22 Aug 2011"
#define Module_MinorVersion "4.79.2.98.2.50"
#define Module_Date "12 Sep 2011"
#define Module_ApplicationDate "22-Aug-11"
#define Module_ApplicationDate "12-Sep-11"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.98.2.49)"
#define Module_HelpVersion "5.35 (22 Aug 2011) 4.79.2.98.2.49"
#define Module_FullVersion "5.35 (4.79.2.98.2.50)"
#define Module_HelpVersion "5.35 (12 Sep 2011) 4.79.2.98.2.50"
#define Module_LibraryVersionInfo "5:35"
hdr/ARMops
View file @ 0ff2f2dd
......@@ -21,7 +21,9 @@ ARMv5T * 4
ARMv5TE * 5
ARMv5TEJ * 6
ARMv6 * 7
ARMvF * &F ; 'Fancy' ARM that describes its features in the feature registers. Generally this implies ARMv7+, but there are also a few ARMv6 CPUs with this value (e.g. ARM1176JZF-S)
ARMvF * &F ; 'Fancy' ARM that describes its features in the feature registers.
; Generally this implies ARMv7+, but there are also a few ARMv6 CPUs with this value
; (e.g. ARM1176JZF-S)
^ 0
ARM600 # 1
......@@ -41,6 +43,7 @@ ARM922T # 1
X80200 # 1
X80321 # 1
Cortex_A8 # 1
Cortex_A9 # 1
ARM1176JZF_S # 1
ARMunk * 255
......
hdr/HALDevice
View file @ 0ff2f2dd
......@@ -102,31 +102,38 @@ HALDeviceInterconnectBus_L4 * 1 :SHL: 24
^ 0
HALDeviceID_AudC_M5451 # 1
HALDeviceID_AudC_TPS65950 # 1
HALDeviceID_AudC_TWL6040 # 1
^ 0
HALDeviceID_Mixer_STAC9750 # 1
HALDeviceID_Mixer_TPS65950 # 1
HALDeviceID_Mixer_TWL6040 # 1
^ 0
HALDeviceID_DMAC_M1535 # 1
HALDeviceID_DMAC_M5229 # 1
HALDeviceID_DMAC_OMAP3 # 1
HALDeviceID_DMAC_OMAP4 # 1
^ 0
HALDeviceID_DMAB_M1535 # 1
HALDeviceID_DMAB_OMAP3 # 1
HALDeviceID_DMAB_OMAP4 # 1
^ 0
HALDeviceID_DMAL_M5229 # 1
^ 0
HALDeviceID_RTC_TPS65950 # 1
HALDeviceID_RTC_TWL6030 # 1
^ 0
HALDeviceID_CPUClk_OMAP3 # 1
HALDeviceID_CPUClk_OMAP4 # 1
^ 0
HALDeviceID_VDU_OMAP3 # 1
HALDeviceID_VDU_OMAP4 # 1
^ 0
HALDeviceID_EtherNIC_SMSC9221 # 1
......@@ -134,8 +141,9 @@ HALDeviceID_EtherNIC_DM9000 # 1
^ 0
HALDeviceID_GPIO_OMAP3 # 1
HALDeviceID_GPIO_OMAP4 # 1
]
] ; Included_Hdr_HALDevice
OPT OldOpt
END
hdr/KernelWS
View file @ 0ff2f2dd
......@@ -1305,7 +1305,7 @@ DebuggerSpace_Size * &1000
NVRamSize # 1 ; Size of NVRam (E2ROM & CMOS) fitted in 256byte units
NVRamBase # 1 ; Base of NVRam
NVRamSpeed # 1 ; Clock hold time in 0.5s units
NVRamSpeed # 1 ; Clock hold time in 0.5us units
NVRamPageSize # 1 ; Page size for writing (log2)
NVRamWriteSize # 1 ; Size of writable region (256byte units)
......@@ -1897,11 +1897,15 @@ RedirectBuff |#| OscliBuffSize
; 6 interrupts for I/O and sound DMA (this is really IOMD specific, not
; ARM600/700 specific but for the moment it is assumed that they are
; used on the same machines).
[ HAL :LAND: M_CortexA9
DefIRQ1Vspace * 12*160+128
|
[ MorrisSupport
DefIRQ1Vspace * 12*4+12*23+2*256+64 + 7*4+12*16+32+256 ;Morris adds 2 more IRQ registers
|
DefIRQ1Vspace * 12*4+12*23+2*256+64 ; for size checking in MOS
]
] ; HAL :LAND: M_CortexA9
DefaultIRQ1V |#| DefIRQ1Vspace
[ AssemblingArthur :LAND: :DEF: ShowWS
......
s/ARMops
View file @ 0ff2f2dd
......@@ -608,12 +608,25 @@ Analyse_WB_CR7_Lx
ADRL a1, XCBTableWBR ; assume read-allocate WB/WT cache
STR a1, [v6, #MMU_PCBTrans]
; Enable L2 cache. This could probably be moved earlier on in the boot sequence (e.g. when the MMU is turned on), but for now it will go here to reduce the chances of stuff breaking
; Enable L2 cache. This could probably be moved earlier on in the boot sequence
; (e.g. when the MMU is turned on), but for now it will go here to reduce the chances
; of stuff breaking
BL Cache_CleanInvalidateAll_WB_CR7_Lx ; Ensure L2 cache is clean
[ M_CortexA9
; write access to ACTLR is only permitted in Secure Mode
; so we must use smc API calls
STMFD sp!, {a2-a4,v3-v4,ip}
LDR ip, =0x102 ; enable/disable PL310 L2 Cache controller
MOV a1, #1 ; enable
myDSB
DCI 0xE1600070 ; SMC #0
LDMFD sp!, {a2-a4,v3-v4,ip}
|
MRC p15, 0, a1, c1, c0, 1
ORR a1, a1, #2 ; L2EN
MCR p15, 0, a1, c1, c0, 1
] ; M_CortexA9
B %FT90
] ; MEMM_Type = "VMSAv6"
......@@ -622,8 +635,8 @@ Analyse_WB_CR7_Lx
Pull "v1,v2,v5,v6,v7,pc"
; This routine works out the values LINELEN, ASSOCIATIVITY, NSETS and CACHE_SIZE defined in section
; B2.3.3 of the ARMv5 ARM.
; This routine works out the values LINELEN, ASSOCIATIVITY, NSETS and CACHE_SIZE defined
; in section B2.3.3 of the ARMv5 ARM.
EvaluateCache
AND a3, a1, #CT_assoc_mask+CT_M
TEQ a3, #(CT_assoc_0:SHL:CT_assoc_pos)+CT_M
......@@ -698,7 +711,7 @@ $var SETA $var+(CT_M_$sz:SHL:CT_M_pos)
; CPUDesc table for ARMv3-ARMv6
KnownCPUTable
; /------Cache Type register fields-----\
; /------Cache Type register fields-----\
; ID reg Mask Arch Type S Dsz Das Dln Isz Ias Iln
CPUDesc ARM600, &000600, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARM610, &000610, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
......@@ -725,6 +738,7 @@ KnownCPUTable
; The cache size data is ignored for ARMv7.
KnownCPUTable_Fancy
CPUDesc Cortex_A8, &00C080, &00FFF0, ARMvF, WB_CR7_Lx, 1, 16K, 32, 16, 16K, 32, 16
CPUDesc Cortex_A9, &00C090, &00FFF0, ARMvF, WB_CR7_Lx, 1, 32K, 32, 16, 32K, 32, 16
CPUDesc ARM1176JZF_S, &00B760, &00FFF0, ARMv6, WB_CR7_LDa, 1, 16K, 32, 16,16K, 32, 16
DCD -1
......@@ -748,6 +762,7 @@ KnownCPUFlags
DCD CPUFlag_ExtendedPages+CPUFlag_XScale, 0 ; X80200
DCD CPUFlag_XScale, 0 ; X80321
DCD 0, 0 ; Cortex_A8
DCD 0, 0 ; Cortex_A9
DCD 0, 0 ; ARM1176JZF_S
[ MEMM_Type = "VMSAv6"
......@@ -814,7 +829,9 @@ ARM_Analyse_Fancy
B %FT27
25
; ARMv7 format cache type register. This should(!) mean that we have the cache level ID register, and all the other ARMv7 cache registers.
; ARMv7 format cache type register.
; This should(!) mean that we have the cache level ID register,
; and all the other ARMv7 cache registers.
; Do we have a split cache?
MRC p15, 1, a1, c0, c0, 1
......@@ -2293,6 +2310,7 @@ PNameTable
DCW PName_X80200 - PNameTable
DCW PName_X80321 - PNameTable
DCW PName_Cortex_A8 - PNameTable
DCW PName_Cortex_A9 - PNameTable
DCW PName_ARM1176JZF_S - PNameTable
PName_ARM600
......@@ -2327,6 +2345,8 @@ PName_X80321
= "X80321:80321 Processor",0
PName_Cortex_A8
= "CortexA8:Cortex-A8 Processor",0
PName_Cortex_A9
= "CortexA9:Cortex-A9 Processor",0
PName_ARM1176JZF_S
= "ARM1176JZF_S:ARM1176JZF-S Processor",0
ALIGN
......
s/NewIRQs
View file @ 0ff2f2dd
......@@ -214,7 +214,11 @@ DefaultIRQ1Vcode_end
Devices * DefaultIRQ1Vcode_end + 12
NoInterrupt * -1
[ M_CortexA9
MaxInterrupts * 160
|
MaxInterrupts * 96
] ; M_CortexA9
DevicesEnd * Devices + MaxInterrupts * 12
......
s/NewReset
View file @ 0ff2f2dd
......@@ -181,7 +181,7 @@ ConfigureRMA
; R8 = last entry we can use
LDR r6, [r7, #VideoSize] ; find out how many pages in video area
MOV r7, #0
; MOV r7, #0
MOV r6, r6, LSR #12 ; = page number of start of skipped bit
ASSERT SoftCamMapSize = L2PTSize +4
MOV r7, #L2PTSize
......@@ -1066,7 +1066,7 @@ DefaultCMOSTable ; list of non-zero options wanted :
; byte pairs of offset, value
; terminated by offset &FF
= KeyDelCMOS, 32
[ M_CortexA8
[ M_CortexA8 :LOR: M_CortexA9
= FileLangCMOS, 26 ; SCSIFS for OMAP3, etc.
|
= FileLangCMOS, 8 ; ADFS
......@@ -1162,7 +1162,7 @@ DefaultCMOSTable ; list of non-zero options wanted :
]
= AlarmAndTimeCMOS,2_00010000 ; !Alarm autosave on
= FSLockCMOS+5, &EA ; Checksum for no password
[ M_CortexA8
[ M_CortexA8 :LOR: M_CortexA9
= CDROMFSCMOS, &C0 ; drives = 0, buffer size = 256K
|
= CDROMFSCMOS, &C1 ; drives = 1, buffer size = 256K
......@@ -1438,7 +1438,7 @@ losepirqlink
BNE hard_reset_forced
LDR R2, =ZeroPage+PIRQ_Chain
CMP R11, R2
LDR R2, =ZeroPage=PFIQasIRQ_Chain
LDR R2, =ZeroPage+PFIQasIRQ_Chain
MOVEQ R11, R2
CMPNE r11, r2
LDREQ r11, =ZeroPage+CallBack_Vector
......@@ -1469,7 +1469,7 @@ hard_reset
MOV r2, #0 ; indicate normal hard reset
]
hard_reset_forced
LDR R8, =ZeroPage
LDR r8, =ZeroPage
[ DebugForcedReset
STR r2, [r8] ; store to logical address zero
]
......
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