Commit d16ab521 authored by Stewart Brodie's avatar Stewart Brodie
Browse files

Work in progress. Do not use.

Detail:
  Many changes to use the APCS macros for function entry and exit so
    that the code can build for 32-bit environments.  Changes are NOT
    yet complete.
  Makefile rebuilds swis.h header file but only exports it if it has
    changed to avoid unnecessary rebuilding of nearly all C sources
    in a build.
Admin:
  Work in progress.  Do not use.

Version 4.97, 4.12.2.5. Tagged as 'RISC_OSLib-4_97-4_12_2_5'
......@@ -58,6 +58,8 @@ OBJASM = objasm
RM = remove
WIPE = -wipe
DIFF = gnu.diff -df >null:
AFLAGS = -depend !Depend -Stamp -quit
CFLAGS = -c -depend !Depend ${INCLUDES} -DDDE -fK
CPFLAGS = ~cfr~v
......@@ -516,6 +518,13 @@ derived.swis: s.makehswis h.swisheader
${EXP_HDR}.SharedCLib: hdr.SharedCLib
${CP} hdr.SharedCLib $@ ${CPFLAGS}
# The swis.h header is only copied if the file differs from an existing
# exported header. This prevents needless recompilations
CLIB:h.swis: derived.swis
-${DIFF} $@ derived.swis
If "<Sys$ReturnCode>" <> 0 Then ${CP} derived.swis $@ ${CPFLAGS}
# Headers:
CLIB:h.assert: clib.h.assert ; ${CP} clib.h.assert $@ ${CPFLAGS}
CLIB:h.ctype: clib.h.ctype; ${CP} clib.h.ctype $@ ${CPFLAGS}
......@@ -536,7 +545,6 @@ CLIB:h.stdint: clib.h.stdint; ${CP} clib.h.stdint $@ ${CPFLAGS}
CLIB:h.stdio: clib.h.stdio; ${CP} clib.h.stdio $@ ${CPFLAGS}
CLIB:h.stdlib: clib.h.stdlib; ${CP} clib.h.stdlib $@ ${CPFLAGS}
CLIB:h.string: clib.h.string; ${CP} clib.h.string $@ ${CPFLAGS}
CLIB:h.swis: derived.swis; ${CP} derived.swis $@ ${CPFLAGS}
CLIB:h.time: clib.h.time; ${CP} clib.h.time $@ ${CPFLAGS}
CLIB:h.varargs: clib.h.varargs; ${CP} clib.h.varargs $@ ${CPFLAGS}
......@@ -674,6 +682,10 @@ o_rl.poll: rlib.s.poll
${CP} rlib.s.defs rlib.s.asmdefs ${CPFLAGS}
${OBJASM} rlib.s.poll o_rl.poll ${AFLAGS}
o_rl.bastxt: rlib.s.bastxt
${CP} rlib.s.defs rlib.s.asmdefs ${CPFLAGS}
${OBJASM} rlib.s.bastxt o_rl.bastxt ${AFLAGS}
m_o_rl.swi: rlib.s.swi
${CP} rlib.s.defs rlib.s.asmdefs ${CPFLAGS}
${OBJASM} rlib.s.swi m_o_rl.swi ${AFLAGS}
......@@ -682,6 +694,10 @@ m_o_rl.poll: rlib.s.poll
${CP} rlib.s.defs rlib.s.asmdefs ${CPFLAGS}
${OBJASM} rlib.s.poll m_o_rl.poll ${AFLAGS}
m_o_rl.bastxt: rlib.s.baxtxt
${CP} rlib.s.defs rlib.s.asmdefs ${CPFLAGS}
${OBJASM} rlib.s.bastxt m_o_rl.bastxt ${AFLAGS}
rm_o_rl.swi: rlib.s.swi
${CP} rlib.s.rom_defs rlib.s.asmdefs ${CPFLAGS}
${OBJASM} rlib.s.swi rm_o_rl.swi ${AFLAGS} -APCS 3/26bit ${OPTIONS}
......@@ -690,6 +706,10 @@ rm_o_rl.poll: rlib.s.poll
${CP} rlib.s.rom_defs rlib.s.asmdefs ${CPFLAGS}
${OBJASM} rlib.s.poll rm_o_rl.poll ${AFLAGS} -APCS 3/26bit ${OPTIONS}
rm_o_rl.bastxt: rlib.s.bastxt
${CP} rlib.s.rom_defs rlib.s.asmdefs ${CPFLAGS}
${OBJASM} rlib.s.bastxt rm_o_rl.bastxt ${AFLAGS} -APCS 3/26bit ${OPTIONS}
#
# trace separated out to allow defining of TRACE
#
......
......@@ -8,7 +8,7 @@
GBLS Module_FullVersion
Module_MajorVersion SETS "4.97"
Module_Version SETA 497
Module_MinorVersion SETS "4.12.2.4"
Module_Date SETS "10 Nov 1999"
Module_FullVersion SETS "4.97 (4.12.2.4)"
Module_MinorVersion SETS "4.12.2.5"
Module_Date SETS "22 Nov 1999"
Module_FullVersion SETS "4.97 (4.12.2.5)"
END
......@@ -4,12 +4,12 @@
*
*/
#define Module_MajorVersion_CMHG 4.97
#define Module_MinorVersion_CMHG 4.12.2.4
#define Module_Date_CMHG 10 Nov 1999
#define Module_MinorVersion_CMHG 4.12.2.5
#define Module_Date_CMHG 22 Nov 1999
#define Module_MajorVersion "4.97"
#define Module_Version 497
#define Module_MinorVersion "4.12.2.4"
#define Module_Date "10 Nov 1999"
#define Module_MinorVersion "4.12.2.5"
#define Module_Date "22 Nov 1999"
#define Module_FullVersion "4.97 (4.12.2.4)"
#define Module_FullVersion "4.97 (4.12.2.5)"
......@@ -24,6 +24,15 @@
GET s.h_Stack
GET rlib.s.asmdefs
GET Hdr:Wimp
GET Hdr:TaskWindow
GBLL FloatingPointArgsInRegs
FloatingPointArgsInRegs SETL {FALSE}
[ FloatingPointArgsInRegs
! 0, "WARNING: Floating point arguments ARE being passed in FP registers"
]
SIGFPE * 2
SIGILL * 3
SIGINT * 4
......@@ -160,7 +169,7 @@ $Label RFS r1
GET clib.s.h_signal
|_clib_initialise|
STMFD sp!, {r1,r2,r14}
FunctionEntry "r1,r2"
LoadStaticBase ip, a4
MOV r0, #-1 ; read max app space size
SWI XOS_ReadDynamicArea
......@@ -171,13 +180,13 @@ $Label RFS r1
STRB a4, [ip, #O_inSignalHandler]
BL |_armsys_lib_init|
MOV a1, #0
LDMFD sp!, {r1,r2,pc}^
Return "r1,r2"
[ ModeMayBeNonUser
IMPORT |_lib_shutdown|
EXPORT |_clib_finalisemodule|
|_clib_finalisemodule|
STMFD sp!, {a1, r14}
FunctionEntry "a1"
BL |_lib_shutdown|
MOV a1, #0
BL |_exit|
......@@ -187,47 +196,52 @@ $Label RFS r1
MOV r3, #0
STR r3, [r1]
SWI Module
LDMFD sp!, {pc}^
[ {CONFIG}<>26
CLRV VS ; explicitly clear V for 32-bit call case
]
Return
]
EventHandler Keep
CMP a1, #-1
MOVNE a1, #0 ; not interested in events other than escape
MOVNES pc, r14
Return ,LinkNotStacked, NE
STMFD sp!, {a2, r14}
MOV a1, #SIGINT
BL |_signal_real_handler|
LDMFD sp!, {a2, r14}
CMP a1, #0
MOVEQS pc, r14
Return ,LinkNotStacked, EQ
LoadStaticBase ip, a1
LDR a1, [ip, #O__interrupts_off]
CMPS a1, #0
CMP a1, #0
MOV a1, #SIGINT
STMEQFD sp!, {r14}
BLEQ raise
LDMEQFD sp!, {r14}
STRNE a1, [ip, #O__saved_interrupt]
MOV a1, #1 ; we wish to handle it, but not just yet
MOVS pc, r14
BNE %FT01
STMFD sp!, {r14}
BL raise
LDMFD sp!, {r14}
01 MOV a1, #1 ; we wish to handle it, but not just yet
Return ,LinkNotStacked
UnhandledEventHandler Keep
CMP a1, #-1
MOVNE a1, #0 ; not interested in events other than escape
MOVNES pc, r14
Return ,LinkNotStacked, NE
LoadStaticBase ip, a1
LDR a1, [ip, #O__interrupts_off]
CMPS a1, #0
CMP a1, #0
MOV a1, #SIGINT
STMEQFD sp!, {r14}
BLEQ raise
LDMEQFD sp!, {r14}
STRNE a1, [ip, #O__saved_interrupt]
MOV a1, #1 ; we wish to handle it, but not just yet
MOVS pc, r14
BNE %FT02
STMFD sp!, {r14}
BL raise
LDMFD sp!, {r14}
02 MOV a1, #1 ; we wish to handle it, but not just yet
Return ,LinkNotStacked
SignalNumber Keep
; nb required not to disturb a4
......@@ -253,8 +267,29 @@ SignalNumber Keep
CMPNE a3, #Error_WriteFail-Error_ReadFail
MOVEQ a2, #SIGSEGV
MOV a1, a2
MOVS pc, r14
Return ,LinkNotStacked
UncaughtTrapHandler Keep
STMFD sp!, {a2, r14}
MOV a4, a1
BL SignalNumber
LDMFD sp!, {a2, r14}
B RaiseIt
|_raise_stacked_interrupts| ; called by CLIB.
LoadStaticBase ip, a1
MOV a2, #0
STR a2, [ip, #O__interrupts_off]
LDR a1, [ip, #O__saved_interrupt]
CMPS a1, #0
Return ,LinkNotStacked, EQ
STR a2, [ip, #O__saved_interrupt]
B raise
Finalise Keep
; (There'd better be a stack set up).
IMPORT |_lib_shutdown|
B |_lib_shutdown|
TrapHandler Keep
MOV a4, a1
......@@ -265,7 +300,7 @@ TrapHandler Keep
CMP a1, #0
LDMFD sp!, {a1, a2, a4, r14}
MOVEQ a1, #0
MOVEQS pc, r14
Return ,LinkNotStacked, EQ
RaiseIt
LoadStaticBase ip, a3
......@@ -279,27 +314,6 @@ Raised
; signal handler, complain loudly!
UncaughtTrapHandler Keep
STMFD sp!, {a2, r14}
MOV a4, a1
BL SignalNumber
LDMFD sp!, {a2, r14}
B RaiseIt
|_raise_stacked_interrupts| ; called by CLIB.
LoadStaticBase ip, a1
MOV a2, #0
STR a2, [ip, #O__interrupts_off]
LDR a1, [ip, #O__saved_interrupt]
CMPS a1, #0
MOVEQS pc, lr
STR a2, [ip, #O__saved_interrupt]
B raise
Finalise Keep
; (There'd better be a stack set up).
IMPORT |_lib_shutdown|
B |_lib_shutdown|
|x$multiply|
; a1 := a2 * a1.
......@@ -310,7 +324,7 @@ m0loop MOVS a2, a2, LSR #1
ADD a1, a1, a1
BNE m0loop
MOV a1, a3
MOVS pc, lr
Return ,LinkNotStacked
|x$remainder|
B |_kernel_srem|
......@@ -321,7 +335,7 @@ m0loop MOVS a2, a2, LSR #1
|x$divtest|
; test for division by zero (used when division is voided)
CMPS a1, #0
MOVNES pc, lr
Return ,LinkNotStacked, NE
STMFD sp!, {r0}
ADR r0, E_DivideByZero
B |_kernel_fault|
......@@ -339,76 +353,76 @@ m0loop MOVS a2, a2, LSR #1
|__rt_rd1chk|
|_rd1chk|
STMFD sp!, {lr}
CMPS a1, #&8000
FunctionEntry
CMP a1, #&8000
BLT readfail
LoadStaticBase ip, lr
LDR lr, [ip, #O_app_space_end]
CMPS a1, lr ; max app space size now read at initialisation
LDMCCFD sp!, {pc}^
CMP a1, lr ; max app space size now read at initialisation
Return ,,CC
B readfail
|__rt_rd2chk|
|_rd2chk|
STMFD sp!, {lr}
CMPS a1, #&8000
FunctionEntry
CMP a1, #&8000
BLT readfail
TST a1, #1
BNE readfail
LoadStaticBase ip, lr
LDR lr, [ip, #O_app_space_end]
CMPS a1, lr ; max app space size now read at initialisation
LDMCCFD sp!, {pc}^
CMP a1, lr ; max app space size now read at initialisation
Return ,,CC
B readfail
|__rt_rd4chk|
|_rd4chk|
STMFD sp!, {lr}
CMPS a1, #&8000
FunctionEntry
CMP a1, #&8000
BLT readfail
TST a1, #3
BNE readfail
LoadStaticBase ip, lr
LDR lr, [ip, #O_app_space_end]
CMPS a1, lr ; max app space size now read at initialisation
LDMCCFD sp!, {pc}^
CMP a1, lr ; max app space size now read at initialisation
Return ,,CC
B readfail
|__rt_wr1chk|
|_wr1chk|
STMFD sp!, {lr}
CMPS a1, #&8000
FunctionEntry
CMP a1, #&8000
BLT writefail
LoadStaticBase ip, lr
LDR lr, [ip, #O_app_space_end]
CMPS a1, lr ; max app space size now read at initialisation
LDMCCFD sp!, {pc}^
CMP a1, lr ; max app space size now read at initialisation
Return ,,CC
B writefail
|__rt_wr2chk|
|_wr2chk|
STMFD sp!, {lr}
CMPS a1, #&8000
FunctionEntry
CMP a1, #&8000
BLT writefail
TST a1, #1
BNE writefail
LoadStaticBase ip, lr
LDR lr, [ip, #O_app_space_end]
CMPS a1, lr ; max app space size now read at initialisation
LDMCCFD sp!, {pc}^
CMP a1, lr ; max app space size now read at initialisation
Return ,,CC
B writefail
|__rt_wr4chk|
|_wr4chk|
STMFD sp!, {lr}
CMPS a1, #&8000
FunctionEntry
CMP a1, #&8000
BLT writefail
TST a1, #3
BNE writefail
LoadStaticBase ip, lr
LDR lr, [ip, #O_app_space_end]
CMPS a1, lr ; max app space size now read at initialisation
LDMCCFD sp!, {pc}^
CMP a1, lr ; max app space size now read at initialisation
Return ,,CC
; and drop into writefail
writefail
LDMFD sp!, {lr}
......@@ -431,32 +445,35 @@ readfail
& 0
MEND
; Note that the number of instructions is critical for the SUBLT, hence the NOOPs
|_memcpy|
FunctionEntry "v1"
STMFD sp!, {v1, lr}
01 SUBS a3, a3, #16
SUBLT pc, pc, a3, ASL #2
LDMIA a2!, {a4, v1, ip, lr}
STMIA a1!, {a4, v1, ip, lr}
BGT %B01
LDMFD sp!, {v1, pc}^
Return "v1"
NOOP
LDMIA a2!, {a4, v1, ip}
STMIA a1!, {a4, v1, ip}
LDMFD sp!, {v1, pc}^
Return "v1"
NOOP
LDMIA a2!, {a4, v1}
STMIA a1!, {a4, v1}
LDMFD sp!, {v1, pc}^
Return "v1"
NOOP
LDMIA a2!, {a4}
STMIA a1!, {a4}
LDMFD sp!, {v1, pc}^
Return "v1"
; Note that the number of instructions is critical for the SUBLT
|_memset|
STMFD sp!, {lr}
FunctionEntry
MOV a4, a2
MOV ip, a2
MOV lr, a2
......@@ -464,16 +481,16 @@ readfail
SUBLT pc, pc, a3, ASL #1
STMIA a1!, {a2, a4, ip, lr}
BGT %B01
LDMFD sp!, {pc}^
Return
STMIA a1!, {a2, a4, ip}
LDMFD sp!, {pc}^
Return
STMIA a1!, {a2, a4}
LDMFD sp!, {pc}^
Return
STMIA a1!, {a4}
LDMFD sp!, {pc}^
Return
mesg DCB "mesg"
wimp_title
......@@ -492,11 +509,6 @@ n_module_lookup EQU 18
wimp_preinitflag EQU &80000000
zp_wimpdomain EQU &ff8
XWimp_CommandWindow EQU &600ef
XWimp_ReadSysInfo EQU &600f2
XTaskWindow_TaskInfo EQU &63380
IMPORT |_kernel_unwind|
|_postmortem|
; Prepare window manager for output
......@@ -569,8 +581,7 @@ postmortem0
LDMFD sp!, {r0-r5}
LDR a3, mesg
CMP a2, a3
BNE postmortem1
BL |_sys_msg|
BLEQ |_sys_msg| ; BL<cond> 32-bit OK
postmortem1
BL |_kernel_fpavailable|
LDMFD sp!, {r14}
......@@ -602,7 +613,7 @@ postmortem_nofp
CMP a1, #0
BLE %F01
LDR a1, [sp, #4+8*4]
BIC a1, a1, #&FC000003
RemovePSRFromReg a1, a2 ; Remove PSR bits safely if necessary
ADR a2, Raised
CMP a1, a2
BNE %B02
......@@ -645,8 +656,13 @@ postmortem_nofp
B |_kernel_stkovf_split|
|_exit|
[ No32bitCode
TST r14, #3
BLEQ |_kernel_setreturncode|
|
MRS a4, CPSR
TST a4, #2_01111 ; EQ if USR26 or USR32
]
BLEQ |_kernel_setreturncode| ; BL<cond> 32-bit OK
B |_kernel_exit|
......@@ -675,7 +691,7 @@ sj_f7 # 3*4
; veneer does.
MOV a2, lr
MOV ip, sp
TST fp, #APCSChange
TST fp, #APCSChange ; XXXX32
LDRNE lr, [sp]
ADDNE ip, ip, #4
STMIA a1!, {v1-v6, fp, ip} ; save in two steps for calling-standard
......@@ -693,7 +709,7 @@ sj_f7 # 3*4
setjmp_return
MOV lr, v2
LDMIA v1, {v1, v2}
MOVS pc, lr
Return ,LinkNotStacked
|longjmp|
ADD v1, a1, #sj_f4
......@@ -705,7 +721,7 @@ setjmp_return
CMP a1, #0
MOVNE a1, #0
STRNEB a1, [ip, #O_inSignalHandler]
BLNE |_kernel_exittraphandler|
BLNE |_kernel_exittraphandler| ; BL<cond> 32-bit OK
BL |_kernel_fpavailable|
CMP a1, #0
......@@ -730,8 +746,13 @@ longjmp_return
; Previously this code caused a data abort.
; Maybe this code should be conditionalised as it should only apply to the
; shared c library.
[ No32bitCode
MOV a1, pc
TST a1, #3
|
MRS a1, CPSR
TST a1, #2_01111 ; EQ if USR26 or USR32
]
BNE chunks_deallocated
LDR v2, [sl, #SC_next-SC_SLOffset] ; first extension chunk
......@@ -754,13 +775,13 @@ chunks_deallocated
MOV r14, v5
MOV a1, v6
LDMDB v1!, {v1-v6}
TST fp, #APCSChange
TST fp, #APCSChange ; XXXX32
MOVNE r12, sp
MOVNE r13, sl
MOVNE r10, fp
BICNE r10, r10, #APCSChange ; correct fp
MOVS pc, r14
Return ,LinkNotStacked
|_oswrch|
......@@ -781,7 +802,7 @@ chunks_deallocated
LDRNE a1, [sp, #8] ; new value of len
LDMFD sp!, {r14}
ADD sp, sp, #5*4
MOVS pc, r14
Return ,LinkNotStacked
|_osgbpb1|
B |_kernel_osgbpb|
......@@ -796,13 +817,13 @@ chunks_deallocated
B |_kernel_osfind|
|_osfile|
STMFD sp!, {a3, a4}
STMFD sp!, {a3, a4, v1, v2} ; v1,v2 just to reserve space
STMFD sp!, {r14}
ADD a3, sp, #4
BL |_kernel_osfile|
LDMFD sp!, {r14}
ADD sp, sp, #8
MOVS pc, r14
ADD sp, sp, #4*4
Return ,LinkNotStacked
|_osfile1|
B |_kernel_osfile|
......@@ -824,35 +845,50 @@ chunks_deallocated
ADFD f0, f0, #0 ; (round to D format)
ReEnableFPInterrupts
TST r1, #&F
MOVEQS pc, lr
Return ,LinkNotStacked, EQ
TST r1, #&7
BNE ldfp_overflow
B underflow_error
; void _stfp(double d, void *x) stores packed decimal at x
|_stfp| STMFD sp!, {r0, r1}
|_stfp|
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
LDFD f0, [sp], #8
STFP f0, [r2, #0]
MOVS pc, lr
|
STFP f0, [r0, #0]
]
Return ,LinkNotStacked
sin STMFD sp!, {r0, r1}
sin
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
LDFD f0, [sp], #8
]
SIND f0, f0
MOVS pc, lr
Return ,LinkNotStacked
cos STMFD sp!, {r0, r1}
cos
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
LDFD f0, [sp], #8
]
COSD f0, f0
MOVS pc, lr
Return ,LinkNotStacked
exp STMFD sp!, {r0, r1}
exp
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
DisableFPInterrupts
LDFD f0, [sp], #8
|
DisableFPInterrupts
]
EXPD f0, f0
ReEnableFPInterrupts
TST r1, #&0F
MOVEQS pc, lr
Return ,LinkNotStacked, EQ
TST r1, #8
BNE underflow_error
B huge_error
......@@ -867,7 +903,7 @@ huge_negative_result
Set_errno
LoadStaticAddress |__errno|, r1
STR r0, [r1, #0]
MOVS pc, lr
Return ,LinkNotStacked
negative_huge_val
DCD &FFEFFFFF ; put constant where it is easy to find
DCD &FFFFFFFF
......@@ -890,73 +926,105 @@ underflow_error
MVFD f0, #0
B Set_errno
log10 STMFD sp!, {r0, r1}
log10
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
LDFD f0, [sp], #8
]
CMFE f0, #0
BEQ huge_negative_result
BMI negative_error
LOGD f0, f0
MOVS pc, lr
Return ,LinkNotStacked
log STMFD sp!, {r0, r1}
log
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
LDFD f0, [sp], #8
]
CMFE f0, #0
BEQ huge_negative_result
BMI negative_error
LGND f0, f0
MOVS pc, lr
Return ,LinkNotStacked
sqrt STMFD sp!, {r0, r1}
sqrt
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
LDFD f0, [sp], #8
]
CMFE f0, #0
BMI negative_error
SQTD f0, f0
MOVS pc, lr
Return ,LinkNotStacked
tan STMFD sp!, {r0, r1}
tan
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
DisableFPInterrupts
LDFD f0, [sp], #8
|
DisableFPInterrupts
]
TAND f0, f0
ReEnableFPInterrupts
TST r1, #&07
MOVEQS pc, lr
Return ,LinkNotStacked, EQ
B huge_error
atan STMFD sp!, {r0, r1}
atan
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
LDFD f0, [sp], #8
]
ATND f0, f0
MOVS pc, lr
Return ,LinkNotStacked
asin STMFD sp!, {r0, r1}
asin
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
DisableFPInterrupts
LDFD f0, [sp], #8
|
DisableFPInterrupts
]
ASND f0, f0
ReEnableFPInterrupts
; A range error is not possible; any error must be a domain error.
; (And the only plausible error flag is IVO, but I don't check).
; Dunno what result is sensible.
TST r1, #&07
MOVEQS pc, lr
Return ,LinkNotStacked, EQ
B negative_error
acos STMFD sp!, {r0, r1}
acos
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1}
DisableFPInterrupts
LDFD f0, [sp], #8
|
DisableFPInterrupts
]
ACSD f0, f0
ReEnableFPInterrupts
; A range error is not possible; any error must be a domain error.
; (And the only plausible error flag is IVO, but I don't check).
; Dunno what result is sensible.
TST r1, #&07
MOVEQS pc, lr
Return ,LinkNotStacked, EQ
B negative_error
pow STMFD sp!, {r0, r1, r2, r3}
pow
[ :LNOT: FloatingPointArgsInRegs
STMFD sp!, {r0, r1, r2, r3}
DisableFPInterrupts
LDFD f0, [sp], #8
LDFD f1, [sp], #8
|
DisableFPInterrupts
]
CMFE f0, #0
BEQ POWFirstArgZero
POWD f0, f0, f1
......@@ -967,7 +1035,7 @@ pow STMFD sp!, {r0, r1, r2, r3}
; negative, second non-integer).
; (DVZ assumed impossible).
TST r1, #&0F
MOVEQS pc, lr
Return ,LinkNotStacked, EQ
TST r1, #1
BNE negative_error
TST r1, #8
......@@ -978,11 +1046,11 @@ POWFirstArgZero
CMFE f1, #0
MVFEQD f0, #1 ; return 1.0 if both args 0.0
ReEnableFPInterrupts
MOVGES pc, lr
Return ,LinkNotStacked, GE
B negative_error
|_count| ; used when profile option is enabled
BIC lr, lr, #&FC000003 ; remove condition code bits
RemovePSRFromReg lr, ip
LDR ip, [lr, #0]
ADD ip, ip, #1
STR ip, [lr, #0]
......@@ -993,7 +1061,7 @@ POWFirstArgZero
; using extra space to record the position in the file that this
; count-point corresponds to.
|_count1| ; used when profile option is enabled
BIC lr, lr, #&FC000003 ; remove condition code bits
RemovePSRFromReg lr, ip
LDR ip, [lr, #0]
ADD ip, ip, #1
STR ip, [lr, #0]
......
......@@ -196,7 +196,7 @@ LookupError
LDR r0, =|__RelocCode| ; if __RelocCode is present, call it and
TEQ r0, #0 ; note the address of the relocation table
MOVEQ r0, #-1 ; in r8, else just set r8 to -1
BLNE __RelocCode
BLNE __RelocCode ; BL<cond> 32-bit OK
MOV r8, r0
; ]
MOV r4, #0
......
......@@ -143,13 +143,9 @@ uwb_f7 # 3*4
uwb_size # 0
Wimp_ReadSysInfo EQU X+&400f2
Wimp_SlotSize EQU X+&400ec
; Not needed anymore since behaviour under debugger is now identical
;Debugger_BeingDebugged EQU X+&41d41
GET Hdr:Wimp
[ DDE
DDEUtils_GetCLSize EQU X+&42583
DDEUtils_GetCL EQU X+&42584
GET Hdr:DDEUtils
]
MACRO
......@@ -185,7 +181,7 @@ DDEUtils_GetCL EQU X+&42584
[ (:LNOT:SharedLibrary)
MOV pc, a4
|
STMFD sp!, {v6, lr}
FunctionEntry "v6"
LoadStaticBase v6
LDRB ip, [v6, #O_ClientFlags]
TST ip, #ClientFlag_APCS_A
......@@ -201,11 +197,7 @@ movne_sla_sl
movne_sl_sla
MOVNE sl, r13
MOVNE sp, r12
[ {CONFIG}=26
LDMFD sp!, {v6, pc}^
|
LDMFD sp!, {v6, pc}
]
Return "v6"
]
......@@ -222,11 +214,11 @@ movne_sl_sla
STR r0, [ip, #O_allocProc] ; default alloc proc
ADR r0, |_kernel_RMAfree|
STR r0, [ip, #O_freeProc] ; and no dealloc proc
LDMFD sp!, {pc}^
LDMFD sp!, {pc}
|_kernel_irqs_disabled|
ANDS a1, r14, #PSRIBit
ANDS a1, r14, #PSRIBit ; XXXX32
MOVS pc, r14
|_kernel_RMAalloc|
......@@ -367,7 +359,7 @@ movne_sl_sla
WritePSRc 0, r5 ; back to user mode
[ DDE
NOOP
SWI DDEUtils_GetCLSize
SWI XDDEUtils_GetCLSize
MOVVS r0, #0
CMP r0, #0
BEQ %F04
......@@ -380,7 +372,7 @@ movne_sl_sla
MOVCC r2, #' '
STRB r2, [r0], #+1
BCS %B03
SWI DDEUtils_GetCL
SWI XDDEUtils_GetCl
MOV r6, r1
04
|
......@@ -450,7 +442,7 @@ movne_sl_sla
BL InstallHandlers
MOV r0, #0
SWI Wimp_ReadSysInfo
SWI XWimp_ReadSysInfo
MOVVS r0, #0 ; error - presumably Wimp not present
CMP r0, #0
MOVNE r0, #1
......@@ -530,7 +522,7 @@ CopyHandler
LDMFD sp!, {a1}
CMP a1, r14
ADRLT a1, E_Exit
BLLT |_kernel_copyerror|
BLLT |_kernel_copyerror| ; BL<cond> 32-bit OK
LDMIB sp, {r4-r9, fp, sp, pc}^
ALIGN
......@@ -982,7 +974,7 @@ FatalErrorX
SavePSR v4
MOV v4, pc
SWI EnterSVC
BLVC open_messagefile
BLVC open_messagefile ; BL<cond> 32-bit OK
RestPSR v4
MOV r0, r0
ADD r2, v6, #O_fastEventStack
......@@ -1196,7 +1188,7 @@ SetWimpSlot Keep
SWINE ChangeEnv
SUB r0, r4, #Application_Base
MOV r1, #-1
SWI Wimp_SlotSize
SWI XWimp_SlotSize
MOVNE r4, r0
MOVNE r0, #Env_MemoryLimit
MOVNE r1, r5
......@@ -1923,8 +1915,8 @@ duh_corrupt
MOVCS ip, #1
MOVVS ip, #0
STR ip, [lr]
BLVS CopyError
MOVVC a1, #0
BLVS CopyError ; BL<cond> 32-bit OK
LDMDB fp, {v1-v6, fp, sp, pc}^
|
; Set up a proper frame here, so if an error happens (and not X)
......@@ -1952,7 +1944,7 @@ AfterSWI
MOVCS ip, #1
MOVVS ip, #0
STR ip, [lr]
BLVS CopyError
BLVS CopyError ; BL<cond> 32-bit OK
MOVVC a1, #0
LDMDB fp, {v1-v6, fp, sp, pc}^
]
......@@ -1970,8 +1962,8 @@ swi_ret_inst
SWI XOS_CallASWIR12
LDR ip, [sp]
STMIA ip, {r0-r9}
BLVS CopyError
MOVVC a1, #0
BLVS CopyError ; BL<cond> 32-bit OK
LDMIA sp!, {a3, v1-v6, pc}^
|
STMDB sp!, {a3, v1-v6, lr}
......@@ -1985,8 +1977,8 @@ swi_ret_inst
MOV pc, sp
LDR ip, [sp, #8]!
STMIA ip, {r0-r9}
BLVS CopyError
MOVVC a1, #0
BLVS CopyError ; BL<cond> 32-bit OK
LDMIA sp!, {a3, v1-v6, pc}^
]
......@@ -2019,11 +2011,12 @@ swi_ret_inst
|_kernel_oswrch|
STMFD sp!, {v6, r14}
SWI WriteC
SWI XOS_WriteC
ErrorExitV6Stacked
BLVS CopyError
MOVVS a1, #-2
LDMFD sp!, {v6, pc}^
Return "v6",,VC
BL CopyError
MOV a1, #-2
Return "v6"
|_kernel_osbget|
STMFD sp!, {v6, r14}
......@@ -2065,9 +2058,9 @@ ErrorExitV6Stacked
LDMFD sp!, {v6, pc}^
|_kernel_osfind|
STMFD sp!, {v6, r14}
SWI Open
LDMVCFD sp!, {v6, pc}^
FunctionEntry "v6"
SWI XOS_Find
Return "v6",,VC
BVS ErrorExitV6Stacked
|_kernel_osfile|
......@@ -2076,14 +2069,15 @@ ErrorExitV6Stacked
; int start, end;
; } _kernel_osfile_block;
; int _kernel_osfile(int op, const char *name, _kernel_osfile_block *inout);
STMFD sp!, {r4, r5, r6, v6, r14}
FunctionEntry "r4-r6,v6"
MOV r6, a3
LDMIA a3, {r2 - r5}
SWI File
SWI XOS_File
STMIA r6, {r2 - r5}
BLVS CopyError
MOVVS a1, #-2
LDMFD sp!, {r4, r5, r6, v6, pc}^
Return "r4-r6,v6",,VC
BL CopyError
MOV a1, #-2
Return "r4-r6,v6"
|_kernel_osargs|
STMFD sp!, {v6, r14}
......@@ -2093,7 +2087,7 @@ ErrorExitV6Stacked
BVS ErrorExitV6Stacked
CMP ip, #0
MOVNE a1, r2
LDMFD sp!, {v6, pc}^
Return "v6"
|_kernel_oscli|
STMFD sp!, {v6, r14}
......@@ -2233,7 +2227,7 @@ CopyUpDone
LDR r0, [ip, #32] ; the CLI string to execute
ADD r0, r0, r14 ; ... suitably relocated...
SWI CLI:AND::NOT:X ; force non-X variant
SWI OS_CLI ; force non-X variant
B s_Exit
s_UpCallHandler
......@@ -2257,10 +2251,11 @@ s_Exit2
CMP a3, #0
SWINE Exit
MOVS a1, a2
BLNE SetWimpSlot_Save_r4r5 ; set slot size back to value before CLI
LDMNEFD sp!, {r4, r5}
BEQ %FT01
BL SetWimpSlot_Save_r4r5 ; set slot size back to value before CLI
LDMFD sp!, {r4, r5}
SUB sp, sp, v5 ; and relocate sp...
01 SUB sp, sp, v5 ; and relocate sp...
SUB v6, v6, v5 ; ...and the static data ptr
; The following loop copies the image down memory. It avoids overwriting
......@@ -2331,25 +2326,23 @@ CopyErrorString
STRB a3, [a2], #+1
CMP a3, #' '
BCS %B01
MOVS pc, r14
Return ,LinkNotStacked
|_kernel_getenv|
; _kernel_oserror *_kernel_getenv(const char *name, char *buffer, unsigned size);
MOV ip, sp
STMFD sp!, {v1, v2, v6, fp, ip, r14, pc}
SUB fp, ip, #4
FunctionEntry "v1,v2,v6", frame
LoadStaticBase v6, ip
MOV r3, #0
MOV r4, #3
SWI X:OR:ReadVarVal
BLVS CopyError
SWI XOS_ReadVarVal
MOVVC a1, #0
STRVCB a1, [r1, r2]
LDMDB fp, {v1, v2, v6, fp, sp, pc}^
BLVS CopyError ; BL<cond> 32-bit OK
Return "v1,v2,v6", "fpbased"
|_kernel_setenv|
; _kernel_oserror *_kernel_setenv(const char *name, const char *value);
STMFD sp!, {v1, v6, r14}
FunctionEntry "v1,v6"
LoadStaticBase v6, ip
; Apparently, we need to say how long the value string is as well
; as terminating it.
......@@ -2360,10 +2353,10 @@ CopyErrorString
BNE %B01
MOV r3, #0
MOV r4, #0
SWI X:OR:SetVarVal
BLVS CopyError
SWI XOS_SetVarVal
MOVVC a1, #0
LDMFD sp!, {v1, v6, pc}^
BLVS CopyError ; BL<cond> 32-bit OK
Return "v1,v6"
;*-------------------------------------------------------------------*
;* Storage management *
......@@ -2374,7 +2367,7 @@ CopyErrorString
LoadStaticBase ip, a3
ADD ip, ip, #O_allocProc
STMIA ip, {a1, a2}
MOVS pc, r14
MOV pc, r14
|_kernel_register_slotextend|
......@@ -2382,7 +2375,7 @@ CopyErrorString
MOVS a2, a1
LDR a1, [ip, #O_heapExtender]
STRNE a2, [ip, #O_heapExtender]
MOVS pc, r14
Return ,LinkNotStacked
|_kernel_alloc|
; unsigned _kernel_alloc(unsigned minwords, void **block);
......@@ -2528,7 +2521,7 @@ alloc_return_block
MOVGE r0, r2 ; return it above heapTop
STRGE r3, [ip]
MOVLT r0, #0
MOVS pc, r14
Return ,LinkNotStacked
|_kernel_free|
; void free(void *);
......@@ -2537,7 +2530,7 @@ alloc_return_block
; startup procedure.
; I don't think there's much point in providing a real procedure for this;
; if I do, it complicates malloc and alloc above.
MOVS pc, r14
MOV pc, r14
;*-------------------------------------------------------------------*
;* Stack chunk handling *
......@@ -2545,7 +2538,7 @@ alloc_return_block
|_kernel_current_stack_chunk|
SUB a1, sl, #SC_SLOffset
MOVS pc, r14
MOV pc, r14
;*-------------------------------------------------------------------*
;* Stack overflow handling *
......@@ -2923,7 +2916,7 @@ u_shifted0mod8
MOVLS a3, a3, LSR #8
BLS u_loop2
MOV a1, a4
MOVS pc, r14
Return ,LinkNotStacked
; Unsigned remainder of a2 by a1: returns remainder in a1
; Could be faster (at expense in size) by duplicating code for udiv,
......@@ -2933,10 +2926,10 @@ u_shifted0mod8
; so we need to stack our link over the call.
|_kernel_urem|
STMFD sp!, {r14}
FunctionEntry
BL |_kernel_udiv|
MOV a1, a2
LDMFD sp!, {pc}^
Return
; Fast unsigned divide by 10: dividend in a1
; Returns quotient in a1, remainder in a2
......@@ -2962,7 +2955,7 @@ u_shifted0mod8
CMP a2, #10
ADDGE a1, a1, #1
SUBGE a2, a2, #10
MOVS pc, r14
Return ,LinkNotStacked
|_kernel_sdiv|
......@@ -3046,15 +3039,16 @@ s_shifted0mod8
RSBNE a1, a1, #0
TST ip, #&80000000
RSBNE a2, a2, #0
MOVS pc, r14
Return ,LinkNotStacked
; Signed remainder of a2 by a1: returns remainder in a1
|_kernel_srem|
FunctionEntry
STMFD sp!, {r14}
BL |_kernel_sdiv|
MOV a1, a2
LDMFD sp!, {pc}^
Return
; Fast signed divide by 10: dividend in a1
; Returns quotient in a1, remainder in a2
......@@ -3079,7 +3073,7 @@ s_shifted0mod8
CMP a4, #0
RSBMI a1, a1, #0
RSBMI a2, a2, #0
MOVS pc, r14
Return ,LinkNotStacked
dividebyzero
; Dump all registers, then enter the abort code.
......@@ -3089,7 +3083,7 @@ dividebyzero
LoadStaticBase ip, a3
ADD ip, ip, #O_registerDump
STMIA ip, {r0-r13}
BIC r0, r14, #PSRBits
BIC r0, r14, #PSRBits ; XXXX32
SUBS r1, pc, r0
ADRGE r1, |_kernel_udiv|
CMPGE r0, r1
......@@ -3110,16 +3104,6 @@ dividebyzero
STMDB sp!, {r14}
SWI GenerateError
[ 0 = 1
ADD ip, ip, #pc*4
LDMIA ip, {r14}^
SUB ip, ip, #pc*4-4
LDMIA ip, {r1-r13}
TEQP pc, #0
NOOP
SWI GenerateError
]
EXPORT |_kernel_fault|
|_kernel_fault|
; r0 points to an error block;
......@@ -3144,15 +3128,8 @@ dividebyzero
[ SharedLibrary ; Only works with module for the moment
XMessageTrans_OpenFile EQU &61501
XMessageTrans_Lookup EQU &61502
XMessageTrans_CloseFile EQU &61504
XMessageTrans_ErrorLookup EQU &61506
MessageTrans_OpenFile EQU &41501
MessageTrans_Lookup EQU &41502
MessageTrans_CloseFile EQU &41504
MessageTrans_ErrorLookup EQU &41506
GET Hdr:MsgTrans
GET Hdr:ModHand
n_module_claim EQU 6
n_module_lookupname EQU 18
......@@ -3176,7 +3153,7 @@ n_module_lookupname EQU 18
; R0 = Pointer to selected error block (default or from message file)
;
|_kernel_copyerror|
STMDB sp!, {r1-r7, r12, lr}
FunctionEntry "r1-r7,r12"
BL open_messagefile
MOV r2, #0
ADR r4, module_name
......@@ -3184,7 +3161,7 @@ n_module_lookupname EQU 18
MOV r6, #0
MOV r7, #0
SWI XMessageTrans_ErrorLookup
LDMIA sp!, {r1-r7, r12, pc}^
Return "r1-r7,r12"
; Try to get a message from the message file
;
......@@ -3196,7 +3173,7 @@ n_module_lookupname EQU 18
; R0 = Message
;
|_kernel_getmessage|
STMDB sp!, {r0-r7, r12, lr}
FunctionEntry "r0-r7,r12"
BL open_messagefile
MOV r0, r1
[ :DEF:DEFAULT_TEXT
......@@ -3211,7 +3188,7 @@ n_module_lookupname EQU 18
MOV r7, #0
SWI XMessageTrans_Lookup
STRVC r2, [sp]
LDMIA sp!, {r0-r7, r12, pc}^
Return "r0-r7,r12"
message_filename
DCB "SharedCLibrary:Messages", 0
......@@ -3224,40 +3201,40 @@ module_name
; Try to open the message file.
;
open_messagefile
STMDB sp!, {r0, r2-r5, lr}
FunctionEntry "r0,r2-r5"
MOV r5, #0
LDR r1, [r5, #CLibWorkSpace]
CMP r1, #0
LDMNEIA sp!, {r0, r2-r5, pc}
Return "r0,r2-r5",,NE
MOV r0, #Module_Claim
MOV r3, #Module_WorkSpace
SWI Module
LDMVSIA sp!, {r0, r2-r5, pc}^ ; NB R1 = 0
SWI XOS_Module
Return "r0,r2-r5",,VS ; NB R1 = 0
STR r2, [r5, #CLibWorkSpace]
MOV r0, r2
ADR r1, message_filename
MOV r2, #0
SWI XMessageTrans_OpenFile
MOVVC r1, r0
LDMVCIA sp!, {r0, r2-r5, pc}^
Return "r0,r2-r5",,VC
MOV r0, #Module_Free
LDR r2, [r5, #CLibWorkSpace]
SWI Module
SWI XOS_Module
MOV r1, #0
LDMIA sp!, {r0, r2-r5, pc}^
Return "r0,r2-r5"
|
|_kernel_copyerror|
MOVS pc, lr
MOV pc, lr
|_kernel_getmessage|
MOVS pc, lr
MOV pc, lr
]
|__counter|
STMDB sp!, {r0,lr}
FunctionEntry "r0"
LDR r0, =CLibCounter
BL |_kernel_irqs_off| ; Disable IRQs round update.
LDRB lr, [r0]
......@@ -3265,7 +3242,7 @@ open_messagefile
ADD lr, lr, #1
STRB lr, [r0]
BL |_kernel_irqs_on|
LDMIA sp!, {r0,pc}
Return "r0"
END
......@@ -83,7 +83,7 @@ CV_Entries SETL {TRUE}
STR r14, [r10, #-4]
LDR r14, [r13, #SC_prev-SC_SLOffset] ; we've changed stack chunks!
LDR r14, [r14, #SC_veneerStkexLink]
MOVS pc, r14
MOV pc, r14
|_kernel_NoVeneer|
ADR r0, E_NoVeneer
......
......@@ -101,7 +101,8 @@ swix_even_more_tedious
STR r14, [sp, #4] ; stash args ptr
TST r11, #&800 ; use of block parameter input?
BLNE swi_blockhead ; if so, handle it and...
BLNE swi_blockhead ; if so, handle it and... (BL<cond> 32-bit OK)
TST r11, #&800 ; use of block parameter input? (r11 preserved by the call, flags not)
LDRNE r14, [sp, #4] ; ...restore arg ptr
TST r12, #&20000 ; if non X SWI, could be a return value register
......@@ -191,7 +192,7 @@ swi_blockhead1
CMP r11, #&9000
MOVEQ r9, r12
LDMFD sp!, {r10-r12, pc}^ ;must restore flags
LDMFD sp!, {r10-r12, pc} ; no need to restore flags
] ; StrongARM
......@@ -230,7 +231,7 @@ swix0
ORR r5, r5, #&e1000000
ORR r5, r5, #&a00000
ANDS r2, r1, #&800
BLNE BuildBlockInst
BLNE BuildBlockInst ; BL<cond> 32-bit OK
SUB r6, r6, sp
MOV r6, r6, LSR #2
BIC r6, r6, #&ff000000
......@@ -294,7 +295,7 @@ VSetReturn
ADD sp, sp, #2*4
LDMIA sp!, {r4-r9,lr}
ADD sp, sp, #2 * 4
MOVS pc, lr
Return ,LinkNotStacked
[ :LNOT: StrongARM
BuildBlockInst
......@@ -308,7 +309,7 @@ BuildBlockInst1
ADDMI r2, r2, #4
SUBS r4, r4, #1
BNE BuildBlockInst1
MOVS pc, lr
Return ,LinkNotStacked
]
END
; Copyright 1996 Acorn Computers Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
r0 RN 0
r1 RN 1
r2 RN 2
r3 RN 3
r4 RN 4
r5 RN 5
r6 RN 6
r7 RN 7
r8 RN 8
r9 RN 9
r10 RN 10
r11 RN 11
r12 RN 12
sp RN 13
lr RN 14
pc RN 15
GET s.h_StrongA
AREA |C$$code|, CODE, READONLY
EXPORT |_swix|
EXPORT |_swi|
[ StrongARM
; tedious static _swi(x) entry handling, to avoid generating dynamic code, and
; requiring an expensive XOS_SynchroniseCodeAreas
|_swix|
ORR r0, r0, #&20000
TST r1, #&FF0 ; check for use of input regs. 4 to 9, or of block param
BNE swix_even_more_tedious ; if so, do full stuff
STMFD sp!, {r2, r3} ; put 1st two variadic args on stack
STMDB sp!, {r1, r4-r9, lr} ; save stuff
SUB sp, sp, #5*4 ; so we can use tail code common with dynamic version (and room for regs stash)
ADD r14, sp, #(5+8)*4 ; r14 -> input args
MOV r12, r0 ; target SWI code
STR fp, [sp] ; stash fp
MOV r11, r1
TST r11, #&001
LDRNE r0, [r14], #4
TST r11, #&002
LDRNE r1, [r14], #4
TST r11, #&004
LDRNE r2, [r14], #4
TST r11, #&008
LDRNE r3, [r14], #4
STR r14, [sp, #4] ; stash args ptr
SWI XOS_CallASWIR12
LDMIA sp, {fp, ip} ; restore (ip -> args)
B SWIXReturn
swix_even_more_tedious
|_swi|
STMFD sp!, {r2, r3} ; put 1st two variadic args on stack
STMDB sp!, {r1, r4-r9, lr} ; save stuff
SUB sp, sp, #5*4 ; so we can use tail code common with dynamic version (and room for regs stash)
ADD r14, sp, #(5+8)*4 ; r14 -> input args
MOV r12, r0 ; target SWI code
STR fp, [sp] ; stash fp
MOV r11, r1
TST r11, #&001
LDRNE r0, [r14], #4
TST r11, #&002
LDRNE r1, [r14], #4
TST r11, #&004
LDRNE r2, [r14], #4
TST r11, #&008
LDRNE r3, [r14], #4
TST r11, #&010
LDRNE r4, [r14], #4
TST r11, #&020
LDRNE r5, [r14], #4
TST r11, #&040
LDRNE r6, [r14], #4
TST r11, #&080
LDRNE r7, [r14], #4
TST r11, #&100
LDRNE r8, [r14], #4
TST r11, #&200
LDRNE r9, [r14], #4
STR r14, [sp, #4] ; stash args ptr
TST r11, #&800 ; use of block parameter input?
BLNE swi_blockhead ; if so, handle it and...
LDRNE r14, [sp, #4] ; ...restore arg ptr
TST r12, #&20000 ; if non X SWI, could be a return value register
BEQ swi_beyond_a_joke
SWI XOS_CallASWIR12
LDMIA sp, {fp, ip} ; restore (ip -> args)
B SWIXReturn
swi_beyond_a_joke
SWI XOS_CallASWIR12
LDMIA sp, {fp, ip} ; restore (ip -> args)
STR pc, [sp, #4*4]!
LDR lr, [sp, #1*4]
ANDS lr, lr, #&000F0000 ; select return value register
BEQ SWIReturn2
CMP lr, #&00010000
MOVEQ r0, r1
CMP lr, #&00020000
MOVEQ r0, r2
CMP lr, #&00030000
MOVEQ r0, r3
CMP lr, #&00040000
MOVEQ r0, r4
CMP lr, #&00050000
MOVEQ r0, r5
CMP lr, #&00060000
MOVEQ r0, r6
CMP lr, #&00070000
MOVEQ r0, r7
CMP lr, #&00080000
MOVEQ r0, r8
CMP lr, #&00090000
MOVEQ r0, r9
CMP lr, #&000F0000 ; for goodness sake!
LDREQ r0, [sp]
B SWIReturn2
swi_blockhead
STMFD sp!, {r10-r12, lr}
LDR r12, [sp, #(4+1)*4] ; pick up args ptr from stack
;r12 currently -> first output arg, so crank it past them
MOV r10, #6
swi_blockhead1
MOVS r11, r11, ASL #2
ADDCS r12, r12, #4
ADDMI r12, r12, #4
SUBS r10, r10, #1
BNE swi_blockhead1
;now r12 -> parameter block args on stack
LDR r11, [sp,#4]
ANDS r11, r11, #&f000 ;select reg for parameter block pointer
MOVEQ r0, r12
CMP r11, #&1000
MOVEQ r1, r12
CMP r11, #&2000
MOVEQ r2, r12
CMP r11, #&3000
MOVEQ r3, r12
CMP r11, #&4000
MOVEQ r4, r12
CMP r11, #&5000
MOVEQ r5, r12
CMP r11, #&6000
MOVEQ r6, r12
CMP r11, #&7000
MOVEQ r7, r12
CMP r11, #&8000
MOVEQ r8, r12
CMP r11, #&9000
MOVEQ r9, r12
LDMFD sp!, {r10-r12, pc}^ ;must restore flags
] ; StrongARM
[ :LNOT: StrongARM
|_swi|
; Construct a stack frame that looks something like this:
; LDMIA r12!, {r0..rn} ; Or NOP if no input regs
; ADD Rb, R12, #Nout * 4 ; Or NOP if no parameter block
; SWI xxxxxx
; MOV R0, Rn ; Use ADD because Rn is correct bitfield
; B SWIReturn
; saved r4-r11,lr
; saved r1
; saved input values (r2...rn)
STMFD sp!, {r2-r3} ; Save r1 and put 1st two variadic args on stack
STMDB sp!, {r1, r4-r9, lr}
ADR r6, SWIReturn-4
B swix0
|_swix|
ORR r0, r0, #&20000
STMDB sp!, {r2-r3}
STMDB sp!, {r1, r4-r9, lr}
ADR r6, SWIXReturn-4
swix0
ORR r3, r0, #&ef000000 ; Construct SWI instruction
MOV r0, r1, LSL #22 ; Construct LDMIA R12!, {regs} instruction
MOVS r0, r0, LSR #22 ; {regs} = {} (IE no input regs) we must not
ORRNE r0, r0, #&e8000000 ; use an LDMIA R12!, {} instruction as this is an
ORRNE r0, r0, #&00bc0000 ; invalid instruction, we use a suitable NOP instead.
MOV r5, r1, LSR #16
AND r5, r5, #&f
ORR r5, r5, #&e1000000
ORR r5, r5, #&a00000
ANDS r2, r1, #&800
BLNE BuildBlockInst
SUB r6, r6, sp
MOV r6, r6, LSR #2
BIC r6, r6, #&ff000000
ADD r6, r6, #&ea000000
STMDB sp!, {r0,r2,r3,r5,r6}
ADD r12, sp, #(5+8)*4 ; Point R12 at input regs on stack.
MOV pc, sp ; Call routine on stack
SWIReturn
STR pc, [sp, #4*4]!
] ; not StrongARM
SWIReturn2
LDR lr, [sp, #1*4]
MOVS lr, lr, ASL #1 ; Shift out setting C if R0 to be written, N
LDRCS lr, [r12], #4 ; if R1 to be written.
STRCS r0, [lr]
LDRMI lr, [r12], #4
STRMI r1, [lr]
LDR lr, [sp, #1*4]
B ReturnTail
SWIXReturn
STR pc, [sp, #4*4]!
LDR lr, [sp, #1*4]
BVS VSetReturn
MOVS lr, lr, ASL #1 ; Shift out setting C if R0 to be written, N
LDRCS lr, [r12], #4 ; if R1 to be written.
STRCS r0, [lr]
LDRMI lr, [r12], #4
STRMI r1, [lr]
LDR lr, [sp, #1*4]
TST lr, #&f0000
MOVEQ r0, #0
ReturnTail
MOVS lr, lr, ASL #3 ; Shift 2 bits each time for the next 2 regs
LDRCS r1, [r12], #4
STRCS r2, [r1]
LDRMI r1, [r12], #4
STRMI r3, [r1]
AND lr, lr, #&ff000000
MOVS lr, lr, ASL #2
LDRCS r1, [r12], #4
STRCS r4, [r1]
BEQ VSetReturn ; Typically saves 16S - (3S + 1N)
LDRMI r1, [r12], #4
STRMI r5, [r1]
MOVS lr, lr, ASL #2
LDRCS r1, [r12], #4
STRCS r6, [r1]
LDRMI r1, [r12], #4
STRMI r7, [r1]
MOVS lr, lr, ASL #2
LDRCS r1, [r12], #4
STRCS r8, [r1]
LDRMI r1, [r12], #4
STRMI r9, [r1]
MOVS lr, lr, ASL #2
LDRCS r9, [sp]
LDRCS r1, [r12], #4
STRCS r9, [r1]
VSetReturn
ADD sp, sp, #2*4
LDMIA sp!, {r4-r9,lr}
ADD sp, sp, #2 * 4
MOVS pc, lr
[ :LNOT: StrongARM
BuildBlockInst
MOV r4, #6
AND r2, r1, #&f000
ORR r2, r2, #&e2000000
ORR r2, r2, #&008c0000
BuildBlockInst1
MOVS r1, r1, ASL #2
ADDCS r2, r2, #4
ADDMI r2, r2, #4
SUBS r4, r4, #1
BNE BuildBlockInst1
MOVS pc, lr
]
END
......@@ -22,31 +22,10 @@
; * whether or not a line number has ever been specified
; * whether or not a line number was specified for this line
a1 RN 0
a2 RN 1
a3 RN 2
a4 RN 3
v1 RN 4
v2 RN 5
v3 RN 6
v4 RN 7
v5 RN 8
v6 RN 9
sl RN 10
fp RN 11
ip RN 12
sp RN 13
lr RN 14
pc RN 15
f0 FN 0
f1 FN 1
f2 FN 2
f3 FN 3
f4 FN 4
f5 FN 5
f6 FN 6
f7 FN 7
GBLL ModeMayBeNonUser
ModeMayBeNonUser SETL {FALSE}
GET rlib.s.asmdefs
GET s.h_Brazil
AREA |C$$code|, CODE, READONLY
......@@ -223,8 +202,7 @@ store_byte
exit_detok
STR v4, [a4]
LDMFD sp!, {a1-ip,lr}
MOVS pc, lr
Return "a1-ip"
EXPORT bastxt_tokenise
......@@ -255,8 +233,8 @@ bastxt_tokenise
; sl: pointer to BASIC tokeniser address
; fp:
; ip: line number increment
LDR ip, [sp, #0] ; get the increment before we ...
STMFD sp!, {a1-sl, lr} ; stack everything!
LDR ip, [sp] ; get the increment
STMFD sp!, {r0-r11, r14} ; stack everything!
MOV v4, a1 ; preserve the pointers
MOV v5, a2
MOV v6, a3
......@@ -359,7 +337,6 @@ token_check
MOVEQ a1, #&CC
STREQB a1, [a3] ; munge if ELSE
STR v2, [sl] ; return the results
LDMFD sp!, {a1-sl, lr} ; unstack everything!
MOVS pc, lr
Return "r0-r11"
END
......@@ -35,37 +35,12 @@
; 0.2 SKS 22-Nov-88 made SWI Poll use X-form SWI
; ECN 08-May-91 '#ifndefed' out unused ROM functions
a1 RN 0
a2 RN 1
a3 RN 2
a4 RN 3
v1 RN 4
v2 RN 5
v3 RN 6
v4 RN 7
v5 RN 8
v6 RN 9
sl RN 10
fp RN 11
ip RN 12
sp RN 13
lk RN 14
lr RN 14
pc RN 15
f0 FN 0
f1 FN 1
f2 FN 2
f3 FN 3
f4 FN 4
f5 FN 5
f6 FN 6
f7 FN 7
XPoll * (1 :SHL: 17) :OR: &400C7
XPollIdle * (1 :SHL: 17) :OR: &400E1
GET rlib.s.asmdefs
GBLL ModeMayBeNonUser
ModeMayBeNonUser SETL {FALSE}
GET rlib.s.asmdefs
GET s.h_Brazil
GET Hdr:Wimp
AREA |C$$code|, CODE, READONLY
......@@ -78,66 +53,61 @@ XPollIdle * (1 :SHL: 17) :OR: &400E1
; a1 is poll mask, a2 is pointer to event structure
wimp_poll
MOV ip, sp
STMFD sp!, {v1,v2,fp,ip,lk,pc}
SUB fp, ip, #4
FunctionEntry "v1-v2", frame
MOV v2, a1
MOV v1, a2
LDR a1, =poll_preserve_fp
LDR a1, [a1]
CMP a1, #0
BLNE |_kernel_fpavailable|
CMPNE a1, #0
BL |_kernel_fpavailable|
TEQ a1, #0
LDRNE a1, =poll_preserve_fp
LDRNE a1, [a1]
TEQNE a1, #0
BLNE save_fp_state
MOV lk, a1
MOV lr, a1
MOV a1, v2 ; restore mask
ADD a2, v1, #4 ; point at eventstr->data
SWI XPoll
SWI XWimp_Poll
SUB a2, a2, #4 ; point back at eventstr
STR a1, [a2, #0] ; set reason code
MOVVC a1, #0 ; no error
CMP lk, #0
CMP lr, #0
BLNE restore_fp_state
LDMEA fp, {v1,v2,fp,sp,pc}^
Return "v1-v2", "fpbased"
; os_error *wimp_pollidle(wimp_emask mask, wimp_eventstr *result, int earliest)
; a1 mask, a2 eventstr, a3 earliest
EXPORT wimp_pollidle
wimp_pollidle
MOV ip, sp
STMFD sp!, {v1,v2,v3,fp,ip,lk,pc}
SUB fp, ip, #4
FunctionEntry "v1-v3", frame
MOV v2, a1
MOV v1, a2
MOV v3, a3
LDR a1, =poll_preserve_fp
LDR a1, [a1]
CMP a1, #0
BLNE |_kernel_fpavailable|
CMPNE a1, #0
BL |_kernel_fpavailable|
TEQ a1, #0
LDRNE a1, =poll_preserve_fp
LDRNE a1, [a1]
TEQNE a1, #0
BLNE save_fp_state
MOV lk, a1
MOV lr, a1
MOV a1, v2 ; restore mask
ADD a2, v1, #4 ; point at eventstr->data
MOV a3, v3 ; restore time
SWI XPollIdle
SWI XWimp_PollIdle
CMP lk, #0
CMP lr, #0
BLNE restore_fp_state
SUB a2, a2, #4 ; point back at eventstr
STR a1, [a2, #0] ; set reason code
MOVVC a1, #0 ; no error
LDMEA fp, {v1,v2,v3,fp,sp,pc}^
Return "v1-v3", "fpbased"
; Only f4..f7 defined preserved over procedure call
; can corrupt a2-a4
......@@ -151,7 +121,7 @@ save_fp_state
STFE f5, [sp, #1*12]
STFE f6, [sp, #2*12]
STFE f7, [sp, #3*12]
MOVS pc, lr
MOV pc, lr
; v1, v2 trashable
restore_fp_state
......@@ -164,7 +134,7 @@ restore_fp_state
ADD sp, sp, #4*12 ; emulated a lot faster than writeback
LDMFD sp!, {v1}
WFS v1
MOVS pc, lr
MOV pc, lr
[ :LNOT:UROM
EXPORT wimp_save_fp_state_on_poll
......@@ -172,7 +142,7 @@ wimp_save_fp_state_on_poll
LDR a1, =poll_preserve_fp
MOV a2, #1
STR a2, [a1]
MOVS pc, lr
MOV pc, lr
]
[ :LNOT:UROM
......@@ -181,7 +151,7 @@ wimp_corrupt_fp_state_on_poll
LDR a1, =poll_preserve_fp
MOV a2, #0
STR a2, [a1]
MOVS pc, lr
MOV pc, lr
]
LTORG
......
......@@ -42,7 +42,7 @@
names SETL {TRUE}
GBLL ModeMayBeNonUser
ModeMayBeNonUser SETL {TRUE}
ModeMayBeNonUser SETL {FALSE}
GET s.h_Brazil
......@@ -52,41 +52,6 @@ XOS_MASK * &00020000 ; mask to make a swi a RISC OS V-error SWI
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Register names
r0 RN 0
r1 RN 1
r2 RN 2
r3 RN 3
r4 RN 4
r5 RN 5
r6 RN 6
r7 RN 7
r8 RN 8
r9 RN 9
r10 RN 10
r11 RN 11
r12 RN 12
r13 RN 13
r14 RN 14
r15 RN 15
a1 RN 0
a2 RN 1
a3 RN 2
a4 RN 3
v1 RN 4
v2 RN 5
v3 RN 6
v4 RN 7
v5 RN 8
v6 RN 9
sl RN 10
fp RN 11
ip RN 12
sp RN 13
lk RN 14
lr RN 14
pc RN 15
GET rlib.s.asmdefs
;whether to avoid dynamic code for swi veneers
......@@ -135,19 +100,19 @@ StaticSWIVeneer SETL StrongARM :LAND: {TRUE}
|v$codesegment|
[ :LNOT:UROM
bbc_get SWI XOS_MASK :OR: ReadC
MOVVSS pc, lk
ORRCSS a1, a1, #&100 ; SKS
MOVS pc, lk
bbc_get SWI XOS_ReadC
Return ,LinkNotStacked,VS
ORRCS a1, a1, #&100 ; SKS
Return ,LinkNotStacked
]
bbc_vduw
SWI XOS_MASK :OR: WriteC
MOVVSS pc, lk
SWI XOS_WriteC
Return ,LinkNotStacked,VS
MOV a1, a1, LSR #8
bbc_vdu SWI XOS_MASK :OR: WriteC
bbc_vdu SWI XOS_WriteC
MOVVC a1, #0
MOVS pc, lk
Return ,LinkNotStacked
; void os_swi(int swicode, os_regset* /*inout*/);
......@@ -156,7 +121,7 @@ bbc_vdu SWI XOS_MASK :OR: WriteC
os_swi
[ StaticSWIVeneer
STMDB sp!, {v1-v6, lk}
STMDB sp!, {v1-v6, lr}
MOV r12, r0
CMP r1, #0
BEQ os_swi_noregset
......@@ -165,12 +130,12 @@ os_swi
SWI XOS_CallASWIR12
LDMIA sp!, {ip}
STMIA ip, {r0-r9}
LDMIA sp!, {v1-v6, pc}^
Return "v1-v6"
os_swi_noregset
SWI XOS_CallASWIR12
LDMIA sp!, {v1-v6, pc}^
Return "v1-v6"
|
STMDB sp!, {v1-v6, lk}
STMDB sp!, {v1-v6, lr}
ORR a1, a1, #SWI_OP ; make into SWI operation
ADR v1, exit_sequence
LDMIA v1, {v2,v3}
......@@ -182,7 +147,7 @@ os_swi_noregset
; SWI whatever ; <- sp
exit_sequence
STMIA ip, {r0-r9}
LDMIA sp!, {a2-a4, v1-v6, pc}^ ; a2-a4 just to pop stack
Return "a2-a4,v1-v6" ; a2-a4 just to pop stack
]
......@@ -192,7 +157,7 @@ exit_sequence
os_swix
[ StaticSWIVeneer
STMDB sp!, {v1-v6, lk}
STMDB sp!, {v1-v6, lr}
ORR a1, a1, #XOS_MASK ; make a SWI of V-error type
MOV r12, r0
CMP r1, #0
......@@ -203,13 +168,13 @@ os_swix
LDMIA sp!, {ip}
STMIA ip, {r0-r9}
MOVVC a1, #0
LDMIA sp!, {v1-v6, pc}^
Return "v1-v6"
os_swix_noregset
SWI XOS_CallASWIR12
MOVVC a1, #0
LDMIA sp!, {v1-v6, pc}^
Return "v1-v6"
|
STMDB sp!, {v1-v6, lk}
STMDB sp!, {v1-v6, lr}
ORR a1, a1, #XOS_MASK ; make a SWI of V-error type
ORR a1, a1, #SWI_OP ; make into SWI operation
ADR v1, xexit_sequence
......@@ -224,7 +189,7 @@ xexit_sequence
STMIA ip, {r0-r9}
MOVVC a1, #0
ADD sp, sp, #4 * 4
LDMIA sp!, {a3, v1-v6, pc}^
Return "a3,v1-v6"
; a3 is junk (LDM)
; Note: CAN NOT move stack past LDM
; before instruction executes
......@@ -247,22 +212,22 @@ os_swi4
os_swi5
os_swi6
[ StaticSWIVeneer
STMDB sp!, {v1-v6, lk}
STMDB sp!, {v1-v6, lr}
MOV r12, r0
MOV a1, a2
MOV a2, a3
MOV a3, a4
ADD lk, sp, #7*4
LDMIA lk, {a4, v1, v2}
ADD lr, sp, #7*4
LDMIA lr, {a4, v1, v2}
SWI XOS_CallASWIR12
MOVVC a1, #0
LDMIA sp!, {v1-v6, pc}^
Return "v1-v6"
|
STMDB sp!, {v1-v6, lk}
STMDB sp!, {v1-v6, lr}
ORR a1, a1, #SWI_OP
ADR ip, swi6_exit_sequence
LDMIA ip, {ip, lk}
STMDB sp!, {a1, ip, lk}
LDMIA ip, {ip, lr}
STMDB sp!, {a1, ip, lr}
MOV a1, a2
MOV a2, a3
MOV a3, a4
......@@ -271,7 +236,7 @@ os_swi6
MOV pc, sp
swi6_exit_sequence
MOVVC a1, #0
LDMIA sp!, {a2-a4, v1-v6, pc}^
Return "a2-a4,v1-v6"
]
swi_ret_inst
......@@ -281,74 +246,74 @@ os_swix1r
ORR a1, a1, #&20000
os_swi1r
[ StaticSWIVeneer
STMDB sp!, {a3, v1-v6, lk}
STMDB sp!, {a3, v1-v6, lr}
MOV r12, r0
MOV r0, a2
SWI XOS_CallASWIR12
LDR ip, [sp]
LDMVSIA sp!, {a2, v1-v6, pc}^
Return "a2,v1-v6",,VS
TEQ ip, #0
STRNE a1, [ip]
MOV a1, #0
LDMIA sp!, {a2, v1-v6, pc}^
Return "a2,v1-v6"
|
ORR a1, a1, #&ef000000
LDR a2, swi_ret_inst
STMDB sp!, {a1, a2, a3, v1-v6, lk}
STMDB sp!, {a1, a2, a3, v1-v6, lr}
MOV a1, a2
MOV ip, pc
MOV pc, sp
LDR ip, [sp, #8]!
LDMVSIA sp!, {a2, v1-v6, pc}^
Return "a2,v1-v6",,VS
TEQ ip, #0
STRNE a1, [ip]
MOV a1, #0
LDMIA sp!, {a2, v1-v6, pc}^
Return "a2,v1-v6"
]
os_swix2r
ORR a1, a1, #&20000
os_swi2r
[ StaticSWIVeneer
STMDB sp!, {a4, v1-v6, lk}
STMDB sp!, {a4, v1-v6, lr}
MOV r12, r0
MOV a1, a2
MOV a2, a3
SWI XOS_CallASWIR12
LDR ip, [sp]
LDMVSIA sp!, {a2, v1-v6, pc}^
Return "a2,v1-v6",,VS
TEQ ip, #0
STRNE a1, [ip]
LDR ip, [sp, #8 * 4]
TEQ ip, #0
STRNE a2, [ip]
MOV a1, #0
LDMIA sp!, {a2, v1-v6, pc}^
Return "a2,v1-v6"
|
MOV ip, a2
ORR a1, a1, #&ef000000
LDR a2, swi_ret_inst
STMDB sp!, {a1, a2, a4, v1-v6, lk}
STMDB sp!, {a1, a2, a4, v1-v6, lr}
MOV a1, ip
MOV a2, a3
MOV ip, pc
MOV pc, sp
LDR ip, [sp, #8]!
LDMVSIA sp!, {a2, v1-v6, pc}^
Return "a2,v1-v6",,VS
TEQ ip, #0
STRNE a1, [ip]
LDR ip, [sp, #8 * 4]
TEQ ip, #0
STRNE a2, [ip]
MOV a1, #0
LDMIA sp!, {a2, v1-v6, pc}^
Return "a2,v1-v6"
]
os_swix3r
ORR a1, a1, #&20000
os_swi3r
[ StaticSWIVeneer
STMDB sp!, {v1-v6, lk}
STMDB sp!, {v1-v6, lr}
MOV r12, r0
MOV a1, a2
MOV a2, a3
......@@ -356,7 +321,7 @@ os_swi3r
SWI XOS_CallASWIR12
ADD ip, sp, #7 * 4
LDMIA ip, {v1, v2, v3}
LDMVSIA sp!, {v1-v6, pc}^
Return "v1-v6",,VS
TEQ v1, #0
STRNE a1, [v1]
TEQ v2, #0
......@@ -364,12 +329,12 @@ os_swi3r
TEQ v3, #0
STRNE a3, [v3]
MOV a1, #0
LDMIA sp!, {v1-v6, pc}^
Return "v1-v6"
|
MOV ip, a2
ORR a1, a1, #&ef000000
LDR a2, swi_ret_inst
STMDB sp!, {a1, a2, v1-v6, lk}
STMDB sp!, {a1, a2, v1-v6, lr}
MOV a1, ip
MOV a2, a3
MOV a3, a4
......@@ -377,7 +342,7 @@ os_swi3r
MOV pc, sp
ADD ip, sp, #9 * 4
LDMIA ip, {v1, v2, v3}
LDMVSIA sp!, {a2, a3, v1-v6, pc}^
Return "a2,a3,v1-v6",,VS
TEQ v1, #0
STRNE a1, [v1]
TEQ v2, #0
......@@ -385,14 +350,14 @@ os_swi3r
TEQ v3, #0
STRNE a3, [v3]
MOV a1, #0
LDMIA sp!, {a2, a3, v1-v6, pc}^
Return "a2,a3,v1-v6"
]
os_swix4r
ORR a1, a1, #&20000
os_swi4r
[ StaticSWIVeneer
STMDB sp!, {v1-v6, lk}
STMDB sp!, {v1-v6, lr}
MOV r12, r0
MOV a1, a2
MOV a2, a3
......@@ -401,7 +366,7 @@ os_swi4r
SWI XOS_CallASWIR12
ADD ip, sp, #8 * 4
LDMIA ip, {v1-v4}
LDMVSIA sp!, {v1-v6, pc}^
Return "v1-v6",,VS
TEQ v1, #0
STRNE a1, [v1]
TEQ v2, #0
......@@ -411,12 +376,12 @@ os_swi4r
TEQ v4, #0
STRNE a4, [v4]
MOV a1, #0
LDMIA sp!, {v1-v6, pc}^
Return "v1-v6"
|
MOV ip, a2
ORR a1, a1, #&ef000000
LDR a2, swi_ret_inst
STMDB sp!, {a1, a2, v1-v6, lk}
STMDB sp!, {a1, a2, v1-v6, lr}
MOV a1, ip
MOV a2, a3
MOV a3, a4
......@@ -425,7 +390,7 @@ os_swi4r
MOV pc, sp
ADD ip, sp, #10 * 4
LDMIA ip, {v1-v4}
LDMVSIA sp!, {a2, a3, v1-v6, pc}^
Return "a2,a3,v1-v6",,VS
TEQ v1, #0
STRNE a1, [v1]
TEQ v2, #0
......@@ -435,24 +400,24 @@ os_swi4r
TEQ v4, #0
STRNE a4, [v4]
MOV a1, #0
LDMIA sp!, {a2, a3, v1-v6, pc}^
Return "a2,a3v1-v6"
]
os_swix5r
ORR a1, a1, #&20000
os_swi5r
[ StaticSWIVeneer
STMDB sp!, {v1-v6, lk}
STMDB sp!, {v1-v6, lr}
MOV r12, r0
MOV a1, a2
MOV a2, a3
MOV a3, a4
ADD lk, sp, #7 * 4
LDMIA lk, {a4, v1}
ADD lr, sp, #7 * 4
LDMIA lr, {a4, v1}
SWI XOS_CallASWIR12
ADD ip, sp, #9 * 4
LDMIA ip, {v3-v6, ip}
LDMVSIA sp!, {v1-v6, pc}^
Return "v1-v6",,VS
TEQ v3, #0
STRNE a1, [v3]
TEQ v4, #0
......@@ -464,12 +429,12 @@ os_swi5r
TEQ ip, #0
STRNE v1, [ip]
MOV a1, #0
LDMIA sp!, {v1-v6, pc}^
Return "v1-v6"
|
MOV ip, a2
ORR a1, a1, #&ef000000
LDR a2, swi_ret_inst
STMDB sp!, {a1, a2, v1-v6, lk}
STMDB sp!, {a1, a2, v1-v6, lr}
MOV a1, ip
MOV a2, a3
MOV a3, a4
......@@ -479,7 +444,7 @@ os_swi5r
MOV pc, sp
ADD ip, sp, #11 * 4
LDMIA ip, {v3-v6, ip}
LDMVSIA sp!, {a3, a4, v1-v6, pc}^
Return "a3,a4,v1-v6",,VS
TEQ v3, #0
STRNE a1, [v3]
TEQ v4, #0
......@@ -491,24 +456,24 @@ os_swi5r
TEQ ip, #0
STRNE v1, [ip]
MOV a1, #0
LDMIA sp!, {a3, a4, v1-v6, pc}^
Return "a3,a4,v1-v6"
]
os_swix6r
ORR a1, a1, #&20000
os_swi6r
[ StaticSWIVeneer
STMDB sp!, {v1-v6, lk}
STMDB sp!, {v1-v6, lr}
MOV r12, r0
MOV a1, a2
MOV a2, a3
MOV a3, a4
ADD lk, sp, #7 * 4
LDMIA lk, {a4, v1, v2}
ADD lr, sp, #7 * 4
LDMIA lr, {a4, v1, v2}
SWI XOS_CallASWIR12
ADD ip, sp, #10 * 4
LDMIA ip, {v3-v6, ip, lk} ; APCS-R assumption here
LDMVSIA sp!, {v1-v6, pc}^
LDMIA ip, {v3-v6, ip, lr} ; APCS-R assumption here
Return "v1-v6",,VS
TEQ v3, #0
STRNE a1, [v3]
TEQ v4, #0
......@@ -519,15 +484,15 @@ os_swi6r
STRNE a4, [v6]
TEQ ip, #0
STRNE v1, [ip]
TEQ lk, #0
STRNE v2, [lk]
TEQ lr, #0
STRNE v2, [lr]
MOV a1, #0
LDMIA sp!, {v1-v6, pc}^
Return "v1-v6"
|
MOV ip, a2
ORR a1, a1, #&ef000000
LDR a2, swi_ret_inst
STMDB sp!, {a1, a2, v1-v6, lk}
STMDB sp!, {a1, a2, v1-v6, lr}
MOV a1, ip
MOV a2, a3
MOV a3, a4
......@@ -536,8 +501,8 @@ os_swi6r
MOV ip, pc
MOV pc, sp
ADD ip, sp, #12 * 4
LDMIA ip, {v3-v6, ip, lk} ; APCS-R assumption here
LDMVSIA sp!, {a3, a4, v1-v6, pc}^
LDMIA ip, {v3-v6, ip, lr} ; APCS-R assumption here
Return "a3,a4,v1-v6",,VS
TEQ v3, #0
STRNE a1, [v3]
TEQ v4, #0
......@@ -548,38 +513,38 @@ os_swi6r
STRNE a4, [v6]
TEQ ip, #0
STRNE v1, [ip]
TEQ lk, #0
STRNE v2, [lk]
TEQ lr, #0
STRNE v2, [lr]
MOV a1, #0
LDMIA sp!, {a3, a4, v1-v6, pc}^
Return "a3,a4,v1-v6"
]
os_byte
STMDB sp!, {lk}
FunctionEntry
MOV r3, r1
MOV ip, r2
LDR r1, [r1]
LDR r2, [r2]
SWI XOS_MASK + Byte
SWI XOS_Byte
STR r1, [r3]
STR r2, [ip]
MOVVC r0, #0
LDMIA sp!, {pc}^
Return
os_word
MOV ip, lk
SWI XOS_MASK + Word
MOV ip, lr
SWI XOS_Word
MOVVC r0, #0
MOVS pc, ip
Return ,LinkNotStacked,,ip
os_read_var_val
STMDB sp!, {r4, lk}
FunctionEntry "r4"
MOV r3, #0
MOV r4, #3
SWI &20023
SWI XOS_ReadVarVal
MOV r0, #0
STRVSB r0, [r1]
STRVCB r0, [r1, r2]
LDMIA sp!, {r4, pc}^
Return "r4"
END
......@@ -517,7 +517,7 @@ application_finalisation ROUT
MOV fp, #0
TEQ r4, #0
BLNE |_clib_finalisemodule|
BLNE |_clib_finalisemodule| ; BL<cond> 32-bit OK
; Restore the magic stack limit things
Pull "r1,r2"
......
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