Add OS_AbortTrap implementation

This supports all the load/store instructions, including FPA & VFP/NEON.
Most instructions are handled directly via the base version of the
AbortTrap API that was first implemented in RISC OS Select. However, to
properly cope with LDREX/STREX, and future support for prefetch aborts,
the API has been extended to allow the kernel to request that a block of
memory is mapped in with certain permissions. For LDREX/STREX the kernel
will then rewind the PC so that the instruction can be retried directly.

Test code in Dev/AbortTrap exists in order to allow checking of all
major functionality, along with code for building the code in a
softloadable module for easier/quicker testing.

.gitignore

@@ -5,4 +5,5 @@
 /o/
 /rm/
 /s/TokHelpSrc
+**/c/atarm
 kstrip

Dev/AbortTrap/attest_ap,fd1

+REM Copyright (c) 2021, RISC OS Open Ltd
+REM All rights reserved.
+REM
+REM Redistribution and use in source and binary forms, with or without
+REM modification, are permitted provided that the following conditions are met:
+REM     * Redistributions of source code must retain the above copyright
+REM       notice, this list of conditions and the following disclaimer.
+REM     * Redistributions in binary form must reproduce the above copyright
+REM       notice, this list of conditions and the following disclaimer in the
+REM       documentation and/or other materials provided with the distribution.
+REM     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+REM       may be used to endorse or promote products derived from this software
+REM       without specific prior written permission.
+REM
+REM THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+REM AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+REM IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+REM ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+REM LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+REM CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+REM SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+REM INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+REM CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+REM ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+REM POSSIBILITY OF SUCH DAMAGE.
+
+REM Test AbortTrap handling of different access permissions
+REM
+REM It iterates through all AP values, testing that reading & writing
+REM triggers the abort handler correctly (abort handler should only
+REM be called for accesses where the code doesn't have permission to
+REM perform the access directly)
+
+ON ERROR ERROR EXT 0,REPORT$+" at "+STR$(ERL)
+da_size%=3*4096
+SYS "OS_Module",6,,,4096+da_size% TO ,,rma%
+
+swi$="OS_AbortTrap"
+
+FOR pass=0 TO 2 STEP 2
+P%=rma%
+[ OPT pass
+.handler%
+; R0 = flags
+; R1 = buffer
+; R2 = required address
+; R3 = length
+; R12 = param
+STMFD R13!,{R0-R5,R14}
+ADR R4,last_call%
+MRS R5,CPSR
+STMIA R4,{R0-R3,R5,R12}
+AND R0,R0,#15
+CMP R0,#2
+LDMHSFD R13!,{R0-R5,R14}
+MSRHS CPSR_f,#(1<<28)+(1<<29)
+ADRHS R0,bad_reason
+MOVHS PC,LR
+
+ADR R4,buffer%
+LDR R5,da_base_ptr%
+SUB R2,R2,R5
+ADD R2,R2,R4
+TST R0,#1
+EORNE R1,R1,R2 ; R1^R2, R2
+EORNE R2,R2,R1 ; R1^R2, R1
+EORNE R1,R1,R2 ; R2, R1
+.loop%
+SUBS R3,R3,#1
+LDRB R5,[R1],#1
+STRB R5,[R2],#1
+BNE loop%
+LDMFD R13!,{R0-R5,PC}
+
+.bad_reason
+EQUD 0
+EQUS "Bad reason" : EQUB 0
+ALIGN
+
+.writew_svc%
+SWI "OS_EnterOS"
+STR R1,[R0]
+SWI "OS_LeaveOS"
+MOV PC,R14
+
+.readb_svc%
+SWI "OS_EnterOS"
+LDRB R0,[R0]
+SWI "OS_LeaveOS"
+MOV PC,R14
+
+.readw_svc%
+SWI "OS_EnterOS"
+LDR R0,[R0]
+SWI "OS_LeaveOS"
+MOV PC,R14
+
+.read_sctlr%
+SWI "OS_EnterOS"
+MRC CP15,0,R0,C1,C0,0
+SWI "OS_LeaveOS"
+MOV PC,R14
+
+.ldm_usr%
+ADR R1, ldm_buf%
+LDMIA R0,{R2-R3}
+STMIA R1,{R2-R3}
+MOV PC,R14
+
+.stm_usr%
+ADR R1, ldm_buf%
+LDMIA R1,{R2-R3}
+STMIA R0,{R2-R3}
+MOV PC,R14
+
+.ldm_svc%
+SWI "OS_EnterOS"
+ADR R1, ldm_buf%
+LDMIA R0,{R2-R3}
+STMIA R1,{R2-R3}
+SWI "OS_LeaveOS"
+MOV PC,R14
+
+.stm_svc%
+SWI "OS_EnterOS"
+ADR R1, ldm_buf%
+LDMIA R1,{R2-R3}
+STMIA R0,{R2-R3}
+SWI "OS_LeaveOS"
+MOV PC,R14
+
+.last_call%
+.last_R0% EQUD 0
+.last_R1% EQUD 0
+.last_R2% EQUD 0
+.last_R3% EQUD 0
+.last_PSR% EQUD 0
+.last_R12% EQUD 0
+
+.da_base_ptr% EQUD 0
+
+.ldm_buf% EQUD 0 : EQUD 0
+
+.buffer%
+]
+NEXT pass
+
+seed%=-TIME
+PRINT "seed: ";seed%
+A%=RND(seed%)
+
+wp%=RND
+da_num%=0
+at_registered%=FALSE
+
+ON ERROR PRINT REPORT$;" at ";ERL : PROCend(1)
+
+PRINT "handler: ";~handler%
+PRINT "wp: ";~wp%
+
+DIM expected% 8
+
+REM Offsets to test:
+REM
+REM Start of mapped page, middle of mapped page, end of mapped page
+DATA 4096-4,4096+2048,8192-4,-1
+
+ap%=0
+REPEAT
+ SYS "OS_Memory",17,ap% TO ,ap%,permissions%
+ IF ap%=-1 THEN PROCend(0)
+ PROCtestap
+ PROCendtest
+ ap%+=1
+UNTIL FALSE
+
+DEF PROCtestap
+ PRINT "ap ";ap%;" permissions ";~permissions%
+
+ REM Must be readable in SVC mode
+ IF (permissions% AND &20)<>&20 THEN PRINT "Never readable?" : ENDPROC
+
+ REM Create a sparse DA
+ SYS "OS_DynamicArea",0,-1,0,-1,ap%+(1<<7)+(1<<10),da_size%,0,0,"ATTest" TO ,da_num%,,da_base%
+
+ !da_base_ptr%=da_base%
+
+ PRINT "da_base: ";~da_base%
+
+ !last_R0%=0
+ !last_R1%=0
+ !last_R2%=0
+ !last_R3%=0
+ !last_PSR%=0
+ !last_R12%=0
+
+ SYS swi$,0,da_base%,da_base%+da_size%,handler%,wp%
+ at_registered%=TRUE
+
+ REM Map in the middle page. We'll perform accesses which cross from the mapped
+ REM page into the unmapped area around it, to check that page access is
+ REM is checked on a per-page basis instead of sending everything through our
+ REM AbortTrap handler
+ SYS "OS_DynamicArea",9,da_num%,da_base%+4096,4096
+
+ REM Report memory permissions
+ PROCcheckvalid
+
+ REM Fill sparse page with test data (if writable in SVC, else just use whatever's currently there)
+ IF permissions% AND &10 THEN PROCfill(da_base%+4096,4096)
+ REM Fill buffer with test data
+ PROCfill(buffer%,da_size%)
+
+ REM perform the access tests
+ RESTORE
+ READ offset%
+ REPEAT
+  PROCexpected(offset%,8,4)
+  A%=da_base%+offset%
+  CALL ldm_usr%
+  IF expected%!0<>ldm_buf%!0 OR expected%!4<>ldm_buf%!4 THEN PRINT "USR LDM ERROR @ ";~offset%;" expected ";~(expected%!0);" ";~(expected%!4);" actual ";~(ldm_buf%!0);" ";~(ldm_buf%!4) : PROCend(1)
+
+  PROCexpected(offset%,8,32)
+  A%=da_base%+offset%
+  CALL ldm_svc%
+  IF expected%!0<>ldm_buf%!0 OR expected%!4<>ldm_buf%!4 THEN PRINT "SVC LDM ERROR @ ";~offset%;" expected ";~(expected%!0);" ";~(expected%!4);" actual ";~(ldm_buf%!0);" ";~(ldm_buf%!4) : PROCend(1)
+
+  ldm_buf%!0=RND
+  ldm_buf%!4=RND
+  A%=da_base%+offset%
+  CALL stm_usr%
+  PROCexpected(offset%,8,2)
+  REM "expected" and "actual" are reversed here, because we're using FNexpected to read back what's been written to the memory
+  IF expected%!0<>ldm_buf%!0 OR expected%!4<>ldm_buf%!4 THEN PRINT "USR STM ERROR @ ";~offset%;" expected ";~(ldm_buf%!0);" ";~(ldm_buf%!4);" actual ";~(expected%!0);" ";~(expected%!4) : PROCend(1)
+
+  ldm_buf%!0=RND
+  ldm_buf%!4=RND
+  A%=da_base%+offset%
+  CALL stm_svc%
+  PROCexpected(offset%,8,16)
+  REM "expected" and "actual" are reversed here, because we're using FNexpected to read back what's been written to the memory
+  IF expected%!0<>ldm_buf%!0 OR expected%!4<>ldm_buf%!4 THEN PRINT "SVC STM ERROR @ ";~offset%;" expected ";~(ldm_buf%!0);" ";~(ldm_buf%!4);" actual ";~(expected%!0);" ";~(expected%!4) : PROCend(1)
+  READ offset%
+ UNTIL offset%=-1
+ENDPROC
+
+DEF PROCendtest
+ IF at_registered% THEN
+  PROClast
+  at_registered%=FALSE
+  SYS swi$,1,da_base%,da_base%+da_size%,handler%,wp%
+ ENDIF
+ IF da_num%<>0 THEN SYS "OS_DynamicArea",1,da_num% : da_num%=0
+ENDPROC
+
+DEF PROCend(E%)
+ PROCendtest
+ SYS "OS_Module",7,,rma%
+ IF E% THEN ERROR EXT 0,"Failed"
+ PRINT "Success"
+ END
+ENDPROC
+
+DEF PROClast
+ PRINT "last R0 ";~!last_R0%;" R1 ";~!last_R1%;" R2 ";~!last_R2%;" R3 ";~!last_R3%;" PSR ";~!last_PSR%;" R12 ";~!last_R12%
+ENDPROC
+
+DEF PROCfill(base%,len%)
+ WHILE len%>0
+  A%=base%
+  B%=RND
+  CALL writew_svc%
+  base%+=4
+  len%-=4
+ ENDWHILE
+ENDPROC
+
+DEF FNexpected(addr%,access%)
+ IF addr%<da_base% OR addr%>=da_base%+da_size% THEN PRINT "Bad addr ";~addr% : PROCend(1)
+ addr%-=da_base%
+ IF (permissions% AND access%)=access% AND addr%>=4096 AND addr%<8192 THEN A%=da_base%+addr% : =USR readb_svc%
+=buffer%?addr%
+
+DEF PROCcheckvalid
+ PROCcheckpage("Low",0)
+ PROCcheckpage("Mid",4096)
+ PROCcheckpage("High",8192)
+ENDPROC
+
+DEF PROCcheckpage(name$,offset%)
+ LOCAL flags%,access%
+ SYS "OS_ValidateAddress",da_base%+offset%,da_base%+offset%+4096 TO ;flags%
+ SYS "OS_Memory",24,da_base%+offset%,da_base%+offset%+4096 TO ,access%
+ PRINT name$;" valid: ";((NOT flags%) AND 2);" ";~access%
+ENDPROC
+
+DEF PROCexpected(offset%,len%,access%)
+ WHILE len%>0
+  len%-=1
+  expected%?len%=FNexpected(da_base%+offset%+len%,access%)
+ ENDWHILE
+ENDPROC

Dev/AbortTrap/runtests,feb

+| Copyright (c) 2021, RISC OS Open Ltd
+| All rights reserved.
+| 
+| Redistribution and use in source and binary forms, with or without
+| modification, are permitted provided that the following conditions are met: 
+|     * Redistributions of source code must retain the above copyright
+|       notice, this list of conditions and the following disclaimer.
+|     * Redistributions in binary form must reproduce the above copyright
+|       notice, this list of conditions and the following disclaimer in the
+|       documentation and/or other materials provided with the distribution.
+|     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+|       may be used to endorse or promote products derived from this software
+|       without specific prior written permission.
+| 
+| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+| ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+| LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+| CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+| SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+| INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+| CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+| ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+| POSSIBILITY OF SUCH DAMAGE.
+| 
+Repeat Run <obey$dir> -type fd1 -verbose

Dev/AbortTrap/standalone/!Mk,fd7

+| Copyright (c) 2021, RISC OS Open Ltd
+| All rights reserved.
+| 
+| Redistribution and use in source and binary forms, with or without
+| modification, are permitted provided that the following conditions are met: 
+|     * Redistributions of source code must retain the above copyright
+|       notice, this list of conditions and the following disclaimer.
+|     * Redistributions in binary form must reproduce the above copyright
+|       notice, this list of conditions and the following disclaimer in the
+|       documentation and/or other materials provided with the distribution.
+|     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+|       may be used to endorse or promote products derived from this software
+|       without specific prior written permission.
+| 
+| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+| ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+| LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+| CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+| SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+| INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+| CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+| ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+| POSSIBILITY OF SUCH DAMAGE.
+| 
+Dir <Obey$Dir>
+amu_machine standalone

Dev/AbortTrap/standalone/!MkClean,fd7

+| Copyright (c) 2021, RISC OS Open Ltd
+| All rights reserved.
+| 
+| Redistribution and use in source and binary forms, with or without
+| modification, are permitted provided that the following conditions are met: 
+|     * Redistributions of source code must retain the above copyright
+|       notice, this list of conditions and the following disclaimer.
+|     * Redistributions in binary form must reproduce the above copyright
+|       notice, this list of conditions and the following disclaimer in the
+|       documentation and/or other materials provided with the distribution.
+|     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+|       may be used to endorse or promote products derived from this software
+|       without specific prior written permission.
+| 
+| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+| AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+| IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+| ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+| LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+| CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+| SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+| INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+| CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+| ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+| POSSIBILITY OF SUCH DAMAGE.
+| 
+Dir <Obey$Dir>
+amu_machine clean
+stripdepnd

Dev/AbortTrap/standalone/Makefile

+# Copyright (c) 2021, RISC OS Open Ltd
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met: 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+#       may be used to endorse or promote products derived from this software
+#       without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+# 
+# Makefile for standalone AbortTrap implementation
+#
+
+DEBUG ?= FALSE
+
+ifeq ($(DEBUG),TRUE)
+CFLAGS += -DABORTTRAP_DEBUG
+CMHGFLAGS += -DABORTTRAP_DEBUG
+endif
+
+USE_SYNCLIB    ?= TRUE
+
+# It looks like there's a compiler bug that causes inlining to break things
+# (FNldmia_exc test fails in assorted ways)
+# https://www.riscosopen.org/tracker/tickets/517
+CFLAGS += -DABORTTRAP_INLINE=0
+
+COMPONENT       = AbortTrap
+OBJS            = cmodule aborttrap atarm atcontext atinstr aterrors atmem
+CMHGFILE        = modhead
+ASFLAGS        += -PD "USE_SYNCLIB SETL {${USE_SYNCLIB}}"
+ifeq (${USE_SYNCLIB},TRUE)
+CFLAGS	       += -DUSE_SYNCLIB
+LIBS            = ${SYNCLIB}
+endif
+
+CFLAGS         += -ff -wp -wc
+CMHGDEFINES     = -DCOMPONENT=${COMPONENT}
+CMHGDEPENDS     = cmodule
+
+RES_OBJ = # fudge
+
+DECGEN = <Tools$Dir>.Misc.decgen.decgen
+
+# Work out which instructions to include support for; this is just to reduce
+# code size, and doesn't affect the handling of the instructions
+# Note that FPA is only included in IOMD builds
+ABORTTRAP_ACTIONS_ARM = ARMv3 ARMv4 ARMv5TE ARMv6 ARMv6K ARMv6T2 ARMv8 VFP ASIMD
+
+ABORTTRAP_ENCODINGS_ARM = Build:decgen.encodings.ARMv7 \
+                          Build:decgen.encodings.ARMv7_ASIMD \
+                          Build:decgen.encodings.ARMv7_VFP \
+                          Build:decgen.encodings.ARMv8_AArch32 \
+                          Build:decgen.encodings.FPA
+
+ifneq (,$(findstring $(MACHINE),IOMD))
+ABORTTRAP_ACTIONS_ARM = ARMv3 ARMv4 FPA
+endif
+ifneq (,$(findstring $(MACHINE),Tungsten))
+ABORTTRAP_ACTIONS_ARM = ARMv3 ARMv4 ARMv5TE
+endif
+ifneq (,$(findstring $(MACHINE),ARM11ZF))
+ABORTTRAP_ACTIONS_ARM = ARMv3 ARMv4 ARMv5TE ARMv6 ARMv6K VFP
+endif
+ifneq (,$(findstring $(MACHINE),CortexA7 CortexA8 CortexA9))
+ABORTTRAP_ACTIONS_ARM = ARMv3 ARMv4 ARMv5TE ARMv6 ARMv6K ARMv6T2 VFP ASIMD
+endif
+
+ABORTTRAP_ACTIONS = ${ABORTTRAP_ACTIONS_ARM}
+
+CFLAGS += $(addprefix -DABORTTRAP_,${ABORTTRAP_ACTIONS})
+
+include StdTools
+include ModStdRule
+include ModuleLibs
+include DbgRules
+include CModule
+
+dirs ::
+	${MKDIR} h
+
+clean ::
+        @IfThere c.atarm     Then delete c.atarm
+
+ABORTTRAP_ARM_DEPS = $(addprefix ^.^.^.aborttrap.actions.,${ABORTTRAP_ACTIONS_ARM})
+
+c.atarm: $(ABORTTRAP_ARM_DEPS) c.atpre $(ABORTTRAP_ENCODINGS_ARM)
+        $(DECGEN) -bits=32 -e "-DCDP={ne(coproc,1)}" "-DLDC_STC={ne(coproc,1)}{ne(coproc,2)}" "-DMRC_MCR={ne(coproc,1)}" -DVFP1=(cond:4) "-DVFP2={ne(cond,15)}" -DAS1(X)=1111001[X] -DAS2=11110100 -DAS3=(cond:4)1110 "-DAS4={ne(cond,15)}" "-DCC={ne(cond,15)}" $(ABORTTRAP_ENCODINGS_ARM) -valid -a $(addprefix ../../../aborttrap/actions/,${ABORTTRAP_ACTIONS_ARM}) -default=DEFAULT -o atarm.c -name=aborttrap_arm -pre atpre.c
+
+o.atarm: c.atarm
+	${CC} ${CFLAGS} -o $@ c.atarm
+
+od.atarm: c.atarm
+	${CC} $(filter-out ${C_NO_FNAMES},${CFLAGS}) ${CDFLAGS} -o $@ c.atarm
+
+# Dynamic dependencies:

Dev/AbortTrap/standalone/c/aborttrap

+/*
+ * Copyright (c) 2021, RISC OS Open Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+ *       may be used to endorse or promote products derived from this software
+ *       without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "../../../aborttrap/aborttrap.c"

Dev/AbortTrap/standalone/c/aterrors

+/*
+ * Copyright (c) 2021, RISC OS Open Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+ *       may be used to endorse or promote products derived from this software
+ *       without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "../../../aborttrap/aterrors.c"

Dev/AbortTrap/standalone/c/atinstr

+/*
+ * Copyright (c) 2021, RISC OS Open Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+ *       may be used to endorse or promote products derived from this software
+ *       without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "../../../aborttrap/atinstr.c"

Dev/AbortTrap/standalone/c/atmem

+/*
+ * Copyright (c) 2021, RISC OS Open Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+ *       may be used to endorse or promote products derived from this software
+ *       without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "../../../aborttrap/atmem.c"

Dev/AbortTrap/standalone/c/atpre

+/*
+ * Copyright (c) 2021, RISC OS Open Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+ *       may be used to endorse or promote products derived from this software
+ *       without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "../../../aborttrap/atpre.c"
+
+/* Generated code will appear here */

Dev/AbortTrap/standalone/c/cmodule

+/*
+ * Copyright (c) 2021, RISC OS Open Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met: 
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+ *       may be used to endorse or promote products derived from this software
+ *       without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "modhead.h"
+#include "swis.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stddef.h>
+
+#include "Global/RISCOS.h"
+#include "Global/Services.h"
+#include "Global/HALDevice.h"
+#include "Global/HALEntries.h"
+#include "Global/NewErrors.h"
+
+#ifdef USE_SYNCLIB
+#include "SyncLib/synclib.h"
+#endif
+
+#include "../../../aborttrap/aborttrap.h"
+#include "../../../aborttrap/aterrors.h"
+#include "../../../kerneliface.h"
+
+extern void veneer(void);
+extern void veneer_config(void *pw,int old_handler);
+static int old_handler;
+
+void *kalloc(size_t size,_kernel_oserror **e)
+{
+	/* A generic error should be sufficient */
+	static _kernel_oserror err = {0,"malloc failed"};
+	void *p = malloc(size);
+	if (!p)
+		*e = &err;
+	return p;
+}
+
+_kernel_oserror const ErrorBlock_BadParameters = {ErrorNumber_BadParameters,"Bad parameters"};
+
+_kernel_oserror *TranslateError(_kernel_oserror const *e)
+{
+	/* We don't care about translating errors */
+	return (_kernel_oserror *) e;
+}
+
+_kernel_oserror* module_init(const char *cmd_tail, int podule_base, void *pw)
+{
+	_kernel_oserror* e = 0;
+
+#ifdef USE_SYNCLIB
+	synclib_init();
+#endif
+
+	aborttrap_init();
+
+	/* Register handler */
+	_kernel_irqs_off();
+	e = _swix(OS_ClaimProcessorVector,_INR(0,1)|_OUT(1),0x104,veneer,&old_handler);
+	if (!e)
+		veneer_config(*((void **)pw),old_handler);
+	_kernel_irqs_on();
+	if (e)
+		goto error;
+    
+	return 0;
+
+error:
+	return e;
+}
+
+_kernel_oserror *module_final(int fatal, int podule, void *pw)
+{
+	_kernel_oserror* e = 0;
+
+	e = _swix(OS_ClaimProcessorVector, _INR(0,2), 0x4,old_handler,veneer);
+	if(e)
+		return e;
+
+	return NULL;
+}
+
+#ifdef ABORTTRAP_DEBUG
+logentry logbuf[LOG_SIZE];
+uint32_t logidx;
+
+_kernel_oserror *module_commands(const char *arg_string, int argc, int cmd_no, void *pw)
+{
+	switch (cmd_no) {
+	case CMD_AbortTrapLog:
+		{
+		uint32_t base = logidx;
+		printf("Address   Opcode    PSR       Result      Disassembly/location\n");
+		for(uint32_t offset=0;offset<LOG_SIZE;offset++)
+		{
+			logentry *l = &logbuf[(base+offset)&(LOG_SIZE-1)];
+			if(l->pc != 0)
+			{
+				/* Disassemble */
+				printf("%08X: %08X: %08X: ",l->pc,l->opcode,l->psr);
+				switch((int)l->result)
+				{
+				case (int) aborttrap_ERROR_UNHANDLED: printf("UNHANDLED  "); break;
+				default: printf("%08x   ",l->result->errnum); break;
+				case 0: printf("CONTINUE   "); break;
+				}
+				char *temp=0;
+				switch(l->psr & PSR_ISET)
+				{
+				case PSR_ISET_ARM:
+					_swix(Debugger_Disassemble,_INR(0,1)|_OUT(1),l->opcode,l->pc,&temp);
+					break;
+				case PSR_ISET_THUMB:
+				case PSR_ISET_THUMBEE: /* Not good! */
+					_swix(Debugger_DisassembleThumb,_INR(0,1)|_OUT(1),l->opcode,l->pc,&temp);
+					break;
+				}
+				if(temp)
+				{
+					int len = strlen(temp);
+					puts(temp);
+					do {
+						putchar(' ');
+					} while(len++<40);
+				}
+				/* Work out where it was */
+				if((l->pc >= 0x8000) && (l->pc < 512<<20))
+				{
+					printf("Application space");
+				}
+				else
+				{
+					/* Check modules */
+					int mod=0,inst=0;
+					uint32_t base;
+					uint32_t bestbase=0;
+					while(!_swix(OS_Module,_INR(0,2)|_OUTR(1,3),12,mod,inst,&mod,&inst,&base))
+					{
+						if(!inst)
+						{
+							if(l->pc-base <= ((uint32_t *)bestbase)[-1])
+								bestbase = base;
+						}
+					}
+					if(bestbase)
+					{
+						printf("Module '%s' (%08X offset %08X)\n",(char *)(bestbase+((uint32_t *)bestbase)[4]),bestbase,l->pc-bestbase);
+					}
+					else
+					{
+						printf("Unknown location\n");
+					}
+				}
+			}
+		}
+		memset(logbuf,0,sizeof(logbuf));
+		}
+		break;
+	case CMD_AbortTrapHandlers:
+		aborttrap_list_handlers();
+		break;
+	}
+	return 0;
+}
+#endif
+
+_kernel_oserror *module_swihandler(int swi_offset, _kernel_swi_regs *r, void *pw)
+{
+	switch (swi_offset)
+	{
+	case AbortTrap_AbortTrap-AbortTrap_00:
+		return aborttrap_swi(r->r[0],r->r[1],r->r[2],r->r[3],r->r[4]);
+	default:
+		return error_BAD_SWI;
+	}
+}

Dev/AbortTrap/standalone/cmhg/modhead

+; Copyright (c) 2021, RISC OS Open Ltd
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met: 
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+;       may be used to endorse or promote products derived from this software
+;       without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; 
+#include "Global/RISCOS.h"
+#include "Global/Services.h"
+
+initialisation-code:	module_init
+
+finalisation-code:	module_final
+
+title-string:		COMPONENT
+
+help-string:		COMPONENT     0.01
+
+date-string:		24 Jun 2021
+
+#ifdef ABORTTRAP_DEBUG
+command-keyword-table:	module_commands
+AbortTrapLog(min-args:0, max-args:0,
+             help-text: "*AbortTrapLog dumps the contents of the log buffer\n",
+             add-syntax:, invalid-syntax: "Syntax: *AbortTrapLog"),
+AbortTrapHandlers(min-args:0, max-args:0,
+             help-text: "*AbortTrapHandlers lists the details of the installed handlers\n",
+             add-syntax:, invalid-syntax: "Syntax: *AbortTrapHandlers")
+#endif
+
+; Just a random unallocated user application SWI chunk
+swi-chunk-base-number: 0xcf000
+
+swi-handler-code: module_swihandler
+
+swi-decoding-table: AbortTrap AbortTrap

Dev/AbortTrap/standalone/s/atcontext

+; Copyright (c) 2021, RISC OS Open Ltd
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+;       may be used to endorse or promote products derived from this software
+;       without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+;
+
+        GBLL    standalone
+standalone SETL {TRUE}
+
+        GET     ../../../aborttrap/atcontext.s
+
+; Veneer for ABT vector
+        GET     ../../../Copro15ops.hdr
+        EXPORT  veneer
+veneer ROUT
+        SUB     sp, sp, #abtcontext_SPSR_svc
+        STMIA   sp, {r0-r12}
+        ADD     r0, sp, #abtcontext_SPSR
+        ADD     r1, sp, #abtcontext_SPSR_svc
+        STMDB   r0, {r1,r14}
+        MRS     r1, SPSR
+        ARM_read_FAR r2
+        ARM_read_FSR r3
+        STMIA   r0,{r1-r3}
+        MOV     r0, sp
+        LDR     r12, ws_ptr
+        BL      aborttrap_dataabort_veneer
+        CMP     r0, #0
+        LDREQ   r4, [sp, #abtcontext_SPSR]
+        MSREQ   SPSR_cxsf, r4
+        LDMEQIA sp, {r0-r13,r15}^         ; The recovered R13 should discard the everything else from the stack
+        ADD     r0, sp, #abtcontext_SPSR
+        LDMIA   r0, {r1-r3}
+        MSR     SPSR_cxsf, r1
+        ARM_write_FAR r2
+        ARM_write_FSR r3
+        LDMIA   sp, {r0-r14}
+        LDR     pc, old_handler
+
+        EXPORT  veneer_config
+veneer_config
+        STR     r0, ws_ptr
+        STR     r1, old_handler
+        MOV     pc, lr
+
+ws_ptr
+        DCD     0
+old_handler
+        DCD     0
+
+        END

Makefile

@@ -24,11 +24,19 @@ else
 C_EXP_HDR       = <cexport$dir>.Global.h
 endif
 
+# Keep SyncLib out of the kernel for now:
+# 1. We're cheating a bit by using an app build of SyncLib, which means the few
+#    C bits will be performing stack limit checking & extension
+# 2. We don't have a way of unlocking mutexes/spinlocks when recovering from
+#    aborts
+USE_SYNCLIB    ?= FALSE
+
 TOKHELPSRC      = ${TOKENSOURCE}
 HELPSRC         = HelpStrs
-ROM_OBJECTS     = GetAll.o
+OBJS            = GetAll
 KERNEL_MODULE   = bin${SEP}${COMPONENT}
-ASFLAGS        += -PD "FreezeDevRel SETL {${FREEZE_DEV_REL}}"
+ASFLAGS        += -PD "FreezeDevRel SETL {${FREEZE_DEV_REL}}" -PD "USE_SYNCLIB SETL {${USE_SYNCLIB}}"
+CFLAGS         += -ff -APCS 3/32bit/nofp/noswst -DKERNEL
 CUSTOMROM       = custom
 CUSTOMEXP       = custom
 CUSTOMSA        = custom
@@ -60,16 +68,79 @@ EXPORTS         = ${EXP_HDR}.AMBControl \
                   ${C_EXP_HDR}.Variables \
                   ${C_EXP_HDR}.VduExt \
                   ${C_EXP_HDR}.VIDCList
+ifeq (${USE_SYNCLIB},TRUE)
+CFLAGS	       += -DUSE_SYNCLIB
+LIBS            = ${SYNCLIB}
+endif
+
+#
+# AbortTrap:
+#
+VPATH += aborttrap
+OBJS += aborttrap atarm atcontext atinstr aterrors atmem
+
+DECGEN = <Tools$Dir>.Misc.decgen.decgen
+
+# Work out which instructions to include support for; this is just to reduce
+# code size, and doesn't affect the handling of the instructions
+# Note that FPA is only included in IOMD builds
+ABORTTRAP_ACTIONS_ARM = ARMv3 ARMv4 ARMv5TE ARMv6 ARMv6K ARMv6T2 ARMv8 VFP ASIMD
+
+ABORTTRAP_ENCODINGS_ARM = Build:decgen.encodings.ARMv7 \
+                          Build:decgen.encodings.ARMv7_ASIMD \
+                          Build:decgen.encodings.ARMv7_VFP \
+                          Build:decgen.encodings.ARMv8_AArch32 \
+                          Build:decgen.encodings.FPA
+
+ifneq (,$(findstring $(MACHINE),IOMD))
+ABORTTRAP_ACTIONS_ARM = ARMv3 ARMv4 FPA
+endif
+ifneq (,$(findstring $(MACHINE),Tungsten))
+ABORTTRAP_ACTIONS_ARM = ARMv3 ARMv4 ARMv5TE
+endif
+ifneq (,$(findstring $(MACHINE),ARM11ZF))
+ABORTTRAP_ACTIONS_ARM = ARMv3 ARMv4 ARMv5TE ARMv6 ARMv6K VFP
+endif
+ifneq (,$(findstring $(MACHINE),CortexA7 CortexA8 CortexA9))
+ABORTTRAP_ACTIONS_ARM = ARMv3 ARMv4 ARMv5TE ARMv6 ARMv6K ARMv6T2 VFP ASIMD
+endif
+
+ABORTTRAP_ACTIONS = ${ABORTTRAP_ACTIONS_ARM}
+
+CFLAGS += $(addprefix -DABORTTRAP_,${ABORTTRAP_ACTIONS})
 
 include StdTools
 include AAsmModule
 include StdRules
+ifeq (${USE_SYNCLIB},TRUE)
+include AppLibs
+endif
 
 # Override this to "TRUE" in the components file if
 # you want an odd-numbered (development) build to be
 # a 'freezable' build - e.g. with no ROM debug output
 FREEZE_DEV_REL ?= FALSE
 
+ROM_OBJECTS = $(addsuffix .o,${OBJS})
+
+#
+# AbortTrap:
+#
+
+clean ::
+        @IfThere aborttrap.c.atarm     Then delete aborttrap.c.atarm
+
+ABORTTRAP_ARM_DEPS = $(addprefix aborttrap.actions.,${ABORTTRAP_ACTIONS_ARM})
+
+aborttrap.c.atarm: $(ABORTTRAP_ARM_DEPS) aborttrap.c.atpre $(ABORTTRAP_ENCODINGS_ARM)
+        $(DECGEN) -bits=32 -e "-DCDP={ne(coproc,1)}" "-DLDC_STC={ne(coproc,1)}{ne(coproc,2)}" "-DMRC_MCR={ne(coproc,1)}" -DVFP1=(cond:4) "-DVFP2={ne(cond,15)}" -DAS1(X)=1111001[X] -DAS2=11110100 -DAS3=(cond:4)1110 "-DAS4={ne(cond,15)}" "-DCC={ne(cond,15)}" $(ABORTTRAP_ENCODINGS_ARM) -valid -a $(addprefix aborttrap/actions/,${ABORTTRAP_ACTIONS_ARM}) -default=DEFAULT -o aborttrap/atarm.c -name=aborttrap_arm -pre aborttrap/atpre.c
+
+o.atarm: aborttrap.c.atarm
+	${CC} ${CFLAGS} -o $@ aborttrap.c.atarm
+
+od.atarm: aborttrap.c.atarm
+	${CC} $(filter-out ${C_NO_FNAMES},${CFLAGS}) ${CDFLAGS} -o $@ aborttrap.c.atarm
+
 #
 # Custom ROM:
 #

aborttrap/actions/ARMv3

+# Copyright (c) 2021, RISC OS Open Ltd
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met: 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+#       may be used to endorse or promote products derived from this software
+#       without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+# 
+
+DEFAULT()
+{
+	return aborttrap_ERROR_UNHANDLED;
+}
+
+# A8.6.53 LDM/LDMIA/LDMFD
+LDMIA_A1(Rn,W,reglist)
+{
+	return aborttrap_LDMIA(ctx,Rn,reglist,W);
+}
+
+# A8.6.54 LDMDA/FA
+LDMDA_A1(Rn,W,reglist)
+{
+	return aborttrap_LDMDA(ctx,Rn,reglist,W);
+}
+
+# A8.6.55 LDMDB/EA
+LDMDB_A1(Rn,W,reglist)
+{
+	return aborttrap_LDMDB(ctx,Rn,reglist,W);
+}
+
+# A8.6.56 LDMIB/ED
+LDMIB_A1(Rn,W,reglist)
+{
+	return aborttrap_LDMIB(ctx,Rn,reglist,W);
+}
+
+# A8.6.58 LDR (immediate, ARM)
+LDR_imm_A1(Rt,Rn,imm12,P,U,W)
+{
+	return aborttrap_LDR_imm(ctx,Rt,Rn,imm12,P,U,!P || W);
+}
+
+# A8.6.59 LDR (literal)
+LDR_lit_A1(Rt,imm12,U,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDR_lit(ctx,Rt,imm12,U);
+}
+
+# A8.6.60 LDR (register)
+LDR_reg_A1(Rt,Rn,imm5,type,Rm,P,U,W)
+{
+	eshift shift_t;
+	uint32_t shift_n;
+	decodeimmshift(type,imm5,&shift_t,&shift_n);
+	return aborttrap_LDR_reg(ctx,Rt,Rn,Rm,P,U,!P || W,shift_t,shift_n);
+}
+
+# A8.6.62 LDRB (immediate, ARM)
+LDRB_imm_A1(Rt,Rn,imm12,P,U,W)
+{
+	return aborttrap_LDRB_imm(ctx,Rt,Rn,imm12,P,U,!P || W);
+}
+
+# A8.6.63 LDRB (literal)
+LDRB_lit_A1(Rt,imm12,U,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDRB_lit(ctx,Rt,imm12,U);
+}
+
+# A8.6.64 LDRB (register)
+LDRB_reg_A1(Rt,Rn,imm5,type,Rm,P,U,W)
+{
+	eshift shift_t;
+	uint32_t shift_n;
+	decodeimmshift(type,imm5,&shift_t,&shift_n);
+	return aborttrap_LDRB_reg(ctx,Rt,Rn,Rm,P,U,!P || W,shift_t,shift_n);
+}
+
+# A8.6.65 LDRBT
+LDRBT_A1(Rt,Rn,imm12,U)
+{
+	return aborttrap_LDRBT_imm(ctx,Rt,Rn,imm12,true,U);
+}
+
+LDRBT_A2(Rt,Rn,imm5,type,Rm,U)
+{
+	eshift shift_t;
+	uint32_t shift_n;
+	decodeimmshift(type,imm5,&shift_t,&shift_n);
+	return aborttrap_LDRBT_reg(ctx,Rt,Rn,Rm,true,U,shift_t,shift_n);
+}
+
+# A8.6.86 LDRT
+LDRT_A1(Rt,Rn,imm12,U)
+{
+	return aborttrap_LDRT_imm(ctx,Rt,Rn,imm12,true,U);
+}
+
+LDRT_A2(Rt,Rn,imm5,type,Rm,U)
+{
+	eshift shift_t;
+	uint32_t shift_n;
+	decodeimmshift(type,imm5,&shift_t,&shift_n);
+	return aborttrap_LDRT_reg(ctx,Rt,Rn,Rm,true,U,shift_t,shift_n);
+}
+
+# A8.6.189 STM/STMIA/STMEA
+STMIA_A1(Rn,W,reglist)
+{
+	return aborttrap_STMIA(ctx,Rn,reglist,W);
+}
+
+# A8.6.190 STMDA/ED
+STMDA_A1(Rn,W,reglist)
+{
+	return aborttrap_STMDA(ctx,Rn,reglist,W);
+}
+
+# A8.6.191 STMDB/FD
+STMDB_A1(Rn,W,reglist)
+{
+	return aborttrap_STMDB(ctx,Rn,reglist,W);
+}
+
+# A8.6.192 STMIB/FA
+STMIB_A1(Rn,W,reglist)
+{
+	return aborttrap_STMIB(ctx,Rn,reglist,W);
+}
+
+# A8.6.194 STR (immediate, ARM)
+STR_imm_A1(Rt,Rn,imm12,P,U,W)
+{
+	return aborttrap_STR_imm(ctx,Rt,Rn,imm12,P,U,!P || W);
+}
+
+# A8.6.195 STR (register)
+STR_reg_A1(Rt,Rn,imm5,type,Rm,P,U,W)
+{
+	eshift shift_t;
+	uint32_t shift_n;
+	decodeimmshift(type,imm5,&shift_t,&shift_n);
+	return aborttrap_STR_reg(ctx,Rt,Rn,Rm,P,U,!P || W,shift_t,shift_n);
+}
+
+# A8.6.197 STRB (immediate, ARM)
+STRB_imm_A1(Rt,Rn,imm12,P,U,W)
+{
+	return aborttrap_STRB_imm(ctx,Rt,Rn,imm12,P,U,!P || W);
+}
+
+# A8.6.198 STRB (register)
+STRB_reg_A1(Rt,Rn,imm5,type,Rm,P,U,W)
+{
+	eshift shift_t;
+	uint32_t shift_n;
+	decodeimmshift(type,imm5,&shift_t,&shift_n);
+	return aborttrap_STRB_reg(ctx,Rt,Rn,Rm,P,U,!P || W,shift_t,shift_n);
+}
+
+# A8.6.199 STRBT
+STRBT_A1(Rt,Rn,imm12,U)
+{
+	return aborttrap_STRBT_imm(ctx,Rt,Rn,imm12,true,U);
+}
+
+STRBT_A2(Rt,Rn,imm5,type,Rm,U)
+{
+	eshift shift_t;
+	uint32_t shift_n;
+	decodeimmshift(type,imm5,&shift_t,&shift_n);
+	return aborttrap_STRBT_reg(ctx,Rt,Rn,Rm,true,U,shift_t,shift_n);
+}
+
+# A8.6.210 STRT
+STRT_A1(Rt,Rn,imm12,U)
+{
+	return aborttrap_STRT_imm(ctx,Rt,Rn,imm12,true,U);
+}
+
+STRT_A2(Rt,Rn,imm5,type,Rm,U)
+{
+	eshift shift_t;
+	uint32_t shift_n;
+	decodeimmshift(type,imm5,&shift_t,&shift_n);
+	return aborttrap_STRT_reg(ctx,Rt,Rn,Rm,true,U,shift_t,shift_n);
+}
+
+# A8.6.219 SWP, SWPB
+SWP_SWPB_A1(Rt,Rt2,Rn,B,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_SWP(ctx,Rt,Rt2,Rn,B);
+}
+
+# B6.1.2 LDM (exception return)
+LDM_exception_A1(Rn,reglist,P,U,W)
+{
+	return aborttrap_LDM_exception(ctx,Rn,reglist,W,U,(P==U));
+}
+
+# B6.1.3 LDM (user registers)
+LDM_user_A1(Rn,reglist,P,U,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDM_user(ctx,Rn,reglist,U,(P==U));
+}
+
+# B6.1.11 STM (user registers)
+STM_user_A1(Rn,reglist,P,U,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_STM_user(ctx,Rn,reglist,U,(P==U));
+}
+
+# A8.6.122 POP
+# Map to the underlying LDM/LDR instruction, it exhibits the same behaviour
+POP_A1 as if LDMIA_A1
+POP_A2 as if LDR_imm_A1
+
+# A8.6.123 PUSH
+# Map to the underlying STM/STR instruction, it exhibits the same behaviour
+PUSH_A1 as if STMDB_A1
+PUSH_A2 as if STR_imm_A1

aborttrap/actions/ARMv4

+# Copyright (c) 2021, RISC OS Open Ltd
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met: 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+#       may be used to endorse or promote products derived from this software
+#       without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+# 
+
+# A8.6.74 LDRH (immediate, ARM)
+LDRH_imm_A1(Rt,Rn,imm4H,imm4L,P,U,W)
+{
+	return aborttrap_LDRH_imm(ctx,Rt,Rn,(imm4H<<4)|imm4L,P,U,!P || W);
+}
+
+# A8.6.75 LDRH (literal)
+LDRH_lit_A1(Rt,imm4H,imm4L,U,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDRH_lit(ctx,Rt,(imm4H<<4)|imm4L,U);
+}
+
+# A8.6.76 LDRH (register)
+LDRH_reg_A1(Rt,Rn,Rm,P,U,W,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDRH_reg(ctx,Rt,Rn,Rm,P,U,!P || W,SHIFT_LSL,0);
+}
+
+# A8.6.78 LDRSB (immediate)
+LDRSB_imm_A1(Rt,Rn,imm4H,imm4L,P,U,W)
+{
+	return aborttrap_LDRSB_imm(ctx,Rt,Rn,(imm4H<<4)|imm4L,P,U,!P || W);
+}
+
+# A8.6.79 LDRSB (literal)
+LDRSB_lit_A1(Rt,imm4H,imm4L,U,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDRSB_lit(ctx,Rt,(imm4H<<4)|imm4L,U);
+}
+
+# A8.6.80 LDRSB (register)
+LDRSB_reg_A1(Rt,Rn,Rm,P,U,W,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDRSB_reg(ctx,Rt,Rn,Rm,P,U,!P || W,SHIFT_LSL,0);
+}
+
+# A8.6.82 LDRSH (immediate)
+LDRSH_imm_A1(Rt,Rn,imm4H,imm4L,P,U,W,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDRSH_imm(ctx,Rt,Rn,(imm4H<<4)|imm4L,P,U,!P || W);
+}
+
+# A8.6.83 LDRSH (literal)
+LDRSH_lit_A1(Rt,imm4H,imm4L,U,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDRSH_lit(ctx,Rt,(imm4H<<4)|imm4L,U);
+}
+
+# A8.6.84 LDRSH (register)
+LDRSH_reg_A1(Rt,Rn,Rm,P,U,W,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDRSH_reg(ctx,Rt,Rn,Rm,P,U,!P || W,SHIFT_LSL,0);
+}
+
+# A8.6.207 STRH (immediate, ARM)
+STRH_imm_A1(Rt,Rn,imm4H,imm4L,P,U,W)
+{
+	return aborttrap_STRH_imm(ctx,Rt,Rn,(imm4H<<4)|imm4L,P,U,!P || W);
+}
+
+# A8.6.208 STRH (register)
+STRH_reg_A1(Rt,Rn,Rm,P,U,W,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_STRH_reg(ctx,Rt,Rn,Rm,P,U,!P || W,SHIFT_LSL,0);
+}
+

aborttrap/actions/ARMv5TE

+# Copyright (c) 2021, RISC OS Open Ltd
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met: 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+#       may be used to endorse or promote products derived from this software
+#       without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+# 
+
+# A8.6.66 LDRD (immediate)
+LDRD_imm_A1(Rt,Rn,imm4H,imm4L,P,U,W)
+{
+	if(Rt==15)
+		return aborttrap_ERROR(Unexpected); /* Don't allow some guy's dodgy code to cause us to access a nonexistant register! */
+	return aborttrap_LDRD_imm(ctx,Rt,Rt+1,Rn,(imm4H<<4)|imm4L,P,U,!P || W);
+}
+
+# A8.6.67 LDRD (literal)
+LDRD_lit_A1(Rt,imm4H,imm4L,U,nonstandard)
+{
+	if(nonstandard || (Rt==15))
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDRD_lit(ctx,Rt,Rt+1,(imm4H<<4)|imm4L,U);
+}
+
+# A8.6.68 LDRD (register)
+LDRD_reg_A1(Rt,Rn,Rm,P,U,W,nonstandard)
+{
+	if(nonstandard || (Rt==15))
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDRD_reg(ctx,Rt,Rt+1,Rn,Rm,P,U,!P || W);
+}
+
+# A8.6.200 STRD (immediate)
+STRD_imm_A1(Rt,Rn,imm4H,imm4L,P,U,W)
+{
+	if(Rt==15)
+		return aborttrap_ERROR(Unexpected); /* Don't allow some guy's dodgy code to cause us to access a nonexistant register! */
+	return aborttrap_STRD_imm(ctx,Rt,Rt+1,Rn,(imm4H<<4)|imm4L,P,U,!P || W);
+}
+
+# A8.6.201 STRD (register)
+STRD_reg_A1(Rt,Rn,Rm,P,U,W,nonstandard)
+{
+	if(nonstandard || (Rt==15))
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_STRD_reg(ctx,Rt,Rt+1,Rn,Rm,P,U,!P || W);
+}
+

aborttrap/actions/ARMv6

+# Copyright (c) 2021, RISC OS Open Ltd
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met: 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of RISC OS Open Ltd nor the names of its contributors
+#       may be used to endorse or promote products derived from this software
+#       without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+# 
+
+# A8.6.69 LDREX
+LDREX_A1(Rt,Rn,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_LDREX_common(ctx,Rt,0,Rn,4);
+}
+
+# A8.6.202 STREX
+STREX_A1(Rt,Rn,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_STREX_common(ctx,Rt,0,Rn,4);
+}
+
+# B6.1.8 RFE
+RFE_A1(Rn,P,U,W,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_RFE(ctx,Rn,W,U,P==U);
+}
+
+# B6.1.10 SRS
+SRS_A1(mode,P,U,W,nonstandard)
+{
+	if(nonstandard)
+		return aborttrap_ERROR(Unexpected);
+	return aborttrap_SRS(ctx,(eprocmode) mode,W,U,P==U);
+}
+