Remove more direct page table access

RISCOS_LogToPhys and OS_Memory 20 (compatibility page) changed to use
suitable subroutines for reading the page tables instead of accessing
them directly.

s/HAL

@@ -2451,37 +2451,19 @@ RISCOS_LogToPhys ROUT
         ; Try checking L1PT for any section mappings (logical_to_physical only
         ; deals with regular 4K page mappings)
         ; TODO - Add large page support
-        LDR     r9, =L1PT
-        MOV     r5, r4, LSR #20
-        LDR     a1, [r9, r5, LSL #2]
-        ASSERT  L1_Section = 2
-        EOR     a1, a1, #2
-        TST     a1, #3
-        MOVNE   a2, #-1
-        MOVNE   a1, #-1
-        BNE     %FT10
-        ; Check if it's a supersection
-        TST     a1, #L1_SS
-        BNE     %FT20
-        MOV     a2, #0 ; vanilla sections only map bottom 4GB of physical space
-        ; Apply offset from bits 0-19 of logical addr
-      [ NoARMT2
-        MOV     a1, a1, LSR #20
-        ORR     a1, a1, r4, LSL #12
-        MOV     a1, a1, ROR #12
-      |
-        BFI     a1, r4, #0, #20
-      ]
+        MOV     r0, a1, LSR #20
+        MOV     r0, r0, LSL #20
+        BL      LoadAndDecodeL1Entry
+        CMP     r2, #-2
+        BHS     %FT10
+        MOVHS   a1, #-1                 ; No L1 page
+        MOVHS   a2, #-1
+        SUBLO   r3, r3, #1              ; Valid L1 page, apply sub-page offset
+        ANDLO   r4, r4, r3
+        ADDLO   a1, r0, r4
 10
         Pull    "r4,r5,r8,r9,pc"
 
-20      MOV     a3, a1, LSR #L1_SSb36Shift
-        UBFX    a2, a1, #L1_SSb32Shift, #L1_SSb32Width
-        BFI     a2, a3, #36-32, #L1_SSb36Width
-        ; Apply offset from bits 0-23 of logical addr
-        BFI     a1, r4, #0, #24
-        Pull    "r4,r5,r8,r9,pc"
-
 ; int RISCOS_IICOpV(IICDesc *descs, uint32_t ndesc_and_bus)
 RISCOS_IICOpV ROUT
         Push    "lr"

s/MemInfo

@@ -1711,13 +1711,14 @@ ChangeCompatibility ROUT
         CMPNE   r0, r1
         EXIT    EQ
         ; If we're attempting to enable it, make sure nothing else has mapped itself in to page zero
-        LDR     r8, =L2PT
         CMP     r1, #0
-        LDRNE   r0, [r8]
-        CMPNE   r0, #0
-        MOVNE   r1, #-1
-        FRAMSTR r1,NE
-        EXIT    NE
+        BEQ     %FT05
+        MOV     r4, #0
+        BL      logical_to_physical
+        MOVCC   r1, #-1
+        FRAMSTR r1,CC
+        EXIT    CC
+05
         ; Set up temp DANode on the stack so we can use a Batcall to manage the mapping
         MOV     r2, sp
         MOV     r0, #DynAreaFlags_NotCacheable