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Commit 49836a59 authored by Kevin Bracey's avatar Kevin Bracey
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* Converted to building with ObjAsm (but still a single object file using ORG). 

* Added ARM_IMB and ARM_IMBRange SWIs as recommended by ARMv5.
* Some early prototype HAL bits popped in - a lot of source restructuring still
  to come.
* New debug target creates an AIF image with debug information, and translates
  this into an ASCII object file for the 16702B logic analyser.

Version 5.35, 4.79.2.1. Tagged as 'Kernel-5_35-4_79_2_1'
parent 0c77dd31
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Docs/32bit
View file @ 49836a59
Here are some notes on my thoughts so far about 32-bit RISC OS.
Any comments appreciated.
GENERAL
=======
My current belief is that RISC OS will either be running 26-bit, or 32-bit,
with no in between state.
RISC OS will either be running 26-bit, or 32-bit, with no in-between state.
When running 32-bit, it will make no use of 26-bit modes, and will call all
routines in a 32-bit mode. There will be no support for 26-bit code, as this
......@@ -37,7 +33,7 @@ that uses MSR which will work on ARM6 onwards.
This way we will continue to be able to test software on our desktop systems -
it can be the same 32-bit binary - it will just run in a 26-bit mode.
RISC OS will be largely unmodified - almost all binary APIs will act the same
RISC OS is initially largely unmodified - almost all binary APIs will act the same
in a 32-bit system as they do now, except that they will be called in a 32-bit
version of the documented processor mode.
......@@ -74,11 +70,16 @@ preserve flags, you will probably be forced to use MRS and MSR instructions.
These are NOPs on pre-ARM 6 ARMs, so you may be able to do clever stuff to
keep ARM2 compatibility.
For example, the recommended code to check whether you're in a 26-bit mode is:
For example, the recommended general-purpose code to check whether you're in
a 26-bit mode is:
MOV R0, #0
MOV R0, #0 ; for ARM 2+3 compatibility only
MRS R0, CPSR ; NOP on 26-bit only ARMs
TST R0, #2_11100 ; EQ if in a 26-bit mode, NE if not
TST R0, #2_11100 ; EQ if in a 26-bit mode, NE if 32-bit
If you know you are in a privileged mode, then you can use:
TEQ PC, PC ; EQ if in a 32-bit mode, NE if 26-bit
Sometimes you may be forced to play with the SPSR registers. Beware: interrupt
code will corrupt SPSR_svc if it calls a SWI. Existing interrupt handlers know
......@@ -133,21 +134,17 @@ before. When running on a 32-bit system, you needn't preserve flags. The
following wrapper around the original SWI entry (converted to be 32-bit safe)
achieves this, assuming you always want NZ preserved on a 26-bit system.
Push R14
BL Original_SWI_Code
Pull R14
[ PreARM6compatibility
MOV R10,#0
]
MRS R10,CPSR ; NOP on pre-ARM6
TST R10,#2_11100 ; EQ if in 26-bit mode - C,V unaltered
MOVNE PC,R14 ; 32-bit exit: NZ corrupted, CV passed back
Push R14
BL Original_SWI_Code
Pull R14
TEQ PC,PC ; are we in a 32-bit mode?
MOVEQ PC,R14 ; 32-bit exit: NZ corrupted, CV passed back
[ PassBackC
BICCC R14,R14,#C_bit ; Extra guff to pass back C as well
ORRCS R14,R14,#C_bit
BICCC R14,R14,#C_bit ; Extra guff to pass back C as well
ORRCS R14,R14,#C_bit
]
MOVVCS PC,R14 ; 26-bit exit: NZC preserved, V clear
ORRVSS PC,R14,#V_bit ; 26-bit exit: NZC preserved, V set
MOVVCS PC,R14 ; 26-bit exit: NZC preserved, V clear
ORRVSS PC,R14,#V_bit ; 26-bit exit: NZC preserved, V set
Yes, this is cumbersome, but it can be removed when backwards compatibility is
no longer desired. The alternative, which would be to pass in caller flags in
......@@ -289,21 +286,21 @@ A few vectors, like RemV, attach significance to entry flags. If not claiming,
you mustn't change those flags for the next callee. In 26-bit mode this might
have been achieved by:
CMP R1,#mybuffer
MOVNES PC,LR
CMP R1,#mybuffer
MOVNES PC,LR
In the 32-bit world, you could change the CMP to a TEQ to preserve C and V, or
you could use something like:
Push R14
MRS R14, CPSR
CMP R1, #maxbuffers
BLS handleit
MSR CPSR_f, R14
Pull PC
Push R14
MRS R14, CPSR
CMP R1, #maxbuffers
BLS handleit
MSR CPSR_f, R14
Pull PC
handleit
...
...
INSIDE THE KERNEL
=================
......@@ -372,6 +369,7 @@ unmapped, to cause an abort.
Their actual locations and sizes are subject to change. In particular, they
may not be in the lower 64MB in future.
MISCELLANEOUS SWIS
==================
......
Docs/HAL/Entries 0 → 100644
View file @ 49836a59
RISC OS and the "HAL"
=====================
RISC OS currently is tied to the IOMD20 and VIDC20 peripheral set,
descendents of the original IOC, MEMC and VIDC devices designed in parallel
with the original ARM. These devices provide a close fit with RISC OS, and
their functionality is well suited to general purpose and embedded systems,
but the continuing drive to reduce cost requires us to support other
peripheral sets on off-the-shelf ARM system on chips.
First targets for support are L7205/L7210 for Customer L and CL92xx (the new
ARM920T based devices) for Customer A. Enclosed are a summary of their
advantages and disadvantages over the ARM7500FE for our Information
Appliance designs.
L7205 CL92xx
+ Faster (50% or so) + Faster (400%+)
+ SDRAM support + SDRAM support
+ USB + USB
+ EIDE interface
+ Lots of GPIO
- No hardware cursor
- No floating point - Incompatible floating point
- No video DACs - No video DACs
- No PS/2 - No PS/2
- Bizarre MS-Windows video system
To support these devices, and others in the future, a simple HAL is to be
inserted underneath RISC OS. This will provide two functions. Firstly, it
will be responsible for initial system bootstrap, much like a PC BIOS, and
secondly it will provide simple APIs to allow hardware access.
The HAL APIs are a thin veneer on top of the hardware. They are designed to
act as replacements for all the hardware knowledge and manipulation performed
by the RISC OS Kernel, together with some APIs that will allow RISC OS driver
modules to become more hardware independent. No attempt will be made (at this
stage) to perform such tasks as separating the video drivers from the Kernel,
for example.
One tricky design decision is the amount of abstraction to aim for. Too
little, and the system is not flexible enough; too much and HAL design is
needlessly complicated for simple hardware. The present design tries to
err on the side of too little abstraction. Extra, more abstract APIs can
always be added later. So, initially, for example, the serial device API
will just provide discovery, some capability flags and the base address
of the UART register set. This will be sufficient for the vast majority
of devices. If new hardware comes along later that isn't UART compatible,
a new API can be defined. Simple hardware can continue to just report
UART base addresses.
The bulk of device driver implementation remains in RISC OS modules - the
difference is that the HAL will allow many device drivers to no longer
directly access hardware. For example, PS2Driver can now use HAL calls to
send and receive bytes through the PS/2 ports, and thus is no longer tied to
IOMD's PS/2 hardware. Similarly, interrupt masking and unmasking, as
performed by any device vector claimant, is now a HAL call. Note that HAL
calls are normally performed via a Kernel SWI - alternatively the Kernel
can return the address of specific Kernel routines. There is nothing to stop
specific drivers talking to hardware directly, as long as they accept that
this will tie them to specific devices.
This dividing line between the HAL and RISC OS driver modules is crucial. If
the HAL does everything, then we have achieved nothing - we have just as much
hardware dependent code - it's just in a different place. It is important to
place the dividing line as close to the hardware as possible, to make it easy
to design a HAL and to prevent large amounts of code duplication between
HALs for different platforms.
The Kernel remains responsible for the ARM's MMU and all other aspects of the
CPU core. The HAL requires no knowledge of details of ARM implementations,
and thus any HAL implementation should work on any processor from the ARM610
to the ARM940T or XScale.
OS independence
===============
Notionally, the HAL implementation is OS independent. It makes no assumptions
about the virtual memory map of the OS, and only uses the defined HAL->OS
entries. The HAL should not call RISC OS SWIs.
In practice, however, the HALs are unlikely to be used on anything other
than RISC OS, and many HALs are likely to be written. This makes it sensible
to place as much intelligence as possible within RISC OS itself, to prevent
duplicated effort.
Calling standards
=================
RISC OS and the HAL are two separate entities, potentially linked separately.
Thus some simple dynamic linking is required. This occurs via a hybrid of the
RISC OS module header and Shared C Library stubs. Each RISC OS/HAL entry is
given a unique (arbitrary) number, starting at 0. The offset to each entry is
given in an entry table. Calls can be made manually through this table, or
stubs could be created at run-time to allow high-level language calls.
Every entry (up to the declared maximum) must exist. If not implemented, a
failure response must be returned, or the call ignored, as appropriate.
To permit high-level language use in the future, the procedure call standard
in both directions is ATPCS, with no use of floating point, no stack limit
checking, no frame pointers, and no Thumb interworking. HAL code is expected
to be ROPI and RWPI (hence it is called with its static workspace base in
sb). The OS kernel is neither ROPI nor RWPI (except for the pre-MMU calls,
which are ROPI).
The HAL will always be called in a privileged mode - if called in an
interrupt mode, the corresponding interrupts will be disabled. The HAL should
not change mode. HAL code should work in both 26-bit and 32-bit modes (but
should assume 32-bit configuration).
Header formats
==============
The OS is linked to run at a particular base address. At present, the address
will be at <n>MB + 64KB. This allows a HAL of up to 64K to be placed at the
bottom of a ROM below the OS, and the whole thing to be section-mapped.
However, if a different arrangement is used, the system will still work
(albeit slightly less efficiently).
The OS starts with a magic word - this aids probing and location of images.
Following that is a defined header format:
Word 0: Magic word ("OSIm" - &6D49534F)
Word 1: Flags (0)
Word 2: Image size
Word 3: Offset from base to entry table
Word 4: Number of entries available
The HAL itself may have whatever header is required to start the system. For
example on ARM7500 16->32 bit switch code is required, and on the 9500 parts
a special ROM header and checksum must be present. Instead of a header,
a pointer to the HAL descriptor is passed to the OS in the OS_Start call:
Word 0: Flags (0)
Word 1: Offset from descriptor to start of HAL (will be <= 0)
Word 2: HAL size
Word 3: Offset from descriptor to entry table
Word 4: Number of entries available
Word 5: Static workspace required
Eoch of the HAL and the OS must be contiguous within physical memory.
RISC OS entry points from HAL init
==================================
Entry 0:
void RISCOS_InitARM(unsigned int flags)
flags: reserved - sbz
On entry:
SVC mode
MMU and caches off
IRQs and FIQs disabled
No RAM or stack used
On exit:
Instruction cache may be on
Usage:
This routine must be called once very early on in the HAL start-up, to accelerate the
CPU for the rest of HAL initialisation. Typically, it will just enable the instruction
cache (if possible on the ARM in use), and ensure that the processor is in 32-bit
configuration and mode.
Some architecture 4 (and later) ARMs have bits in the control register that affect
the hardware layer - eg the iA and nF bits in the ARM920T. These are the HAL's
responsibility - the OS will not touch them. Conversely, the HAL should not touch the
cache, MMU and core configuration bits (currently bits 0-14).
On architecture 3, the control register is write only - the OS will set bits 11-31 to
zero.
Likewise, such things as the StrongARM 110's register 15 (Test, Clock and Idle Control)
are the HAL's responsibility. The OS does not know about the configuration of the
system, so cannot program such registers.
This entry may not be called after RISCOS_Start.
Entry 1:
void *RISCOS_AddRAM(unsigned int flags, void *start, void *end, uintptr_t sigbits, void *ref)
flags
bit 0: video memory (only first contiguous range will be used)
bits 8-11: speed indicator (arbitrary, higher => faster)
other bits reserved (SBZ)
start
start address of RAM (inclusive) (no alignment requirements)
end
end address of RAM (exclusive) (no alignment requirements, but must be >= start)
sigbits
significant address bit mask (1 => this bit of addr decoded, 0 => this bit ignored)
ref
reference handle (NULL for first call)
Returns ref for next call
On entry:
SVC32 mode
MMU and data cache off
IRQs and FIQs disabled
Other notes:
This entry point must be the first call from the HAL to RISC OS following a hardware
reset. It may be called as many times as necessary to give all enumerate RAM that
is available for general purpose use. It should only be called to declare video
memory if the video memory may be used as normal RAM when in small video modes.
To permit software resets:
The HAL must be non-destructive of any declared RAM outside the first 4K of the first
block.
The stack pointer should be initialised 4K into the first block, or in some non-
declared RAM.
Must present memory in a fixed order on any given system.
Current limitations:
The first block must be at least 256K and 16K aligned. (Yuck)
Block coalescing only works well if RAM banks are added in ascending address order.
RISC OS will use RAM at the start of the first block as initial workspace. Max usage
is 16 bytes per block + 32 (currently 8 per block + 4). This limits the number of
discontiguous blocks (although RISC OS will concatanate contiguous blocks where
possible).
This call must not be made after RISCOS_Start.
Entry 2:
void RISCOS_Start(unsigned int flags, int *riscos_header, int *hal_entry_table, void *ref)
flags
bit 0: power on reset
On entry:
SVC32 mode
MMU and data cache off
IRQs and FIQs disabled
Usage:
This routine must be called after all calls to RISCOS_AddRAM have been completed.
It does not return. Future calls back to the HAL are via the HAL entry table, after
the MMU has been enabled.
Entry 3:
void *RISCOS_MapInIO(unsigned int flags, void *phys, unsigned int size)
flags: bit 2 => make memory bufferable
phys: physical address to map in
size: number of bytes of memory to map in
Usage:
This routine is used to map in IO memory for the HAL's usage. Normally it would
only be called during HAL_Init(). Once mapped in the IO space cannot be released.
It returns the resultant virtual address corresponding to phys, or 0 for failure.
Failure can only occur if no RAM is available for page tables, or if the virtual
address space is exhausted.
void *RISCOS_AccessPhysicalAddress(unsigned int flags, void *phys, void **oldp)
flags: bit 2 => make memory bufferable
other bits must be zero
phys: physical address to access
oldp: pointer to location to store old state (or NULL)
On entry:
Privileged mode
MMU on
FIQs on
Re-entrant
On exit:
Returns logical address corresponding to phys
Usage:
Arranges for the physical address phys to be mapped in to logical memory.
In fact, the whole megabyte containing "phys" is mapped in (ie if phys =
&12345678, then &12300000 to &123FFFFF become available). The memory is
supervisor access only, non-cacheable, non-bufferable by default, and will
remain available until the next call to RISCOS_Release/AccessPhysicalAddress
(although interrupt routines or subroutines may temporarily map in something
else).
When finished, the user should call RISCOS_ReleasePhysicalAddress.
void RISCOS_ReleasePhysicalAddress(void *old)
old: state returned from a previous call to RISCOS_AccessPhysicalAddress
On entry:
MMU on
FIQs on
Re-entrant
Usage:
Call with the a value output from a previous RISCOS_ReleasePhysicalAddress.
Example:
void *old;
unsigned int *addr = (unsigned int *) 0x80005000;
unsigned int *addr2 = (unsigned int *) 0x90005000;
addr = (unsigned int *) RISCOS_AccessPhysicalAddress(addr, &old);
addr[0] = 3; addr[1] = 5;
addr2 = (unsigned int *) RISCOS_AccessPhysicalAddress(addr2, NULL);
*addr2 = 7;
RISCOS_ReleasePhysicalAddress(old);
HAL entries
===========
void HAL_Start(int *riscos_header)
Docs/HAL/Init 0 → 100644
View file @ 49836a59
Arrange correct ROM image
POST
Initialise memory system
ROM timings, width
Reset screen
Disable interrupts
Start timers
Size memory
Set up table describing memory layout
Set up video DMA
Time CPU
CONT / CONT_Break
InitMEMC (in: r1 = 0 -> Reset, 1 -> Break)
Check for 7500 vs IOMD
Program CPU, MEM and IO clocks
Set ROM timings
Set ROM width
Set up VRAM refresh
Set up peripheral timings
Set up sound format
Ensure MMU off and caches
Set up VIDC
Disable interrupts in IOC
Start timer 0
MemSize (out: r0 = page size, r1 = memory size, r2 = MEMC CR)
Set up RAM width
Find memory - create a table of (addr,len) pairs (in first memory found)
Find VRAM - if none take from first block
Start filling in page zero (in first block)
Set up video DMA registers
Allocate L1PT, and some L2PT, and soft CAM
Turn on MMU and caches
TimeCPU (out: r0 = peak RAM speed in kHz)
Put in extra pages: cursor, system heap
Start keyboard scanning
If POR or FX 200
Clear memory
Check processor type
Fill in processor vectors
Read CMOS
Fill in SWI dispatch table
Wait for keyboard (up to two seconds)
If (POR AND R/T/Del/Copy)
Reset CMOS
Goto Hard Reset
IF (POR or CannotReset or SysHeapCorrupt or CAM map nonsense or Ctrl pressed)
Clear the CAM
Set it up
InitDynamicAreas
Create system dynamic areas
InitVectors
Clear SWI hash table
Clear POR bit
Else
Do the soft reset stuff
Re-initialise kernel
If (hard reset)
Init variables
Initialise modules
PostInit
Set mode
Print "RISC OS"
Service_Reset
Shut all files
Beep if hard reset
If numpad key down
reconfigure monitor, change mode
print "monitor type reconfigured"
Check shift
Do boot
Else check *
Else enter language
\ No newline at end of file
Docs/HAL/MoreEnts 0 → 100644
View file @ 49836a59
Initialisation
==============
HAL_Init
Interrupts
==========
The HAL must provide the ability to identify, prioritise and mask IRQs, and the ability
to mask FIQs. RISC OS supplies the ARM's processor vectors, and on an IRQ calls the HAL
to request the identity of the highest priority interrupt.
IRQ and FIQ device numbers are arbitrary, varying from system to system. They should be
arranged to allow quick mappings to and from hardware registers, and should ideally
be packed, starting at 0.
HAL_IRQEnable
HAL_IRQDisable
HAL_IRQClear
HAL_FIQEnable
HAL_FIQDisable
HAL_FIQClear
HAL_GetHighestIRQ
Timers
======
The HAL must supply at least one timer capable of generating periodic interrupts.
Each timer should generate a separate logical interrupt.
HAL_Timer
HAL_TimerEnable
HAL_TimerRead
HAL_TimerSetRate
HAL_TimerDisable
Docs/HAL/Notes 0 → 100644
View file @ 49836a59
Entry into RISC OS:
POST check (if any) complete
CPU & memory systems at full speed
MMU off, SVC32 mode, IRQs+FIQs disabled
All interrupts masked
I/O timings set up
DRAM refresh running
Video system stabilised (off?)
Information passed:
Table of (addr,len) pairs of RAM
Address + amount of VRAM
Memory speed?
CPU speed?
Entry point to HAL
Questions:
How to clear RAM without logical copy? Do we NEED a logical copy?
Yes we do - but logical copy will NOT be contiguous.
Physical Size Logical - offset
F0000000 01000000 80000000 70000000
F1000000 01000000 81000000 70000000
60000000 00001000 82000000 22000000 - fast SRAM - how to signal?
02000000 00200000 80000000 7FE00000
10000000 01700000 80200000 70200000
11B00000 02500000 81900000 6FE00000
14000000 04000000 83E00000 6FE00000
02000000 00200000 82000000 80000000
10000000 01700000 90000000 80000000
11B00000 02500000 91B00000 80000000
14000000 04000000 94000000 80000000
Memory Map
00000000 16K Kernel workspace
00004000 16K Scratch space
00008000 Mem-32K Application memory
0xxxxxxx 3840M-Mem Dynamic areas
F0000000 160M I/O space (growing downwards if necessary)
FA000000 1M HAL workspace
FA100000 8K IRQ stack
FA200000 32K SVC stack
FA300000 8K ABT stack
FA400000 8K UND stack
FAE00000 1M Reserved for physical memory accesses
FAFE8000 32K HAL workspace
FAFF0000 32K "Cursor/System/Sound" block (probably becoming just "System")
FAFF8000 32K "Nowhere"
FB000000 4M L2PT
FB400000 16K L1PT
FB404000 4M-16K System heap
FB800000 8M Soft CAM
FC000000 64M ROM
26-bit system:
00000000 16K Kernel workspace
00004000 16K Scratch space
00008000 28M-32K Application memory
01C00000 32K SVC stack
01C08000 2M-32K System heap
01F00000 32K Cursor/System/Sound
01F08000 32K "Nowhere"
02100000 15M Module area
03000000 8M I/O space
03800000 8M ROM
04000000 2G-64M Dynamic areas
80000000 512M Logical copy of physical space
A0000000 1280M Dynamic areas
F0000000 224M I/O space (growing downwards if necessary)
FE000000 1M HAL workspace
FE100000 8K ABT stack
FE200000 8K UND stack
FF000000 4M L2PT + embedded L1PT
FF800000 8M Soft CAM
"Soft" resets
Entry through HAL - full HAL initialisation.
HAL must not destroy (much) memory.
RISC OS detects intact memory and makes the reset "soft".
RAM page tables reconstructed from CAM.
Other page tables reconstructed through HAL.
"Break"
RISC OS calls HAL to shut down, then shuts off MMU, and calls HAL_Reset code.
HAL then re-enters RISC OS in the usual fashion.
Makefile
View file @ 49836a59
......@@ -33,11 +33,16 @@ C_EXP_HDR = <cexport$dir>.Global.h
#
MKDIR = mkdir -p
AS = aasm
ARMASM = objasm
LD = link
CP = copy
RM = remove
WIPE = -wipe
CCFLAGS = -c -depend !Depend -IC:
ASFLAGS = -depend !Depend -Stamp -quit -To $@ -From
ASFLAGS = -depend !Depend ${THROWBACK} -Stamp -quit -To $@ -From
ARMASMFLAGS = -depend !Depend -g ${THROWBACK}
CPFLAGS = ~cfr~v
WFLAGS = ~cfr~v
TOKENISE = tokenise
TOKENS = Hdr:Tokens
......@@ -47,7 +52,10 @@ TOKENS = Hdr:Tokens
#
COMPONENT = Kernel
SOURCE = s.GetAll
TARGET = rm.${MACHINE}.Kernel
TARGET = rm.Kernel
AIFDBG = aif.Kernel
GPADBG = GPA
OBJECTS = o.GetAll
EXPORTS = ${EXP_HDR}.EnvNumbers \
${EXP_HDR}.ModHand \
${EXP_HDR}.PublicWS \
......@@ -59,16 +67,25 @@ EXPORTS = ${EXP_HDR}.EnvNumbers \
#
# Generic rules:
#
.SUFFIXES: .o .s
.s.o:; ${ARMASM} ${ARMASMFLAGS} -o $@ $<
rom: ${TARGET}
@echo ${COMPONENT}: rom module built
debug: ${GPADBG}
@echo ${COMPONENT}: debug image built
install_rom: ${TARGET}
${CP} ${TARGET} ${INSTDIR}.${COMPONENT} ${CPFLAGS}
@echo ${COMPONENT}: rom module installed
clean:
${RM} ${TARGET}
${RM} s.TMOSHelp
${WIPE} o.* ${WFLAGS}
${RM} ${TARGET}
${WIPE} aif ${WFLAGS}
${RM} ${GPADBG}
@echo ${COMPONENT}: cleaned
export: ${EXPORTS}
......@@ -92,14 +109,21 @@ resources-: resources_common
TokenCheck LocalRes:Messages
print LocalRes:CmdHelp { >> ${RESDIR}.${COMPONENT}.Messages }
${TARGET}: ${SOURCE} s.TMOSHelp
${MKDIR} rm.${MACHINE}
${AS} ${ASFLAGS} ${SOURCE}
stamp $@
${TARGET}: ${OBJECTS}
${LD} -bin -o ${TARGET} ${OBJECTS}
${AIFDBG}: ${OBJECTS}
${MKDIR} aif
${LD} -aif -bin -d -o ${AIFDBG} ${OBJECTS}
${GPADBG}: ${AIFDBG}
ToGPA ${AIFDBG} ${GPADBG}
s.TMOSHelp: ${TOKENS} HelpStrs
${TOKENISE} ${TOKENS} HelpStrs $@
o.GetAll: s.TMOSHelp
#
# Exported interface headers
#
......
MkRom,fd7
View file @ 49836a59
......@@ -14,5 +14,5 @@
|
Dir <Obey$Dir>
time
amu_machine rom
amu_machine rom debug THROWBACK=-throwback
time
TestSrc/Begin
View file @ 49836a59
......@@ -344,7 +344,7 @@ ts_ROM_bvectors
MACRO
MODE $mode_bits
msr ,CPSR_c,#I32_bit :OR: F32_bit :OR: $mode_bits
MSR CPSR_c,#I32_bit :OR: F32_bit :OR: $mode_bits
MEND
MACRO
......@@ -1871,7 +1871,7 @@ ts_led_fail
; This will take 1 Second to complete.
;
;|------>|--1/4 Sec--|--1/4 Sec--|--1/4 Sec--|--1/4 Sec--|
;|--Red--|---Green---|----Red----|----Red----|----Red----|\
;|--Red--|---Green---|----Red----|----Red----|----Red----|\ 
; \_______________________________________________/
;
; Red Green
......@@ -1892,7 +1892,7 @@ ts_led_pass
; This will take 1 Second to complete.
;
;|------>|--1/4 Sec--|--1/4 Sec--|--1/4 Sec--|--1/4 Sec--|
;|--Red--|---Green---|---Green---|---Green---|----RED----|\
;|--Red--|---Green---|---Green---|---Green---|----RED----|\ 
; \_______________________________________________/
;
; Red Green
......
TestSrc/Cmos
View file @ 49836a59
......@@ -87,9 +87,9 @@ ts_TXCheckAck ROUT
ts_SetC1C0 ROUT
MOVS R11, R14 ; NE: indicate not checking clock
ts_SetOrCheck
mrs ,R14, CPSR
MRS R14, CPSR
ORR R14, R14, #I32_bit ; disable interrupts
msr ,CPSR_c, R14
MSR CPSR_c, R14
ADD R0, R0, R1, LSL #1 ; R0 := C0 + C1*2
......@@ -221,10 +221,10 @@ ts_Acknowledge ROUT
BL ts_SetC1C0
TST R3, #1 ; should be LO for correct acknowledge
mrs ,R3, CPSR
MRS R3, CPSR
BICEQ R3, R3, #V_bit ; clear V if correct acknowledge
ORRNE R3, R3, #V_bit ; set V if no acknowledge
msr ,CPSR_f, R3
MSR CPSR_f, R3
MOV PC,R9
......
TestSrc/ExtCmd
View file @ 49836a59
......@@ -601,7 +601,7 @@ ts_execute ROUT
ADD pc,pc,r8 ; jump over the msr instruction
NOP
& 2_11100001011010011111000000001100 ;
MSR SPSR_cf,R12
ADDS r14,pc,r0 ; Load the address of %13 into r14
; to provide a return address
......
VersionASM
View file @ 49836a59
......@@ -10,9 +10,9 @@
GBLS Module_ApplicationDate4
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS ""
Module_Date SETS "08 Sep 2000"
Module_ApplicationDate2 SETS "08-Sep-00"
Module_ApplicationDate4 SETS "08-Sep-2000"
Module_FullVersion SETS "5.35"
Module_MinorVersion SETS "4.79.2.1"
Module_Date SETS "15 Sep 2000"
Module_ApplicationDate2 SETS "15-Sep-00"
Module_ApplicationDate4 SETS "15-Sep-2000"
Module_FullVersion SETS "5.35 (4.79.2.1)"
END
VersionNum
View file @ 49836a59
......@@ -4,15 +4,15 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 08 Sep 2000
#define Module_MinorVersion_CMHG 4.79.2.1
#define Module_Date_CMHG 15 Sep 2000
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion ""
#define Module_Date "08 Sep 2000"
#define Module_MinorVersion "4.79.2.1"
#define Module_Date "15 Sep 2000"
#define Module_ApplicationDate2 "08-Sep-00"
#define Module_ApplicationDate4 "08-Sep-2000"
#define Module_ApplicationDate2 "15-Sep-00"
#define Module_ApplicationDate4 "15-Sep-2000"
#define Module_FullVersion "5.35"
#define Module_FullVersion "5.35 (4.79.2.1)"
hdr/KernelWS
View file @ 49836a59
......@@ -228,19 +228,40 @@ DANode_NodeSize # 0
; The addresses below are only temporary; eventually most of them will be allocated at run time (we hope!)
[ :DEF: OldMemoryMap
AplWorkMaxSize * &01000000 ; 16M
RMAAddress * &01800000
RMAMaxSize * &00400000 ; 4M
ZeroPage * &00000000
[ HAL
; Sort out 26/32 bit versions
SVCStackSize * 32*1024
RMAAddress * &80000000 ; temporary - run time allocate
ScreenEndAdr * &A0000000 ; temporary - run time allocate
ScreenMaxSize * 480*1024
RMAMaxSize * -1
IO * &F0000000
HALWorkspace * &FA000000
IRQStackAddress * &FA100000
SVCStackAddress * &FA200000
PhysicalAccess * &FAE00000
CursorChunkAddress * &FAFF0000
L2PT * &FB000000
L1PT * &FB400000
SysHeapChunkAddress * &FB404000
SysHeapAddress * SysHeapChunkAddress
SysHeapMaxSize * &FB800000 - SysHeapAddress
CAM * &FB800000
|
AplWorkMaxSize * &01C00000 ; 28M
RMAAddress * &02100000
RMAMaxSize * &00B00000 ; 11M
]
SVCStackSize * 8*1024
SysHeapChunkAddress * &01C00000
SVCStackAddress * SysHeapChunkAddress
SysHeapAddress * SysHeapChunkAddress+SVCStackSize
SysHeapMaxSize * &00200000-SVCStackSize
CursorChunkAddress * &01F00000 ; Fixed size 32K
......@@ -260,6 +281,7 @@ ScreenMaxSize * 480*1024
FreePoolAddress * &06000000 ; may still go lower!
PhysRam * &05000000
]
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; system variables
......@@ -899,9 +921,19 @@ VDWSSize # 0
; *****************************************************************************
; Real workspace definition
; locations used during reset only
^ ZeroPage+&20
InitKbdHandler # 4
InitKbdWs # 16
InitUsedStart # 4
InitUsedEnd # 4
InitClearRamWs # 5*4
AlignSpace 32 ; because we clear 32 at a time
InitWsEnd # 0
; Basic kernel space - defined locations for external modules
^ &100
^ ZeroPage+&100
IRQ1V # 4 ; &100
Export_ESC_Status # 1 ; &104
......@@ -1015,30 +1047,55 @@ DRAMSizeD # 4
DRAMPhysAddrE # 4
DRAMSizeE # 4
[ MorrisSupport
DRAMPhysAddrExtra # 4 * 12 ; The DRAM used with MORRIS can fragment into four
DRAMSizeExtra # 4 * 12 ; blocks so allocate 3 extra word pairs per bank
DRAMPhysAddrExtra # 8 * 12 ; The DRAM used with MORRIS can fragment into four
; blocks so allocate 3 extra word pairs per bank
]
PhysRamTableEnd # 0
DRAMPhysTableSize * (PhysRamTableEnd-DRAMPhysAddrA) / 8
! 0, "VideoPhysAddr held at ":CC::STR:(VideoPhysAddr)
[ :LNOT: HAL
VRAMSize # 4 ; Amount of VRAM (in bytes) (may be more than 2M) (at &200 last time I checked)
VRAMWidth # 4 ; 0 => no VRAM, 1 => 32-bits wide, 2 => 64-bits wide
VideoBandwidth # 4 ; video bandwidth in bytes/sec
L2PTSize # 4 ; Amount of memory (in bytes) used for static L2PT
; - this consists of fixed size first bit, plus variable size
; bit for the free pool L2, which follows directly after it
]
SoftCamMapSize # 4 ; Amount of memory (in bytes) used for soft CAM map
; (whole number of pages)
[ {FALSE}
InitKbdHandler # 4 ; Address of interrupt routine
InitKbdWs # 16 ; Workspace for reset keyboard IRQ code (was 12 changed for Morris)
]
CLine_Softcopy # 1 ; Added for Morris - Monitor id
VRAMWidth # 1 ; 0 => no VRAM, 1 => 32-bits wide, 2 => 64-bits wide
[ :LNOT: STB
LCD_Active # 1 ; Added to support LCD/CRT switching. bm 6 bits 0=>External CRT in use, 1=>Mono, 2=>Passive colour, 3=>Active colour
; bit 7 unset=>single panel, set=>dual panel
LCD_Inverted # 1 ; Added to support LCD palette inversion. 0=normal, 1=inverted. Note that the inversion is invisible to apps.
! 0, "LCD_Active flag byte held at ":CC::STR:(LCD_Active)
]
[ HAL
AlignSpace
HAL_EntryTable # 4
HAL_WsSize # 4
ICache_Info # 0
ICache_NSets # 4
ICache_Size # 4
ICache_LineLen # 1
ICache_Associativity # 1
Cache_Type # 1
Cache_Flags # 1
DCache_Info # 4
DCache_NSets # 4
DCache_Size # 4
DCache_LineLen # 1
DCache_Associativity # 1
]
[ StrongARM
ProcessorType # 1 ; Processor type (handles 600 series onwards)
......@@ -1075,7 +1132,8 @@ ProcVec_End # 0
ProcVecPreVeneersSize * 4*4 ; Space for preveneers for loading handler addresses from 0 page.
ProcVecPreVeneers # ProcVecPreVeneersSize
ASSERT @ = &300
ASSERT @ <= &300
# (&300-@)
Export_DebuggerSpace # 16*8 ; Debugger module needs some zero page
[ E2ROMSupport
......@@ -1497,11 +1555,19 @@ OffsetLogicalToPhysical * TopOfDMAPhysRAM - TopOfDMAWorkSpace
SoundWorkSpaceSize * &1000
[ HAL32
SoundDMABufferSize * &1000
|
Export_SoundDMABufferSize * &1000
ASSERT Export_SoundDMABufferSize = SoundDMABufferSize
]
SoundEvtSize * &1000
[ HAL32
SoundDMABuffers |#| SoundDMABufferSize * 2
SoundWorkSpace |#| SoundWorkSpaceSize + SoundEvtSize
|
Export_SoundDMABuffers |#| SoundDMABufferSize * 2
ASSERT Export_SoundDMABuffers = SoundDMABuffers
ASSERT ?Export_SoundDMABuffers = ?SoundDMABuffers
......@@ -1509,6 +1575,7 @@ Export_SoundDMABuffers |#| SoundDMABufferSize * 2
Export_SoundWorkSpace |#| SoundWorkSpaceSize + SoundEvtSize
ASSERT Export_SoundWorkSpace = SoundWorkSpace
ASSERT ?Export_SoundWorkSpace = ?SoundWorkSpace
]
; Cursor
......@@ -1527,7 +1594,9 @@ Export_SvcTable |#| &400
ASSERT Export_SvcTable = SvcTable
ASSERT ?Export_SvcTable = ?SvcTable
[ :LNOT: HAL32
ASSERT SvcTable = &01F033FC ; Required for SVC table pokers, 1.20 compatible
]
[ No26bitCode
SWIDespatch_Size * 33*4
|
......@@ -1595,14 +1664,22 @@ IRQSTK # 0 ; Overflow will give abort
; High system workspace
; *****************************************************************************
[ HAL32
^ SVCStackAddress
|
^ SysHeapChunkAddress
]
# SVCStackSize ; svcstk size. Overflow will give abort
Export_SVCSTK # 0
ASSERT Export_SVCSTK = SVCSTK
ASSERT ?Export_SVCSTK = ?SVCSTK
[ HAL32
Export_SysHeapStart * SysHeapAddress
|
Export_SysHeapStart # 0
]
ASSERT Export_SysHeapStart = SysHeapStart
ASSERT ?Export_SysHeapStart = ?SysHeapStart
......
hdr/KeyWS
View file @ 49836a59
......@@ -46,20 +46,6 @@ LastLED # 1 ; last request for LED change, so we don
MouseType # 1 ; current pointer device type
MousePresent # 1 ; mouse detected
[ Keyboard_Type = "A1A500"
JustGotKbId # 1
RequestMouse # 1
RequestLED # 1
RequestSPD # 1
RequestKbId # 1
SPDRec # 1 ; number to be received
ResetState # 1 ; next thing to go in reset handshake
KeyRow # 1 ; half received key up or down
Reply # 1 ; next reply to be sent (&FF if nowt)
KbIdHalf # 1
MouseCount # 1 ; 0 => X next, 1 => Y next
MouseDelta # 2 ; delta X,Y
]
# 3 :AND: (- :INDEX: @)
......@@ -71,14 +57,6 @@ MouseXMult # 4
MouseYMult # 4
KeyVec # 4
[ Keyboard_Type = "A1A500"
SPDinput # 4
SPDoutput # 4
[ AssemblePointerV
MouseXCount # 4
MouseYCount # 4
]
]
MouseBounds # 16
MouseBoundLCol * MouseBounds+0
......@@ -100,58 +78,47 @@ UserKeyWorkSpace # UserKeyWorkSpaceSize
; PMF -> VDU communication stuff put in here because both VDU and PMF
; 'GET' this file
GBLA ExtEntries
ExtEntries SETA 0
MACRO
AddExtEntry $EntryName
Index_$EntryName * ExtEntries
[ AssemblingArthur
Value_$ExtEntries * $EntryName
|
[ DoingVdu
Value_$ExtEntries * $EntryName
]
]
ExtEntries SETA ExtEntries +1
MEND
MACRO
$Table OutputExternals
$Table
LCLA count
count SETA 0
WHILE count < ExtEntries
& Value_$count - $Table -4
count SETA count + 1
WEND
MEND
; GBLA ExtEntries
;ExtEntries SETA 0
;
; MACRO
; AddExtEntry $EntryName
;Index_$EntryName * ExtEntries
;Value_$ExtEntries * $EntryName
;ExtEntries SETA ExtEntries +1
; MEND
;
; MACRO
;$Table OutputExternals
;$Table
; LCLA count
;count SETA 0
; WHILE count < ExtEntries
; & Value_$count - $Table -4
;count SETA count + 1
; WEND
; MEND
MACRO
ByteToNosbod $EntryName
[ AssemblingArthur
VDWS WsPtr
BL $EntryName
|
MOV R0, #Index_$EntryName
BL ByteToNosbod
]
MEND
AddExtEntry DoReadPOSVPOSI
AddExtEntry DoReadPOSVPOSO
AddExtEntry DoOSBYTE87
AddExtEntry DoResetFont
AddExtEntry DoReadFont
AddExtEntry DoReadVDUStatus
AddExtEntry DoReadVDUVariable
AddExtEntry DoReadPalette
AddExtEntry DoSetPalette
AddExtEntry DoPointerStuff
AddExtEntry DoSetScreenStart
AddExtEntry DoSetDriverBank
AddExtEntry DoSetDisplayBank
AddExtEntry DoOsbyte163_242
AddExtEntry DoOsWord13
; AddExtEntry DoReadPOSVPOSI
; AddExtEntry DoReadPOSVPOSO
; AddExtEntry DoOSBYTE87
; AddExtEntry DoResetFont
; AddExtEntry DoReadFont
; AddExtEntry DoReadVDUStatus
; AddExtEntry DoReadVDUVariable
; AddExtEntry DoReadPalette
; AddExtEntry DoSetPalette
; AddExtEntry DoPointerStuff
; AddExtEntry DoSetScreenStart
; AddExtEntry DoSetDriverBank
; AddExtEntry DoSetDisplayBank
; AddExtEntry DoOsbyte163_242
; AddExtEntry DoOsWord13
END
hdr/PublicWS
View file @ 49836a59
......@@ -78,6 +78,13 @@ VduDriverWorkSpace # &3000
^ &00004000
ScratchSpace # &4000
[ HAL32
SVCSTK * &FA208000
SysHeapStart * &FB404000
^ &FAFF33FC
SvcTable # &400
BranchToSWIExit # 4
|
^ &01C02000
SVCSTK # 0
......@@ -97,6 +104,7 @@ SoundDMABufferSize * &1000
^ &01F06000
SoundDMABuffers # SoundDMABufferSize * 2
]
OPT OldOpt
......
s/AMBControl/Memory
View file @ 49836a59
......@@ -22,7 +22,7 @@
; fragment less often.
XROS_Module ENTRY
XROS_Module Entry
TEQ R0,#6
TEQNE R0,#7
TEQNE R0,#13
......
s/ARM600
View file @ 49836a59
......@@ -17,9 +17,6 @@
GBLL DebugAborts
DebugAborts SETL {FALSE}
[ Simulator
! 0, "**** Warning - IOMD Simulator debugging included - will crash on real thing! ****"
]
; MMU interface file - ARM600 version
......@@ -81,6 +78,7 @@ DebugAborts SETL {FALSE}
; Fixed page allocation is as follows
^ 0
[ :LNOT: HAL
DRAMOffset_CursorChunk # 32*1024 ; ie on MEMC1 this is the last 32K of DAG-addressable memory
DRAMOffset_PageZero # 32*1024 ; 32K at location zero
DRAMOffset_SystemHeap # 32*1024 ; system heap/svc stack
......@@ -90,6 +88,7 @@ DRAMOffset_AbortStack # 8*1024
AlignSpace 16*1024 ; L1PT (and hence L2PT) must be 16K-aligned
DRAMOffset_L2PT # 0 ; static L2PT (variable size, with embedded L1PT)
DRAMOffset_L1PT * DRAMOffset_L2PT + 48*1024
]
; Undefined stack memory (size 8K) starts immediately after end of L2PT (which is variable size)
; Soft CAM map (variable size) starts immediately after end of UndStack
......@@ -98,8 +97,10 @@ StaticPagesSize * @
; Logical addresses are as follows
[ :LNOT: HAL
L2PT * &02C00000 ; size 256K
L1PT * &02C0C000 ; in the middle of L2PT, where the mapping for 03000000 to 03FFFFFF would be
]
FixedAreasL2Size * 96*1024 ; amount of L2 to cover fixed areas, excluding free pool
......@@ -195,7 +196,7 @@ SixteenMByte EQU (1024*1024 * 16)
; out: All registers preserved, operation ignored if illegal
;
SetDAG ENTRY "r0-r1,r12"
SetDAG Entry "r0-r1,r12"
MOV r12, #IOMD_Base
CMP r1, #1
BEQ %FT10
......@@ -664,6 +665,7 @@ SSETMEMC ROUT
WritePSRc SVC_mode+I_bit, r11
ExitSWIHandler
[ :LNOT: HAL
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; ClearPhysRAM - Routine to clear "all" memory
......@@ -853,17 +855,13 @@ lastregion SETA lastregion +1
; Tim says "Yuk, yuk, yuk!!"
RamSkipTable
[ ClearPhysRAMspeedup ; allow some workspace to speed up ClearPhysRAM Mike says whoosh
MakeSkipTable 1, DRAMOffset_PageZero + 0, 64 ; skip 1st 32 bytes of LogRAM, so IRQs work!
; additional 32 bytes for workspace
|
MakeSkipTable 1, DRAMOffset_PageZero + 0, 32 ; skip 1st 32 bytes of LogRAM, so IRQs work!
]
MakeSkipTable 1, DRAMOffset_PageZero + 0, InitWsEnd - ZeroPage ; skip 1st n bytes of LogRAM, so IRQs work!
MakeSkipTable 1, DRAMOffset_PageZero + SkippedTables, SkippedTablesEnd-SkippedTables
MakeSkipTable 1, DRAMOffset_L2PT, DRAMOffset_PageZero + L2PTSize - DRAMOffset_L2PT
EndSkipTables
ASSERT DRAMOffset_PageZero + L2PTSize < DRAMOffset_L2PT
]
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -1188,10 +1186,6 @@ MedusaInit
MOV r0, #&12 ; 5-3 cycle ROM access
|
[ Simulator
MOV r0, #IOMD_ROMCR_62 + IOMD_ROMCR_BurstOff ; make faster for simulation (no point in burst mode, it's
; no faster than the fastest initial speed)
|
[ RISCPCBurstMode
[ 1 = 1
ReadCop r0, CR_ID
......@@ -1208,7 +1202,6 @@ MedusaInit
|
MOV r0, #IOMD_ROMCR_156 + IOMD_ROMCR_BurstOff ; initialise ROM speed to 156.25ns (changed from 187ns 21-Jan-94)
]
]
] ;RO371Timings conditional
......@@ -1255,7 +1248,7 @@ CommonInit
; In both cases we want to end up in 32-bit config with MMU off, in 32-bit mode
SetMode SVC32_mode, r1, r0 ; try to select SVC32 mode
mrs AL, r2, CPSR ; read back PSR
MRS r2, CPSR ; read back PSR
AND r2, r2, #&1F ; extract mode bits from PSR we tried to modify
TEQ r2, #SVC32_mode ; and see if we made it into SVC32
BEQ %FT05 ; [we made it so must be a Break]
......@@ -1287,6 +1280,9 @@ CommonInit
; can't clash as IOMD only goes up to 2000 0000 and our physical mapping is above that).
05
[ HAL
! 0, "Sort out Break"
|
MOV r0, #0
LDR r0, [r0, #DRAMPhysAddrA] ; get address of 1st DRAM bank
LDR r1, =PhysSpace + DRAMOffset_L1PT ; offset to start of L1
......@@ -1307,6 +1303,7 @@ CommonInit
SUB r0, r0, #ROM ; form RAM-ROM offset
ADD pc, pc, r0 ; jump to RAM code (when we get onto IOMD, we'll have to be in 32-bit mode)
NOP ; this instruction will be skipped
]
; we're now in RAM, so it's safe to turn the MMU off, but leave us in 32-bit config (and 32-bit mode)
......@@ -1620,7 +1617,8 @@ NoDRAMPanic
; Now go back and put the VRAM information in, and also program VIDCR and VIDCUR
STR r6, [r12, #VRAMWidth] ; store width of VRAM (0,1 or 2)
[ :LNOT:HAL
STRB r6, [r12, #VRAMWidth] ; store width of VRAM (0,1 or 2)
MOV r14, #IOMD_Base
STRB r1, [r14, #IOMD_VIDCR]
STR r0, [r14, #IOMD_VIDCUR] ; set up VIDCUR to start of video RAM
......@@ -1634,25 +1632,18 @@ NoDRAMPanic
MOV r4, r6, LSL #20 ; convert amount of VRAM to bytes
STR r4, [r12, #VRAMSize] ; and store
]
ADD r2, r12, #VideoPhysAddr ; r2 -> Start of PhysRamTable
STMIA r2, {r0, r7} ; store video memory block
MemSizeTotalRAM
; Now we have to work out the total RAM size
[ Simulator
TubeString r4, r5, r6, "Address Size"
]
MOV r1, #0
MOV r7, r2
40
LDMIA r7!, {r4, r5} ; get address, size
ADD r1, r1, r5 ; add on size
[ Simulator
TubeDumpNoStack r4, r6, r8, r9
TubeDumpNoStack r5, r6, r8, r9
TubeNewlNoStack r6, r8
]
TEQ r7, r3
BNE %BT40
......@@ -1677,6 +1668,7 @@ MemSizeTotalRAM
STMCCIA r3!, {r6, r7}
BCC %BT57
[ :LNOT: HAL
; Now set up L1 + L2
; - first work out how big static L2 needs to be
; - then zero L1 + L2 (L1 is actually inside L2)
......@@ -1699,13 +1691,11 @@ MemSizeTotalRAM
MOV r10, r5
MOV r11, r5
MOV r12, r5
[ :LNOT: Simulator ; don't bother zeroing L1/2 for Mark
ADD r2, r2, r3 ; start at end and work back
60
STMDB r2!, {r5-r12}
SUBS r3, r3, #8*4
BNE %BT60
]
; r2 ends up pointing at L2
......@@ -1883,12 +1873,10 @@ CritEnd ; 2 words after we go up into RO
ORR r2, r2, r0
MOV r0, #4*1024 ; r0 = true page size (now split off
; from MEMC control register)
[ Simulator
TubeString r4, r5, r6, "Got through all of MemSize, and we're still here!"
TubeChar r4, r5, "MOV r5, #4", NoStack
]
MOV pc, r13
] ; :LNOT: HAL
; add_dram_bank
; Entry: r10 -> workspace (initially 0)
; r0 = bank address
......@@ -2173,6 +2161,7 @@ MemInitTable ; sz, U, C, B, logaddr, (ap, (physaddr))
; Now explicit initialisation of L2 for static pages
[ :LNOT: HAL
MemInitPagesL2 &8000, 0, 0, CursorChunkAddress, AP_Read, DRAMOffset_CursorChunk ;but see L1L2PTenhancements
MemInitPagesL2 &8000, 1, 1, &00000000, AP_Full, DRAMOffset_PageZero
MemInitPagesL2 &8000, 1, 1, SysHeapChunkAddress, AP_Full, DRAMOffset_SystemHeap
......@@ -2192,6 +2181,7 @@ MemInitTable ; sz, U, C, B, logaddr, (ap, (physaddr))
]
MemInitPagesL2 -1, 1, 1, UndStackSoftCamChunk, AP_Full, 0 ; variable offset and size
]
& 0, 0, 0 ; terminate table
......@@ -2562,7 +2552,7 @@ MMUCReason_ModifyControl # 1 ; reason code 0
MMUCReason_Flush # 1 ; reason code 1
MMUCReason_Unknown # 0
MMUControlSWI ENTRY
MMUControlSWI Entry
BL MMUControlSub
PullEnv
ORRVS lr, lr, #V_bit
......@@ -2773,21 +2763,21 @@ UndPreVeneer ROUT
; for the time being just merge lr and psr
mrs AL, r1, SPSR ; r1 = saved PSR
MRS r1, SPSR ; r1 = saved PSR
AND r2, r1, #&F0000003 ; get saved NZCV and 26 bit modes
ORR lr_undef, lr_undef, r2
AND r2, r1, #I32_bit + F32_bit ; extract I and F from new place
ORR r1, lr_undef, r2, LSL #IF32_26Shift ; r1 = combined lr and psr
mrs AL, r2, CPSR ; now switch into SVC26
MRS r2, CPSR ; now switch into SVC26
BIC r3, r2, #&1F
ORR r3, r3, #SVC26_mode
msr AL, SPSR_cxsf, r3 ; set SPSR_undef to be CPSR but with SVC26
msr AL, CPSR_c, r3 ; and select this mode now
MSR SPSR_cxsf, r3 ; set SPSR_undef to be CPSR but with SVC26
MSR CPSR_c, r3 ; and select this mode now
MOV lr_svc, r1 ; lr_svc = PC + PSR from exception
msr AL, CPSR_c, r2 ; go back into undef mode
MSR CPSR_c, r2 ; go back into undef mode
LDR r1, =UndHan ; work out address of undefined instruction handler
LDR r1, [r1]
......@@ -2806,7 +2796,7 @@ PAbPreVeneer ROUT
; for the time being just merge lr and psr
mrs AL, r1, SPSR ; r1 = saved PSR
MRS r1, SPSR ; r1 = saved PSR
LDR r2, =Abort32_dumparea
STMIA r2, {r1,lr_abort} ;dump 32-bit PSR, fault address (PC)
......@@ -2817,10 +2807,10 @@ PAbPreVeneer ROUT
AND r2, r1, #I32_bit + F32_bit ; extract I and F from new place
ORR r1, lr_abort, r2, LSL #IF32_26Shift ; r1 = combined lr and psr
mrs AL, r2, CPSR ; now switch into SVC26
MRS r2, CPSR ; now switch into SVC26
BIC r2, r2, #&1F
ORR r2, r2, #SVC26_mode
msr AL, CPSR_c, r2
MSR CPSR_c, r2
MOV lr_svc, r1 ; lr_svc = PC + PSR from exception
LDR r1, =PAbHan
......@@ -2848,8 +2838,8 @@ DAbPreVeneer ROUT
STMIA r13_abort, {r0-r7} ; save unbanked registers anyway
STR lr_abort, [r13_abort, #15*4] ; save old PC, ie instruction address
mrs AL, r0, SPSR ; r0 = PSR when we aborted
mrs AL, r1, CPSR ; r1 = CPSR
MRS r0, SPSR ; r0 = PSR when we aborted
MRS r1, CPSR ; r1 = CPSR
ADD r2, r13_abort, #8*4 ; r2 -> saved register bank for r8 onwards
LDR r4, =Abort32_dumparea+3*4 ;use temp area (avoid overwriting main area for expected aborts)
......@@ -2870,22 +2860,22 @@ DAbPreVeneer ROUT
BEQ %FT05
ORR r3, r3, r1 ; and put in user's
msr AL, CPSR_c, r3 ; switch to user's mode
MSR CPSR_c, r3 ; switch to user's mode
STMIA r2, {r8-r14} ; save the banked registers
mrs AL, r5, SPSR ; get the SPSR for the aborter's mode
MRS r5, SPSR ; get the SPSR for the aborter's mode
STR r5, [r2, #8*4] ; and store away in the spare slot on the end
; (this is needed for LDM with PC and ^)
[ No26bitCode
ORR r1, r1, #ABT32_mode
msr AL, CPSR_c, r1 ; back to abort mode for the rest of this
MSR CPSR_c, r1 ; back to abort mode for the rest of this
05
Push "r0" ; save SPSR_abort
|
05
ORR r1, r1, #SVC26_mode ; then switch to SVC for the rest of this
msr AL, CPSR_c, r1
MSR CPSR_c, r1
Push "r0, lr_svc" ; save SPSR_abort and lr_svc
]
......@@ -3255,14 +3245,14 @@ DAbPreVeneer ROUT
[ No26bitCode
Pull "r0" ; r0 = (possibly updated) SPSR_abort
mrs AL, r1, CPSR
MRS r1, CPSR
|
Pull "r0, lr" ; r0 = (possibly updated) SPSR_abort, restore lr_svc
SetMode ABT32_mode, r1 ; leaves r1 = current PSR
]
mrs AL, r6, SPSR ; get original SPSR, with aborter's original mode
MRS r6, SPSR ; get original SPSR, with aborter's original mode
AND r7, r6, #&0F
TEQ r7, #USR26_mode ; also matches USR32
LDMEQIA r2, {r8-r14}^ ; if user mode then just use ^ to reload registers
......@@ -3271,13 +3261,13 @@ DAbPreVeneer ROUT
ORR r6, r6, #I32_bit ; use aborter's flags and mode but set I
BIC r6, r6, #T32_bit ; and don't set Thumb bit
msr AL, CPSR_c, r6 ; switch to aborter's mode
MSR CPSR_c, r6 ; switch to aborter's mode
LDMIA r2, {r8-r14} ; reload banked registers
msr AL, CPSR_c, r1 ; switch back to ABT32
MSR CPSR_c, r1 ; switch back to ABT32
80
LDR lr_abort, [r13_abort, #15*4] ; get PC to return to
msr AL, SPSR_cxsf, r0 ; set up new SPSR (may have changed for LDM {PC}^)
MSR SPSR_cxsf, r0 ; set up new SPSR (may have changed for LDM {PC}^)
LDMIA r13_abort, {r0-r7} ; reload r0-r7
[ No26bitCode
......@@ -3315,9 +3305,9 @@ DAbPreVeneer ROUT
NOP ; don't access banked registers after LDM^
ADD sp, sp, #9*4 ; junk user bank stack frame + saved SPSR
mrs AL, r1, CPSR
MRS r1, CPSR
mrs AL, r6, SPSR ; get original SPSR, with aborter's original mode
MRS r6, SPSR ; get original SPSR, with aborter's original mode
AND r7, r6, #&0F
TEQ r7, #USR26_mode ; also matches USR32
LDMEQIA r2, {r8-r14}^ ; if user mode then just use ^ to reload registers
......@@ -3326,9 +3316,9 @@ DAbPreVeneer ROUT
ORR r6, r6, #I32_bit ; use aborter's flags and mode but set I
BIC r6, r6, #T32_bit ; and don't set Thumb
msr AL, CPSR_c, r6 ; switch to aborter's mode
MSR CPSR_c, r6 ; switch to aborter's mode
LDMIA r2, {r8-r14} ; reload banked registers
msr AL, CPSR_c, r1 ; switch back to ABT32
MSR CPSR_c, r1 ; switch back to ABT32
80
STR r0, [r13_abort, #16*4] ; save handler address at top of stack
......@@ -3406,7 +3396,7 @@ LargePageSize * 1 :SHL: LargePageSizeShift
SmallPageSizeShift * 12
SmallPageSize * 1 :SHL: SmallPageSizeShift
ProcessTransfer ENTRY "r1-r7,r12"
ProcessTransfer Entry "r1-r7,r12"
[ DebugAborts
DLINE "ProcessTransfer entered"
......@@ -3831,12 +3821,21 @@ ARMA_IMBrange_threshold * 128*1024
; - the clean is either whole cache or range as appropriate
;
SyncCodeAreasSWI ROUT
Push "lr"
BL SyncCodeAreas
Pull "lr" ; no error return possible
B SLVK
SyncCodeAreas
TST R0,#1 ; range variant of SWI?
BEQ SyncCodeAreasFull
SyncCodeAreasRange
ARM_read_ID R10
AND R10,R10,#&F000
CMP R10,#&A000
BNE SLVK ;not StrongARM
TST R0,#1 ;range variant of SWI?
BEQ %FT01
MOVNE PC,LR ;not StrongARM
MOV R11,R1 ;R11 := low address (inclusive)
ADD R12,R2,#4 ;R12 := high address (exclusive)
SUB R12,R12,R11
......@@ -3849,13 +3848,19 @@ SyncCodeAreasSWI ROUT
MOV R0,R0 ;NOPs to ensure 4 instructions after IC flush before return
MOV R0,R0
MOV R0,R0
B SLVK
01 ;full IMB required
LDR R12,=SyncCodeA_sema
MOV PC,LR
SyncCodeAreasFull
ARM_read_ID R10
AND R10,R10,#&F000
CMP R10,#&A000
MOVNE PC,LR ;not StrongARM
01 LDR R12,=SyncCodeA_sema
MOV R10,#1 ;set semaphore
SWPB R11,R10,[R12]
CMP R11,#0 ;was it already set?
BNE SLVK ;semaphore set, avoid reentrancy, let first call do it
MOVNE PC,LR ;semaphore set, avoid reentrancy, let first call do it
MOV R12,#ARMA_Cleaner_flipflop
LDR R11,[R12]
EOR R11,R11,#16*1024
......@@ -3866,7 +3871,7 @@ SyncCodeAreasSWI ROUT
MOV R12,#0
STRB R12,[R12,#SyncCodeA_sema] ;reset semaphore
MOV R0,R0 ;NOP to ensure 4 instructions after IC flush before return
B SLVK
MOV PC,LR
LTORG
......
s/Arthur2
View file @ 49836a59
......@@ -1905,7 +1905,7 @@ VarFindIt Entry "r0,r1,r2,r5,r6,r7,r8,r9,r10,r11"
BNE %BT45
50
mrs HS, r10, CPSR ; preserve last HS result we got
MRSHS r10, CPSR ; preserve last HS result we got
MOVHS r11, r4
MOVLO r6, r5
55
......@@ -1925,7 +1925,7 @@ VarFindIt Entry "r0,r1,r2,r5,r6,r7,r8,r9,r10,r11"
]
MOVLS r4, r11
MOVHI r3, #0
msr LS, CPSR_f, r10
MSRLS CPSR_f, r10
[ DebugSysVars
SWI XOS_WriteS
......@@ -2091,7 +2091,7 @@ VarFindIt_QA ROUT
BNE %BT45
50
mrs HS, r10, CPSR ; preserve last HS result we got
MRSHS r10, CPSR ; preserve last HS result we got
MOVHS r11, r4
MOVLO r6, r5
55
......@@ -2113,7 +2113,7 @@ VarFindIt_QA ROUT
MOV r7, r6
MOVLS r6, r11
MOVHI r5, #0
msr LS, CPSR_f, r10
MSRLS CPSR_f, r10
TOGPSR Z_bit, lr
99
......
s/Arthur3
View file @ 49836a59
......@@ -1268,7 +1268,7 @@ Config_$name._table
; Exit : R2 -> table entry, EQ for not found
; R0 stepped on
FindOption ENTRY "r1, r3-r5"
FindOption Entry "r1, r3-r5"
ADRL r2, Config_Table+1
04
MOV r1, #0 ; offset
......@@ -1449,7 +1449,7 @@ BadConOptError
= "BadConOpt:Bad configure option", 0
ALIGN
ReadNumParm ENTRY "r1"
ReadNumParm Entry "r1"
10
LDRB r2, [r0], #1
CMP r2, #" "
......@@ -1467,7 +1467,7 @@ ReadNumParm ENTRY "r1"
; returns R2 = number or -1 for Auto
; R0 -> terminator
ReadNumAuto ENTRY "r1,r3,r4"
ReadNumAuto Entry "r1,r3,r4"
10
LDRB r2, [r0], #1
CMP r2, #" "
......@@ -1795,6 +1795,7 @@ ExitShow
; status bits :
ALIGN
20
ADD r0, r2, #1 ; got to do *status on a NoParm or Special
21
......@@ -1958,7 +1959,7 @@ AlternateTab
; read byte from CMOS RAM : info word in R0, byte -> R1
ReadByte ENTRY "r0, r2"
ReadByte Entry "r0, r2"
MOV r1, r0, LSR #16 ; get bytoff
AND r1, r1, #&FF
MOV r0, #ReadCMOS
......@@ -1979,7 +1980,7 @@ GetValue EntryS "r1"
MOV r0, r1, LSR r0 ; ...then down again
EXITS
PrintR0 ENTRY "r1, r2"
PrintR0 Entry "r1, r2"
CMP r0, #-1
BNE %FT10
ADRL r0, AutoString
......@@ -2177,7 +2178,7 @@ ModeCMOSTable
;
; out: -
WriteMultiField ENTRY "r0-r5"
WriteMultiField Entry "r0-r5"
MOV r3, r0 ; pointer to where we're at in table
MOV r4, r2 ; value
10
......@@ -2201,7 +2202,7 @@ WriteMultiField ENTRY "r0-r5"
; in: r0 -> table
; out: r0 = value
ReadMultiField ENTRY "r1-r6"
ReadMultiField Entry "r1-r6"
LDR r6, [r0, #4] ; get maximum value allowed
ADD r3, r0, #2*4 ; pointer to where we're at in table (skip auto, max)
MOV r4, #0 ; cumulative value
......@@ -2246,7 +2247,7 @@ Config_WimpMode_showcode ROUT
ADR r0, WimpModeSpacedString
B ModeWimpModeShowCode
Read_Configd_Mode ENTRY
Read_Configd_Mode Entry
ADR r0, ModeCMOSTable
BL ReadMultiField
EXIT
......@@ -2391,7 +2392,7 @@ Config_MonitorType_showcode ROUT
ADD r2, r4, #4
B ExitShow
Read_Configd_MonitorType ENTRY
Read_Configd_MonitorType Entry
ADR r0, MonitorTypeCMOSTable
BL ReadMultiField
EXIT
......@@ -2421,12 +2422,12 @@ Config_Sync_showcode ROUT
ADD r2, r4, #4
B ExitShow
Read_Configd_Sync ENTRY
Read_Configd_Sync Entry
ADR r0, SyncCMOSTable
BL ReadMultiField
EXIT
SetUpPrinterBuffer ENTRY "r1-r3"
SetUpPrinterBuffer Entry "r1-r3"
MOV r0, #PrinterBufferCMOS
BL Read
MOV r2, #0
......
s/ArthurSWIs
View file @ 49836a59
......@@ -37,7 +37,7 @@
; Out VC : r1 -> first unused char, r2 = number
; VS : r1 unchanged, r2 = 0, current error block set
ReadUnsigned_Routine ENTRY "r0-r1, r3-r4, r9"
ReadUnsigned_Routine Entry "r0-r1, r3-r4, r9"
WritePSRc SVC_mode, r9
......@@ -143,7 +143,7 @@ ReadUnsigned_Routine ENTRY "r0-r1, r3-r4, r9"
; Out VC : Number read in r2, r1 updated. r3 = number of chars used
; VS : r1 preserved, r2 -> error block
ReadNumberInBase ENTRY "r0, r1, r12"
ReadNumberInBase Entry "r0, r1, r12"
MOV r2, #0 ; Result
MOV r3, #0 ; Number of valid digits read
......@@ -204,7 +204,7 @@ ReadNumberInBase ENTRY "r0, r1, r12"
; Out EQ -> r0 = valid number in [0..base-1], r1++
; NE -> r0 invalid, r1 same
GetCharForReadNumber ENTRY
GetCharForReadNumber Entry
LDRB r0, [r1]
CMP r0, #"0"
......@@ -270,11 +270,11 @@ VecInitLoop
CallVector ROUT
[ No26bitCode
mrs AL, r12, CPSR
MRS r12, CPSR
CMP r10, #NVECTORS
BHS CallVecTooHigh ; return - silly value
msr AL, CPSR_f, r12 ; put back caller's flags + int state
MSR CPSR_f, r12 ; put back caller's flags + int state
Push lr ; claimed return goes back to caller
|
CMP r10, #NVECTORS
......@@ -302,7 +302,7 @@ CallVecLoop
Pull pc ; can't restore all flags. CV will be preserved
CallVecTooHigh
msr AL, CPSR_f, r12
MSR CPSR_f, r12
MOV pc, lr
|
Pull pc,,^ ; we don't expect to get to here
......@@ -589,9 +589,9 @@ defaultvectab
NaffVector ROUT
Def_100HZ
mrs AL, lr, CPSR
MRS lr, CPSR
BIC lr, lr, #V_bit
msr AL, CPSR_f, lr ; Clear V, preserve rest
MSR CPSR_f, lr ; Clear V, preserve rest
LDR pc, [sp], #4 ; Claim vector, do nowt
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
......@@ -1026,9 +1026,9 @@ display_post_postinit_calls
CallAVector_SWI ; R9 is the vector number (!!)
STR lr, [sp, #-4]! ; save caller PSR on stack
MOV R10, R9
msr ,CPSR_f, R12 ; restore caller CCs (including V)
MSR CPSR_f, R12 ; restore caller CCs (including V)
BL CallVector
mrs ,r10, CPSR ; restore CCs
MRS r10, CPSR ; restore CCs
LDR lr, [sp], #4
AND r10, r10, #&F0000000
BIC lr, lr, #&F0000000
......@@ -1108,7 +1108,7 @@ SysClaimFail
; R1 = SysHeapStart
;
FreeSysHeapNode ENTRY
FreeSysHeapNode Entry
MOV R0, #HeapReason_Free
LDR R1, =SysHeapStart
SWI XOS_Heap
......@@ -1130,11 +1130,11 @@ ValidateAddress_Code ROUT
LDR R12, [R10, #AplWorkSize]
BL RangeCheck
MOV r11, #SysHeapChunkAddress ; need to still check 1st 8K
LDR r11, =SysHeapChunkAddress ; need to still check 1st 8K
ADD r12, r11, #SysHeapStart-SysHeapChunkAddress
BL RangeCheck
MOV R11, #CursorChunkAddress
LDR R11, =CursorChunkAddress
ADD R12, R11, #32*1024
BL RangeCheck
......
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