Commit 2247d8e9 authored by Jeffrey Lee's avatar Jeffrey Lee
Browse files

Add zero page relocation support

Detail:
  A whole mass of changes to add high processor vectors + zero page relocation support to the Cortex branch of the kernel
  At the moment the code can only cope with two ZeroPage locations, &0 and &FFFF0000. But with a bit more tweaking those restrictions can probably be lifted, allowing ZeroPage to be hidden at almost any address (assuming it's fixed at compile time). If I've done my job right, these restrictions should all be enforced by asserts.
  There's a new option, HiProcVecs, in hdr/Options to control whether high processor vectors are used. When enabling it and building a ROM, remember:
  * FPEmulator needs to be built with the FPEAnchor=High option specified in the components file (not FPEAnchorType=High as my FPEmulator commit comments suggested)
  * ShareFS needs unplugging/removing since it can't cope with it yet
  * Iyonix users will need to use the latest ROOL boot sequence, to ensure the softloaded modules are compatible (OMAP, etc. don't really softload much so they're OK with older sequences)
  * However VProtect also needs patching to fix a nasty bug there - http://www.riscosopen.org/tracker/tickets/294
  The only other notable thing I can think of is that the ProcessTransfer code in s/ARM600 & s/VMSAv6 is disabled if high processor vectors are in use (it's fairly safe to say that code is obsolete in HAL builds anyway?)
  Fun challenge for my successor: Try setting ZeroPage to &FFFF00FF (or similar) so its value can be loaded with MVN instead of LDR. Then use positive/negative address offsets to access the contents.
  File changes:
  - hdr/ARMops - Modified ARMop macro to take the ZeroPage pointer as a parameter instead of 'zero'
  - hdr/Copro15ops - Corrected $quick handling in myISB macro
  - hdr/Options - Added ideal setting for us to use for HiProcVecs
  - s/AMBControl/allocate, s/AMBControl/growp, s/AMBControl/mapslot, s/AMBControl/memmap, s/AMBControl/service, s/AMBControl/shrinkp, s/Arthur2, s/Arthur3, s/ArthurSWIs, s/ChangeDyn, s/ExtraSWIs, s/HAL, s/HeapMan, s/Kernel, s/MemInfo, s/Middle, s/ModHand, s/MoreSWIs, s/MsgCode, s/NewIRQs, s/NewReset, s/Oscli, s/PMF/buffer, s/PMF/IIC, s/PMF/i2cutils, s/PMF/key, s/PMF/mouse, s/PMF/osbyte, s/PMF/oseven, s/PMF/osinit, s/PMF/osword, s/PMF/oswrch, s/SWINaming, s/Super1, s/SysComms, s/TickEvents, s/Utility, s/vdu/vdu23, s/vdu/vdudriver, s/vdu/vdugrafl, s/vdu/vdugrafv, s/vdu/vdupalxx, s/vdu/vdupointer, s/vdu/vduswis, s/vdu/vduwrch - Lots of updates to deal with zero page relocation
  - s/ARM600 - UseProcessTransfer option. Zero page relocation support. Deleted pre-HAL ClearPhysRAM code to tidy the file up a bit.
  - s/ARMops - Zero page relocation support. Set CPUFlag_HiProcVecs when high vectors are in use.
  - s/KbdResPC - Disable compilation of dead code
  - s/VMSAv6 - UseProcessTransfer option. Zero page relocation support.
Admin:
  Tested with OMAP & Iyonix ROM softloads, both with high & low zero page.
  High zero page hasn't had extensive testing, but boot sequence + ROM apps seem to work.


Version 5.35, 4.79.2.98.2.48. Tagged as 'Kernel-5_35-4_79_2_98_2_48'
parent 26a09556
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.98.2.47"
Module_Date SETS "07 Aug 2011"
Module_ApplicationDate SETS "07-Aug-11"
Module_MinorVersion SETS "4.79.2.98.2.48"
Module_Date SETS "08 Aug 2011"
Module_ApplicationDate SETS "08-Aug-11"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.98.2.47)"
Module_HelpVersion SETS "5.35 (07 Aug 2011) 4.79.2.98.2.47"
Module_FullVersion SETS "5.35 (4.79.2.98.2.48)"
Module_HelpVersion SETS "5.35 (08 Aug 2011) 4.79.2.98.2.48"
END
......@@ -5,19 +5,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.98.2.47
#define Module_Date_CMHG 07 Aug 2011
#define Module_MinorVersion_CMHG 4.79.2.98.2.48
#define Module_Date_CMHG 08 Aug 2011
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.98.2.47"
#define Module_Date "07 Aug 2011"
#define Module_MinorVersion "4.79.2.98.2.48"
#define Module_Date "08 Aug 2011"
#define Module_ApplicationDate "07-Aug-11"
#define Module_ApplicationDate "08-Aug-11"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.98.2.47)"
#define Module_HelpVersion "5.35 (07 Aug 2011) 4.79.2.98.2.47"
#define Module_FullVersion "5.35 (4.79.2.98.2.48)"
#define Module_HelpVersion "5.35 (08 Aug 2011) 4.79.2.98.2.48"
#define Module_LibraryVersionInfo "5:35"
......@@ -66,27 +66,27 @@ CPUFlag_HiProcVecs * 1:SHL:20 ; High processor vectors are in
; The macro to do an ARM operation. All ARM operations are expected
; to corrupt a1 only
; This macro corrupts ip unless $zero reg is supplied
; This macro corrupts ip unless $zeropage reg is supplied
MACRO
ARMop $op, $cond, $tailcall, $zero
[ "$zero" = ""
MOV$cond ip, #ZeroPage
ARMop $op, $cond, $tailcall, $zeropage
[ "$zeropage" = ""
LDR$cond ip, =ZeroPage
]
[ "$tailcall" = ""
MOV$cond lr, pc
]
[ "$zero" = ""
[ "$zeropage" = ""
LDR$cond pc, [ip, #Proc_$op]
|
LDR$cond pc, [$zero, #Proc_$op]
LDR$cond pc, [$zeropage, #Proc_$op]
]
MEND
MACRO
ChangedProcVecs $tmp
[ XScaleJTAGDebug
MOV $tmp, #0
LDR $tmp, =ZeroPage
LDR $tmp, [$tmp, #ProcessorFlags]
TST $tmp, #CPUFlag_XScaleJTAGconnected
BEQ %FT01
......
......@@ -572,7 +572,7 @@ C15 CN 15
|
[ NoARMv7
; ARMv6, use legacy MCR op
[ "$quick"="q"
[ "$quick"=""
MOV$cond $temp,#0
]
MCR$cond p15,0,$temp,c7,c5,4
......
......@@ -357,7 +357,9 @@ GetMessages SETS ""
]
GBLL HiProcVecs ; Relocate processor vectors and first 16K of workspace to &FFFF0000
HiProcVecs SETL {FALSE} ; Coming soon!
HiProcVecs SETL {FALSE} ; Leave off for now
; In an ideal world, we'd use something like this:
; HiProcVecs SETL M_Tungsten :LOR: :LNOT: NoARMv6
GBLL DebugForcedReset ; debug forced hard resets
DebugForcedReset SETL {FALSE}
......
......@@ -64,7 +64,7 @@ allocate
STR R4,[R2,#AMBNode_Npages] ;number of pages = 0 (so far)
MOV R4,#ApplicationStart
STR R4,[R2,#AMBNode_startaddr]
LDR R4,=AppSpaceDANode
LDR R4,=ZeroPage+AppSpaceDANode
LDR R4,[R4,#DANode_Flags]
AND R4,R4,#&7F
STR R4,[R2,#AMBNode_PPL] ;PPL from bottom 8 bits of DA flags
......
......@@ -34,8 +34,8 @@ growpages ROUT
MOV R0,R2 ;R0 -> AMB node
LDR R1,=FreePoolDANode ;R1 := source for pages
LDR R2,=AppSpaceDANode ;R2 := dest for pages
LDR R1,=ZeroPage+FreePoolDANode ;R1 := source for pages
LDR R2,=ZeroPage+AppSpaceDANode ;R2 := dest for pages
LDR R7,[R0,#AMBNode_Npages] ;R7 := current no. of pages
SUB R3,R6,R7 ;no. of pages required from FreePool
......@@ -88,7 +88,7 @@ growpages ROUT
LDR R5,[R2,#DANode_Size]
ADD R5,R5,R3,LSL #Log2PageSize
STR R5,[R2,#DANode_Size] ;new AppSpace size
MOV R6,#0
LDR R6,=ZeroPage
STR R5,[R6,#MemLimit] ;update MemLimit
02
......@@ -115,7 +115,7 @@ growp_TryToShrinkShrinkables ROUT
MOV R11,R1 ; -> FreePool DANode
MOV R1,R3,LSL #Log2PageSize ;amount we need in FreePool
MOV R2,R4,LSL #Log2PageSize ;amount we have in FreePool
MOV R10,#DAList
LDR R10,=ZeroPage+DAList
ASSERT DANode_Link = 0 ;because DAList has only link
10
LDR R10,[R10,#DANode_Link] ;and load next
......
......@@ -58,7 +58,7 @@ AMBControl_Init
STR R0,[R2]
;claim block for PhysBin array
LDR R3,=MaxCamEntry
LDR R3,=ZeroPage+MaxCamEntry
LDR R3,[R3]
ADD R3,R3,#1 ;no. of RAM pages extant
MOV R3,R3,LSR #AMBPhysBinShift ;no. of bin entries reqd.
......@@ -69,7 +69,7 @@ AMBControl_Init
STR R2,AMBPhysBin
;init PhysBin
MOV R0,#PhysRamTable
LDR R0,=ZeroPage+PhysRamTable
LDR R3,AMBPhysBin
LDR R4,AMBPhysBinEntries
LDMIA R0!,{R1,R2} ;address,size of first physical fragment
......@@ -90,7 +90,7 @@ AMBControl_Init
STR R1,[R1,#AMBNode_prev] ;anchor prev initially -> anchor (empty list)
STR R1,[R1,#AMBNode_next] ;anchor next initially -> anchor (empty list)
[ AMB_LazyMapIn
MOV R0,#0
LDR R0,=ZeroPage
LDR R0,[R0,#ProcessorFlags]
TST R0,#CPUFlag_BaseRestored
MOVEQ R1,#AMBFlag_LazyMapIn_disable ;laziness not supported if we can't trivially restart after abort (because we're lazy!)
......@@ -99,7 +99,7 @@ AMBControl_Init
MOVNE R1,#AMBFlag_LazyMapIn_disable
STR R1,AMBFlags
]
MOV R0,#AMBControl_ws
LDR R0,=ZeroPage+AMBControl_ws
STR R12,[R0] ;now initialisation is complete
Pull "R0-R4,R12,PC"
......@@ -114,7 +114,7 @@ AMBControl_Init
; other regs. depend on reason code
AMBControlSWI
MOV R12,#AMBControl_ws
LDR R12,=ZeroPage+AMBControl_ws
LDR R12,[R12]
AND R11,R0,#&FF
......
......@@ -121,12 +121,12 @@ ms_mapdone
;update AppSpace kernel stuff
LDR R2,[R1,#AMBNode_Npages]
LDR R3,=AppSpaceDANode
LDR R3,=ZeroPage+AppSpaceDANode
MOV R0,#ApplicationStart
CMP R5,#-1
ADDNE R0,R0,R2,LSL #Log2PageSize
STR R0,[R3,#DANode_Size]
MOV R3,#0
LDR R3,=ZeroPage
STR R0,[R3,#MemLimit]
CMP R5,#-1
MOVEQ R3,#0
......
......@@ -63,7 +63,7 @@
;
AMB_LazyFixUp ROUT
MOV r7,r12
MOV r12,#AMBControl_ws
LDR r12,=ZeroPage+AMBControl_ws
LDR r12,[r12]
CMP r12,#0
BEQ %FT90 ;not initialised!
......@@ -127,7 +127,7 @@ AMB_LazyFixUp ROUT
MOV r5,#L2PT
STR r4,[r5,r0,LSL #2] ;update L2PT
;
MOV r5,#0
LDR r5,=ZeroPage
LDR r5,[r5,#CamEntriesPointer]
ADD r5,r5,r6,LSL #3 ;r5 -> CAM entry affected
MOVS r0,r0,LSL #Log2PageSize ;address is now ordinary again, and must be non-zero
......@@ -184,7 +184,7 @@ AMB_MakeHonestLA ROUT
CMP r0,#AbsMaxAppSize ;quick dismiss if definitely not app address
MOVHS pc,lr
Push "r1,r12,lr"
MOV r12,#AMBControl_ws
LDR r12,=ZeroPage+AMBControl_ws
LDR r12,[r12]
CMP r12,#0
BEQ %FT90 ;we're dormant!
......@@ -205,11 +205,11 @@ AMB_MakeHonestLA ROUT
;
AMB_MakeHonestPN ROUT
Push "r1-r3,r12,lr"
MOV r12,#AMBControl_ws
LDR r12,=ZeroPage+AMBControl_ws
LDR r12,[r12]
CMP r12,#0
BEQ %FT90 ;we're dormant!
MOV r14,#0
LDR r14,=ZeroPage
LDR r1,[r14,#MaxCamEntry]
CMP r0,r1
BHI %FT90 ;invalid page number
......@@ -317,7 +317,7 @@ AMB_movepagesin_CAM ROUT
MOV lr,r9
MOV r9,r3
MOV r11,#0
LDR r11,=ZeroPage
LDR r11,[r11,#CamEntriesPointer] ;r11 -> CAM
CMP r8,#8
......@@ -370,7 +370,7 @@ AMB_movepagesout_CAM ROUT
MOV lr,r9
LDR r9,=DuffEntry
MOV r11,#0
LDR r11,=ZeroPage
LDR r11,[r11,#CamEntriesPointer] ;r11 -> CAM
CMP r8,#8
......@@ -474,7 +474,7 @@ AMB_SetMemMapEntries ROUT
MOV r10,r4 ;ptr to next page number
LDR r2,[r10] ;page number of 1st page
MOV r7,#0
LDR r7,=ZeroPage
LDR r7,[r7,#CamEntriesPointer] ;r7 -> CAM
ADD r1,r7,r2,LSL #3 ;r1 -> CAM entry for 1st page
[ AMB_LimpidFreePool
......@@ -503,7 +503,7 @@ AMB_SetMemMapEntries ROUT
;
MOV r0,r4 ;address of 1st page
MOV r1,r8 ;number of pages
MOV r3,#0
LDR r3,=ZeroPage
ARMop MMU_ChangingUncachedEntries,,,r3 ;no cache worries, hoorah
MOV r3,r5
BL AMB_movepagesout_L2PT ;unmap 'em from where they are
......@@ -515,7 +515,7 @@ AMB_smme_mapnotlimpid
;
MOV r0,r4 ;address of 1st page
MOV r1,r8 ;number of pages
MOV r3,#0
LDR r3,=ZeroPage
ARMop MMU_ChangingEntries,,,r3 ;
MOV r3,r5
BL AMB_movepagesout_L2PT
......@@ -528,7 +528,7 @@ AMB_smme_mapnotlimpid
AMB_smme_mapin
MOV r0,r4 ;address of 1st page
MOV r1,r8 ;number of pages
MOV r3,#0
LDR r3,=ZeroPage
ARMop MMU_ChangingUncachedEntries,,,r3 ;TLB coherency, possibly not needed (TLBs shouldn't cache 0 entries)
MOV r3,r5
BL AMB_movepagesin_L2PT
......@@ -540,7 +540,7 @@ AMB_smme_mapin
AMB_smme_mapout
MOV r0,r4 ;address of 1st page
MOV r1,r8 ;number of pages
MOV r3,#0
LDR r3,=ZeroPage
ARMop MMU_ChangingEntries,,,r3 ;
LDR r3,=DuffEntry
BL AMB_movepagesout_L2PT
......@@ -571,12 +571,11 @@ AMB_SetMemMapEntries_SparseMapOut ROUT
Push "r0-r11,lr"
MOV r10,r4 ;ptr to page list
MOV r7,#0
LDR r7,[r7,#CamEntriesPointer] ;r7 -> CAM
LDR r2,=ZeroPage
MOV r9,#AP_Duff ;permissions for DuffEntry
LDR r1,=DuffEntry ;means Nowhere, in CAM
LDR r7,[r2,#CamEntriesPointer] ;r7 -> CAM
MOV r4,#ApplicationStart ;log. address of first page
MOV r2,#0 ;r2 is zero during sparse map out
LDR r1,=DuffEntry ;means Nowhere, in CAM
;if the number of pages mapped in is small enough, we'll do cache/TLB coherency on
;just those pages, else global (performance decision, threshold probably not critical)
......@@ -605,6 +604,7 @@ AMB_SetMemMapEntries_SparseMapOut ROUT
BEQ %FT16
TEQ r6, #0
BNE %FT14 ;check for coherency as we go
LDR r2,=ZeroPage
MOV r0,r4 ;address of page
ARMop MMU_ChangingEntry,,,r2
14
......@@ -612,6 +612,7 @@ AMB_SetMemMapEntries_SparseMapOut ROUT
ADD r0,r7,r0,LSL #3 ;r0 -> CAM entry for page
STMIA r0,{r1,r9} ;CAM entry for page set to DuffEntry,AP_Duff
LDR lr,=L2PT ;lr -> L2PT
MOV r2, #0
STR r2,[lr,r4,LSR #(Log2PageSize-2)] ;L2PT entry for page set to 0 (means translation fault)
SUBS r3,r3,#1
STREQ r2,[r5,#-4] ;make sure we clear last word of bitmap, and...
......@@ -621,7 +622,9 @@ AMB_SetMemMapEntries_SparseMapOut ROUT
ADD r4,r4,#PageSize ;next logical address
MOVS r8,r8,LSL #1 ;if 32 bits processed...
BNE %BT12
STR r2,[r5,#-4] ;zero word of bitmap we've just traversed (r2 is 0)
MOV r2, #0
STR r2,[r5,#-4] ;zero word of bitmap we've just traversed
LDR r2,=ZeroPage
B %BT10
20
......@@ -645,7 +648,7 @@ AMB_MakeUnsparse ROUT
SUB r0,r0,#1
MOVS r0,r0,LSR #Log2PageSize
BEQ %FT20
MOV r12,#AMBControl_ws
LDR r12,=ZeroPage+AMBControl_ws
LDR r12,[r12]
CMP r12,#0
BEQ %FT20
......@@ -700,7 +703,7 @@ AMB_FindMemMapEntries ROUT
Push "r0-r11,lr"
;initialise r0,r1,r2 as physical RAM chunk cache for AMB_r11topagenum routine
MOV r9,#PhysRamTable
LDR r9,=ZeroPage+PhysRamTable
LDMIA r9,{r0,r1} ;r0,r1 := phys addr,size of chunk
ADD r1,r1,r0 ;r0,r1 := lowest addr,highest addr + 1 of chunk
MOV r2,#0 ;r2 := first page number of chunk
......@@ -761,7 +764,7 @@ AMB_r11topagenum ROUT
ADD r11,r11,r2 ;page number
MOV pc,lr
10
MOV r9,#PhysRamTable
LDR r9,=ZeroPage+PhysRamTable
MOV r2,#0 ;start at page number 0
20
LDMIA r9!,{r0,r1} ;r0,r1 := phys addr,size of chunk
......
......@@ -30,7 +30,7 @@
AMBsrv_memorymoved ROUT
Push "R3-R6,R12,LR"
MOV R12,#AMBControl_ws
LDR R12,=ZeroPage+AMBControl_ws
LDR R12,[R12]
CMP R12,#0
Pull "R3-R6,R12,PC",EQ ;AMBControl not initialised yet!
......@@ -41,7 +41,7 @@ AMBsrv_memorymoved ROUT
LDR R3,[R4,#AMBNode_Npages]
LDR R6,=AppSpaceDANode
LDR R6,=ZeroPage+AppSpaceDANode
LDR R6,[R6,#DANode_Size]
SUB R6,R6,#ApplicationStart
MOV R6,R6,LSR #Log2PageSize
......@@ -172,7 +172,7 @@ AMBsrv_memorymoved ROUT
AMBsrv_pagessafe ROUT
Push "R0-R1,R5-R10,R12,LR"
MOV R12,#AMBControl_ws
LDR R12,=ZeroPage+AMBControl_ws
LDR R12,[R12]
CMP R12,#0
Pull "R0-R1,R5-R10,R12,PC",EQ ;AMBControl not initialised yet!
......
......@@ -61,8 +61,8 @@ shrinkpages
TST R3,#1 ;check flag
MOVEQ R1,#0 ;source is not App space
LDRNE R1,=AppSpaceDANode ;source is App space
LDR R2,=FreePoolDANode ;dest
LDRNE R1,=ZeroPage+AppSpaceDANode ;source is App space
LDR R2,=ZeroPage+FreePoolDANode ;dest
LDR R7,[R0,#AMBNode_Npages] ;R7 := current number of pages
SUBS R3,R7,R6 ;R3 := no. of pages to move
......@@ -90,7 +90,7 @@ shrinkpages
LDRNE R0,[R1,#DANode_Size]
SUBNE R0,R0,R3,LSL #Log2PageSize
STRNE R0,[R1,#DANode_Size]
MOVNE R5,#0
LDRNE R5,=ZeroPage
STRNE R0,[R5,#MemLimit] ;update MemLimit
02
......
This diff is collapsed.
......@@ -72,7 +72,7 @@ ARM_Analyse
Push "v1,v2,v5,v6,v7,lr"
ARM_read_ID v1
ARM_read_cachetype v2
MOV v6, #ZeroPage
LDR v6, =ZeroPage
ADRL v7, KnownCPUTable
FindARMloop
......@@ -111,6 +111,9 @@ FindARMloop
|
MOV v5, #0
]
[ HiProcVecs
ORR v5, v5, #CPUFlag_HiProcVecs
]
TST v2, #CT_S
ORRNE v5, v5, #CPUFlag_SplitCache+CPUFlag_SynchroniseCodeAreas
......@@ -147,9 +150,10 @@ FindARMloop
BNE %FT35
; Do we get vector exceptions on read?
MOV a1, #0
LDR a2, =ZeroPage
MOV a1, a2
LDR a1, [a1] ; If this aborts a1 will be left unchanged
TEQ a1, #0
TEQ a1, a2
ORREQ v5, v5, #CPUFlag_VectorReadException
]
35
......@@ -342,8 +346,7 @@ Analyse_WB_CR7_LDa
ADRL a1, MMU_ChangingUncachedEntries_WB_CR7_LDa
STR a1, [v6, #Proc_MMU_ChangingUncachedEntries]
MOV a1, #0
LDRB a2, [a1, #DCache_Associativity]
LDRB a2, [v6, #DCache_Associativity]
MOV a3, #256
MOV a4, #8 ; to find log2(ASSOC), rounded up
......@@ -357,15 +360,15 @@ Analyse_WB_CR7_LDa_L1
RSB a2, a4, #32
MOV a3, #1
MOV a3, a3, LSL a2
STR a3, [a1, #DCache_IndexBit]
LDR a4, [a1, #DCache_NSets]
LDRB a2, [a1, #DCache_LineLen]
STR a3, [v6, #DCache_IndexBit]
LDR a4, [v6, #DCache_NSets]
LDRB a2, [v6, #DCache_LineLen]
SUB a4, a4, #1
MUL a4, a2, a4
STR a4, [a1, #DCache_IndexSegStart]
STR a4, [v6, #DCache_IndexSegStart]
MOV a2, #64*1024 ; arbitrary-ish
STR a2, [a1, #DCache_RangeThreshold]
STR a2, [v6, #DCache_RangeThreshold]
ADRL a1, XCBTableWBR ; assume read-allocate WB/WT cache
STR a1, [v6, #MMU_PCBTrans]
......@@ -421,14 +424,13 @@ Analyse_WB_Crd
ADRL a1, MMU_ChangingUncachedEntries_WB_Crd
STR a1, [v6, #Proc_MMU_ChangingUncachedEntries]
MOV a1, #0
LDR a2, =DCacheCleanAddress
STR a2, [a1, #DCache_CleanBaseAddress]
STR a2, [a1, #DCache_CleanNextAddress]
STR a2, [v6, #DCache_CleanBaseAddress]
STR a2, [v6, #DCache_CleanNextAddress]
MOV a2, #64*1024 ;arbitrary-ish threshold
STR a2, [a1, #DCache_RangeThreshold]
STR a2, [v6, #DCache_RangeThreshold]
LDRB a2, [a1, #ProcessorType]
LDRB a2, [v6, #ProcessorType]
TEQ a2, #SA110
ADREQL a2, XCBTableSA110
BEQ Analyse_WB_Crd_finish
......@@ -437,7 +439,7 @@ Analyse_WB_Crd
ADREQL a2, XCBTableSA1110
ADRNEL a2, XCBTableWBR
Analyse_WB_Crd_finish
STR a2, [a1, #MMU_PCBTrans]
STR a2, [v6, #MMU_PCBTrans]
B %FT90
Analyse_WB_Cal_LD
......@@ -489,16 +491,15 @@ Analyse_WB_Cal_LD
ADRL a1, MMU_ChangingUncachedEntries_WB_Cal_LD
STR a1, [v6, #Proc_MMU_ChangingUncachedEntries]
MOV a1, #0
LDR a2, =DCacheCleanAddress
STR a2, [a1, #DCache_CleanBaseAddress]
STR a2, [a1, #DCache_CleanNextAddress]
STR a2, [v6, #DCache_CleanBaseAddress]
STR a2, [v6, #DCache_CleanNextAddress]
[ XScaleMiniCache
! 1, "You need to arrange for XScale mini-cache clean area to be mini-cacheable"
LDR a2, =DCacheCleanAddress + 4 * 32*1024
STR a2, [a1, #MCache_CleanBaseAddress]
STR a2, [a1, #MCache_CleanNextAddress]
STR a2, [v6, #MCache_CleanBaseAddress]
STR a2, [v6, #MCache_CleanNextAddress]
]
......@@ -508,14 +509,14 @@ Analyse_WB_Cal_LD
|
MOV a2, #32*1024
]
STR a2, [a1, #DCache_RangeThreshold]
STR a2, [v6, #DCache_RangeThreshold]
; enable full coprocessor access
LDR a2, =&3FFF
MCR p15, 0, a2, c15, c1
ADRL a2, XCBTableXScaleWA ; choose between RA and WA here
STR a2, [a1, #MMU_PCBTrans]
STR a2, [v6, #MMU_PCBTrans]
B %FT90
......@@ -769,7 +770,7 @@ KnownCPUFlags
ARM_Analyse_Fancy
Push "v1,v2,v5,v6,v7,lr"
ARM_read_ID v1
MOV v6, #ZeroPage
LDR v6, =ZeroPage
ADRL v7, KnownCPUTable_Fancy
10
LDMIA v7!, {a1, a2}
......@@ -791,6 +792,9 @@ ARM_Analyse_Fancy
STRB a1, [v6, #Cache_Type]
MOV v5, #CPUFlag_32bitOS+CPUFlag_No26bitMode ; 26bit has been obsolete for a long time
[ HiProcVecs
ORR v5, v5, #CPUFlag_HiProcVecs
]
; Work out whether the cache info is in ARMv6 or ARMv7 style
MRC p15, 0, a1, c0, c0, 1
......@@ -1132,7 +1136,7 @@ Cache_CleanAll_WB_CR7_LDa ROUT
; DCache_IndexSegStart = &000000E0 (start at index=0, segment = 7)
;
Push "a2, ip"
MOV ip, #0
LDR ip, =ZeroPage
LDRB a1, [ip, #DCache_LineLen] ; segment field starts at this bit
LDR a2, [ip, #DCache_IndexBit] ; index field starts at this bit
LDR ip, [ip, #DCache_IndexSegStart] ; starting value, with index at min, seg at max
......@@ -1153,7 +1157,7 @@ Cache_CleanInvalidateAll_WB_CR7_LDa ROUT
; similar to Cache_CleanAll, but does clean&invalidate of Dcache, and invalidates ICache
;
Push "a2, ip"
MOV ip, #0
LDR ip, =ZeroPage
LDRB a1, [ip, #DCache_LineLen] ; segment field starts at this bit
LDR a2, [ip, #DCache_IndexBit] ; index field starts at this bit
LDR ip, [ip, #DCache_IndexSegStart] ; starting value, with index at min, seg at max
......@@ -1180,7 +1184,7 @@ Cache_InvalidateAll_WB_CR7_LDa ROUT
Cache_RangeThreshold_WB_CR7_LDa ROUT
MOV a1, #0
LDR a1, =ZeroPage
LDR a1, [a1, #DCache_RangeThreshold]
MOV pc, lr
......@@ -1226,7 +1230,7 @@ IMB_Range_WB_CR7_LDa ROUT
ADD a2, a2, a1
BHS IMB_Full_WB_CR7_LDa
Push "lr"
MOV lr, #0
LDR lr, =ZeroPage
LDRB lr, [lr, #DCache_LineLen]
10
MCR p15, 0, a1, c7, c10, 1 ; clean DCache entry by VA
......@@ -1250,7 +1254,7 @@ MMU_Changing_WB_CR7_LDa ROUT
MMU_ChangingEntry_WB_CR7_LDa ROUT
Push "a2, lr"
ADD a2, a1, #PageSize
MOV lr, #0
LDR lr, =ZeroPage
LDRB lr, [lr, #DCache_LineLen]
10
MCR p15, 0, a1, c7, c14, 1 ; clean&invalidate DCache entry
......@@ -1271,13 +1275,12 @@ MMU_ChangingEntry_WB_CR7_LDa ROUT
MMU_ChangingEntries_WB_CR7_LDa ROUT
Push "a2, a3, lr"
MOV a2, a2, LSL #Log2PageSize
MOV a3, #0
LDR a3, [a3, #DCache_RangeThreshold] ;check whether cheaper to do global clean
LDR lr, =ZeroPage
LDR a3, [lr, #DCache_RangeThreshold] ;check whether cheaper to do global clean
CMP a2, a3
BHS %FT30
ADD a2, a2, a1 ;clean end address (exclusive)
MOV a3, #0
LDRB a3, [a3, #DCache_LineLen]
LDRB a3, [lr, #DCache_LineLen]
MOV lr, a1
10
MCR p15, 0, a1, c7, c14, 1 ; clean&invalidate DCache entry
......@@ -1365,7 +1368,7 @@ Cache_CleanAll_WB_Crd ROUT
;
Push "a2-a4, v1, v2, lr"
MOV lr, #0
LDR lr, =ZeroPage
LDR a1, [lr, #DCache_CleanBaseAddress]