Tags · Jeffrey Lee / HdrSrc · GitLab

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HdrSrc-2_81

a79659ce · Resync with allocations database · Sep 12, 2019

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HdrSrc-2_80 Merge request: https://gitlab.riscosopen.org/RiscOS/Sources/Programmer/HdrSrc/merge_requests/3

dda94028 · Add supersection definitions to MEMM.ARM600 as well · Aug 19, 2019

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HdrSrc-2_79 Merge request: https://gitlab.riscosopen.org/RiscOS/Sources/Programmer/HdrSrc/merge_requests/2

7d91c601 · Add definitions for supersections in L1PT · Jul 15, 2019

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HdrSrc-2_78 Merge request: https://gitlab.riscosopen.org/RiscOS/Sources/Programmer/HdrSrc/merge_requests/1

79a72575 · Add a definition of the BEN bit in SCTLR (née MMU control register) · Jun 23, 2019

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HdrSrc-2_77

ad292190 · Resync with allocations database · May 30, 2018

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HdrSrc-2_76

8298f414 · Resync with allocations database · Apr 27, 2018

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HdrSrc-2_75

af8e96a8 · Resync with allocations database · Apr 15, 2018

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HdrSrc-2_74

e091e732 · Add GNUmakefile for cross-compilation use · Apr 12, 2018

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HdrSrc-2_73

bbca0fed · Fix non-functional teletext on some platforms, and standardise on HiResTTX across the board · Jan 26, 2018

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HdrSrc-2_72

f38dfe08 · Resync with allocations database (SMP module definitions) · Jul 25, 2017

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HdrSrc-2_71

eb0df56d · Resync with allocations database (extensions to GraphicsV) · Jun 07, 2017

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HdrSrc-2_70

c1dced2c · Resync with allocations database · Dec 29, 2016

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HdrSrc-2_69

0b4990ab · Update VMSAv6 page table definitions · Aug 02, 2016

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HdrSrc-2_68

69c46a2f · Resync with allocations database · Aug 01, 2016

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HdrSrc-2_67

76495ac5 · Resync with allocations database · Jul 03, 2016

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HdrSrc-2_66

833b0b02 · Fix SetMode macro · Jun 18, 2016

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HdrSrc-2_65

71306206 · Add new PSR manipulation macros, optimised for 32bit machines · Jun 12, 2016

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HdrSrc-2_64

15c9ad3f · CortexA7 is missing from the HiResTTX switch. This means on Titanium · Jun 05, 2016

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HdrSrc-2_63

7d0f8d91 · Add new "26" machine type. Simplify ARM2 support. · May 28, 2016

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HdrSrc-2_62

03e4d645 · Revert change from HdrSrc 2.61 · May 09, 2016

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