Commit aab71fc1 authored by ROOL's avatar ROOL :robot:
Browse files

Participate in keyboard scan dependencies

Detail:
  Replace keyboard scan code with list of modules that the kernel needs to do the same.
  Reorder the HALEntries to match Kernel-5_89.
  Back fill missing UARTDefault entry point.
  Delete unused workspace.
  Remove now unused USB driver and local copies of OHCI registers.
Admin:
  Submission for USB bounty.

Version 0.60. Tagged as 'Tungsten-0_60'
......@@ -14,31 +14,11 @@
#
# Makefile for Tungsten HAL
#
# ***********************************
# *** C h a n g e L i s t ***
# ***********************************
# Date Name Description
# ---- ---- -----------
# 25-May-94 AMcC Created.
#
#
# Paths
#
EXP_HDR = <export$dir>
C_EXP_HDR = <cexport$dir>.Global.h
include StdTools
CFLAGS = -c ${THROWBACK} -Wc -ff -cpu 5TE -APCS 3/32bit/noswst -depend !Depend -IC:,TCPIPLibs:,C:USB
ASFLAGS = -depend !Depend -g -APCS 3/nofp/noswst -cpu 5TE ${THROWBACK}
TOKENISE = tokenise
TOKENS = Hdr:Tokens
#
# Program specific options:
#
COMPONENT = Tungsten
TARGET = bin.Tungsten
DBGTARGET = aif.Tungsten
......@@ -47,7 +27,7 @@ EXPORTS =
OBJECTS = o.Top o.Boot o.IIC o.Interrupts o.Timers o.NVMemory o.MachineID \
o.PCIasm o.DebugPCI o.Video o.PCI o.CLib o.CLibAsm o.ATA \
o.M1535DMA o.USBHAL o.UART o.Audio o.MSI o.RTC o.PCItung o.USBtung
o.M1535DMA o.KbdScan o.UART o.Audio o.MSI o.RTC o.PCItung
DIRS = dirs
......
/* (0.59)
/* (0.60)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.59
#define Module_MajorVersion_CMHG 0.60
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 08 Jul 2017
#define Module_Date_CMHG 09 Sep 2017
#define Module_MajorVersion "0.59"
#define Module_Version 59
#define Module_MajorVersion "0.60"
#define Module_Version 60
#define Module_MinorVersion ""
#define Module_Date "08 Jul 2017"
#define Module_Date "09 Sep 2017"
#define Module_ApplicationDate "08-Jul-17"
#define Module_ApplicationDate "09-Sep-17"
#define Module_ComponentName "Tungsten"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/Tungsten"
#define Module_FullVersion "0.59"
#define Module_HelpVersion "0.59 (08 Jul 2017)"
#define Module_LibraryVersionInfo "0:59"
#define Module_FullVersion "0.60"
#define Module_HelpVersion "0.60 (09 Sep 2017)"
#define Module_LibraryVersionInfo "0:60"
This diff is collapsed.
/* Copyright 2004 Castle Technology Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#define HAL
#ifdef HAL
//#define DEBUGLIB
#endif
#include "pci.h"
/* Calling standard mungery - mustn't touch sb/v6 */
__global_reg(6) void *sb;
void* hal_find_usb_base(int* basep)
{
return pci_find_class_address (0x0C0310, basep);
}
uint8_t hal_find_usb_irq(pci_dev* device)
{
return pci_read_config_byte_dev(device, PCI_INT_LINE);
}
void hal_done_with_controller(pci_dev* device)
{
return ;
}
void hal_usb_power(int port, int state)
{
}
void hal_ack_usb_irq(unsigned device)
{
}
/* Copyright 2017 Castle Technology Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if !defined(OHCI_H) /* file used if not already included */
#define OHCI_H
/*****************************************************************************
* $Id$
* $Name$
*
* Author(s): Daniel R Ellis
* Project(s): Next Generation (331)
*
* ----------------------------------------------------------------------------
* Copyright [2000] Pace Micro Technology PLC. All rights reserved.
*
* The copyright in this material is owned by Pace Micro Technology PLC
* ("Pace"). This material is regarded as a highly confidential trade secret
* of Pace. It may not be reproduced, used, sold or in any other way exploited
* or transferred to any third party without the prior written permission of
* Pace.
*
* ----------------------------------------------------------------------------
* Purpose: Data structures pertinent to the Open Host Controller
* Interface, as specified in OpenHCI release 1.0a available from
* http://www.compaq.com/productinfo/development/openhci.html
*
* Note that these data structures are ARM architecture dependant,
* i.e. 32-bit little endian
*
* ----------------------------------------------------------------------------
* History: See source control system log
*
*****************************************************************************/
/*****************************************************************************
* Include header files
*****************************************************************************/
#include <stdint.h>
typedef uint32_t u_int32_t;
typedef uint16_t u_int16_t;
#include "ohcireg.h"
/*****************************************************************************
* MACROS
*****************************************************************************/
/*****************************************************************************
* New type definitions
*****************************************************************************/
/* Isochronous transfer descriptor */
typedef struct OHCI_IsoTD {
unsigned int startFrame:16; /* Frame in which to send */
unsigned int :5;
unsigned int delayInterrupt:3; /* HC may wait this many frames */
unsigned int frameCount:3; /* number of packets in this TD - 1 */
unsigned int :1;
unsigned int conditionCode:4; /* Status of last transaction */
char* bufferPage0; /* bottom 12 bits zero */
struct OHCI_IsoTD* nextTD; /* the next transfer descriptor */
char* bufferEnd; /* the end of the buffer */
unsigned short offset[8]; /* buffer offsets for transfers */
} OHCI_IsoTD;
/* General transfer descriptor */
typedef struct OHCI_TD {
int :18;
unsigned int bufferRounding:1; /* 1=> don't error unfilled buffer */
unsigned int direction:2; /* SETUP/OUT/IN/reserved */
unsigned int delayInterrupt:3; /* HC may wait this many frames */
unsigned int dataToggle:2; /* for PID DATA0/DATA1 */
unsigned int errorCount:2; /* incremented before recording */
unsigned int conditionCode:4; /* Status of last transaction */
char* currentBuffer; /* next transfer memory location */
struct OHCI_TD* nextTD; /* the next transfer descriptor */
char* bufferEnd; /* the end of the buffer */
} OHCI_TD;
/* Endpoint descriptor */
typedef struct OHCI_ED {
unsigned int functionAddress:7; /* USB address of function */
unsigned int endpointNumber:4; /* Address within function */
unsigned int direction:2; /* 00,11=>TD, 01 OUT, 10 IN */
unsigned int speed:1; /* 0 full, 1 low */
unsigned int skip:1; /* skip this endpoint */
unsigned int format:1; /* 1 => isochronous */
unsigned int maxPacketSize:11; /* max bytes in a single packet */
unsigned int :5;
OHCI_TD* tailPointer; /* end of TD list */
union {
union {
OHCI_TD* normal; /* next TD to process on list */
OHCI_IsoTD* iso; /* next TD to process on list */
} pointer;
struct {
unsigned int halted:1; /* set if halted (error) */
unsigned int toggleCarry:1; /* LSb of TD data Toggle field */
} flags;
} head;
struct OHCI_ED* nextED; /* next endpoint */
} OHCI_ED;
/* The Host Controller Communications Area */
#define OHCI_NUM_INTERRUPTS 32
typedef struct OHCI_Hcca {
OHCI_ED* interruptTable[OHCI_NUM_INTERRUPTS]; /* Table of interrupt EDs */
unsigned short frameNumber; /* updated before processing */
unsigned short pad1; /* zeroed upon frameNumber Update */
union {
OHCI_TD* pointer; /* current value of hcdone head */
unsigned int flag:1; /* other interrupts also set */
} donehead;
unsigned char reserved[116];
} OHCI_Hcca;
/* These are the registers of the OHCI controller */
typedef struct OHCI_Registers {
unsigned int revision;
struct {
unsigned int CBSR:2; /* Control/Bulk service ration */
unsigned int PLE:1; /* Periodic list enable */
unsigned int IE:1; /* Isochronous enable */
unsigned int CLE:1; /* Control list enable */
unsigned int BLE:1; /* Bulk list enable */
unsigned int HCFS:2; /* host controller functional state */
unsigned int IR:1; /* Interrupt routing */
unsigned int RWC:1; /* Remote wakeup connected */
unsigned int RWE:1; /* Remote wakeup enabled */
unsigned int :21;
} control;
union {
struct {
unsigned int HCR:1; /* Host controller reset */
unsigned int CLF:1; /* Control list filled */
unsigned int BLF:1; /* Bulk list filled */
unsigned int OCR:1; /* Ownership change request */
unsigned int :12;
unsigned int SOC:2; /* Scheduling overrun count */
unsigned int :14;
} bits;
unsigned int word;
} command_status;
union {
struct {
unsigned int SO:1; /* Scheduling overrun */
unsigned int WDH:1; /* Writeback done head */
unsigned int SF:1; /* Start of frame */
unsigned int RD:1; /* Resume detected */
unsigned int UE:1; /* Unrecoverable error */
unsigned int FNO:1; /* Frame number overflow */
unsigned int RHSC:1; /* Root hub status changed */
unsigned int :23;
unsigned int OC:1; /* Ownership change */
unsigned int MIE:1; /* Master interrupt enable */
} bits;
unsigned int word;
} status, enable, disable;
OHCI_Hcca* hcca;
OHCI_ED* period_current_ED;
OHCI_ED* control_head_ED;
OHCI_ED* control_current_ED;
OHCI_ED* bulk_head_ED;
OHCI_ED* bulk_current_ED;
OHCI_TD* done_head;
struct {
unsigned int FI:14; /* Frame interval in 12MHz periods */
unsigned int :2;
unsigned int FSMPS:15; /* Scheduler max packet size */
unsigned int FIT:1; /* Frame interval toggle */
} fm_interval;
struct {
unsigned int FR:14; /* Frame remaining */
unsigned int :17;
unsigned int FRT:1; /* Frame remaining toggle */
} fm_remaining;
struct {
unsigned int FN:16; /* Frame number */
unsigned int :16;
} fm_number;
unsigned int periodic_start; /* delay before doing periodic data */
unsigned int ls_threshold; /* low speed threshold */
struct RootHub {
unsigned int descriptorA;
unsigned int descriptorB;
unsigned int status;
/* Allow specification of number of root hub ports by includer of this file */
#ifndef OHCI_ROOT_HUB_PORTS
#define OHCI_ROOT_HUB_PORTS 1
#endif
#define UPS_CURRENT_CONNECT_STATUS 0x00000001
#define UPS_PORT_ENABLED 0x00000002
#define UPS_SUSPEND 0x00000004
#define UPS_OVERCURRENT_INDICATOR 0x00000008
#define UPS_RESET 0x00000010
#define UPS_PORT_POWER 0x00000100
#define UPS_LOW_SPEED 0x00000200
#define UPS_C_CONNECT_STATUS 0x00010000
#define UPS_C_PORT_ENABLED 0x00020000
#define UPS_C_SUSPEND 0x00040000
#define UPS_C_OVERCURRENT_INDICATOR 0x00080000
#define UPS_C_PORT_RESET 0x00100000
union {
struct {
int CCS:1; /* Current connect status & ClearPortEnable */
int PES:1; /* Port enable status & SetPortEnable */
int PSS:1; /* port suspend status & SetPortSuspend */
int POCI:1; /* port over current & ClearPortSuspend */
int PRS:1; /* port rest status & SetPortReset */
int :3;
int PPS:1; /* port power status & SetPortpower */
int LSDA:1; /* low spd dev attach & ClearPortPower */
int :6;
int CSC:1; /* connect status change */
int PESC:1; /* port enable status change */
int PSSC:1; /* port suspend status change */
int OCIC:1; /* port over current indicator change */
int PRSC:1; /* port reset status change */
int :11;
} bits;
unsigned int word;
} port_status[OHCI_ROOT_HUB_PORTS];
} rootHub;
} OHCI_Registers;
/*****************************************************************************
* Constants
*****************************************************************************/
/*****************************************************************************
* Global variables
*****************************************************************************/
/*****************************************************************************
* Function prototypes
*****************************************************************************/
/*****************************************************************************
* FunctionName
*
* Description of the function
*
* Assumptions
* State any assumptions and side effects (eg. globals changed)
*
* Inputs
* variablename: describe variable, range of inputs, etc.
*
* Outputs
* variablename: describe variable, range of outputs, etc.
*
* Returns
* describe possible return values, etc.
*****************************************************************************/
#endif /* end of sentry #ifdef */
/*****************************************************************************
* END OF FILE
*****************************************************************************/
/* Copyright 2003 Tematic Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef USBHAL_H
#define USBHAL_H
extern void HAL_KbdScanSetup (void);
extern unsigned int HAL_KbdScan (void);
extern void HAL_KbdScanFinish (void);
extern int HAL_KbdScanInterrupt (int devno);
extern void HAL_IRQEnable(int);
extern void* vtophys (const void* v);
extern void *alloc_contig(size_t len, int alignment);
extern void free_contig(void *p);
/* microsecond delay */
extern void delay(int);
struct usbhal;
extern struct usbhal* alloc_usbhal (int s);
extern struct usbhal* get_usbhal (void);
#endif
/* $NetBSD: ohcireg.h,v 1.18 2000/04/27 15:26:47 augustss Exp $ */
/* $FreeBSD: src/sys/dev/usb/ohcireg.h,v 1.8 1999/11/17 22:33:40 n_hibma Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Lennart Augustsson (lennart@augustsson.net) at
* Carlstedt Research & Technology.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _DEV_PCI_OHCIREG_H_
#define _DEV_PCI_OHCIREG_H_
/*** PCI config registers ***/
#define PCI_CBMEM 0x10 /* configuration base memory */
#define PCI_INTERFACE_OHCI 0x10
/*** OHCI registers */
#define OHCI_REVISION 0x00 /* OHCI revision # */
#define OHCI_REV_LO(rev) ((rev)&0xf)
#define OHCI_REV_HI(rev) (((rev)>>4)&0xf)
#define OHCI_REV_LEGACY(rev) ((rev) & 0x100)
#define OHCI_CONTROL 0x04
#define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */
#define OHCI_RATIO_1_1 0x00000000
#define OHCI_RATIO_1_2 0x00000001
#define OHCI_RATIO_1_3 0x00000002
#define OHCI_RATIO_1_4 0x00000003
#define OHCI_PLE 0x00000004 /* Periodic List Enable */
#define OHCI_IE 0x00000008 /* Isochronous Enable */
#define OHCI_CLE 0x00000010 /* Control List Enable */
#define OHCI_BLE 0x00000020 /* Bulk List Enable */
#define OHCI_HCFS_MASK 0x000000c0 /* HostControllerFunctionalState */
#define OHCI_HCFS_RESET 0x00000000
#define OHCI_HCFS_RESUME 0x00000040
#define OHCI_HCFS_OPERATIONAL 0x00000080
#define OHCI_HCFS_SUSPEND 0x000000c0
#define OHCI_IR 0x00000100 /* Interrupt Routing */
#define OHCI_RWC 0x00000200 /* Remote Wakeup Connected */
#define OHCI_RWE 0x00000400 /* Remote Wakeup Enabled */
#define OHCI_COMMAND_STATUS 0x08
#define OHCI_HCR 0x00000001 /* Host Controller Reset */
#define OHCI_CLF 0x00000002 /* Control List Filled */
#define OHCI_BLF 0x00000004 /* Bulk List Filled */
#define OHCI_OCR 0x00000008 /* Ownership Change Request */
#define OHCI_SOC_MASK 0x00030000 /* Scheduling Overrun Count */
#define OHCI_INTERRUPT_STATUS 0x0c
#define OHCI_SO 0x00000001 /* Scheduling Overrun */
#define OHCI_WDH 0x00000002 /* Writeback Done Head */
#define OHCI_SF 0x00000004 /* Start of Frame */
#define OHCI_RD 0x00000008 /* Resume Detected */
#define OHCI_UE 0x00000010 /* Unrecoverable Error */
#define OHCI_FNO 0x00000020 /* Frame Number Overflow */
#define OHCI_RHSC 0x00000040 /* Root Hub Status Change */
#define OHCI_OC 0x40000000 /* Ownership Change */
#define OHCI_MIE 0x80000000 /* Master Interrupt Enable */
#define OHCI_INTERRUPT_ENABLE 0x10
#define OHCI_INTERRUPT_DISABLE 0x14
#define OHCI_HCCA 0x18
#define OHCI_PERIOD_CURRENT_ED 0x1c
#define OHCI_CONTROL_HEAD_ED 0x20
#define OHCI_CONTROL_CURRENT_ED 0x24
#define OHCI_BULK_HEAD_ED 0x28
#define OHCI_BULK_CURRENT_ED 0x2c
#define OHCI_DONE_HEAD 0x30
#define OHCI_FM_INTERVAL 0x34
#define OHCI_GET_IVAL(s) ((s) & 0x3fff)
#define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff)
#define OHCI_FIT 0x80000000
#define OHCI_FM_REMAINING 0x38
#define OHCI_FM_NUMBER 0x3c
#define OHCI_PERIODIC_START 0x40
#define OHCI_LS_THRESHOLD 0x44
#define OHCI_RH_DESCRIPTOR_A 0x48
#define OHCI_GET_NDP(s) ((s) & 0xff)
#define OHCI_PSM 0x0100 /* Power Switching Mode */
#define OHCI_NPS 0x0200 /* No Power Switching */
#define OHCI_DT 0x0400 /* Device Type */
#define OHCI_OCPM 0x0800 /* Overcurrent Protection Mode */
#define OHCI_NOCP 0x1000 /* No Overcurrent Protection */
#define OHCI_GET_POTPGT(s) ((s) >> 24)
#define OHCI_RH_DESCRIPTOR_B 0x4c
#define OHCI_RH_STATUS 0x50
#define OHCI_LPS 0x00000001 /* Local Power Status */
#define OHCI_OCI 0x00000002 /* OverCurrent Indicator */
#define OHCI_DRWE 0x00008000 /* Device Remote Wakeup Enable */
#define OHCI_LPSC 0x00010000 /* Local Power Status Change */
#define OHCI_CCIC 0x00020000 /* OverCurrent Indicator Change */
#define OHCI_CRWE 0x80000000 /* Clear Remote Wakeup Enable */
#define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) /* 1 based indexing */
#define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE)
#define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | \
OHCI_FNO | OHCI_RHSC | OHCI_OC)
#define OHCI_NORMAL_INTRS (OHCI_SO | OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC)
#define OHCI_FSMPS(i) (((i-210)*6/7) << 16)
#define OHCI_PERIODIC(i) ((i)*9/10)
typedef u_int32_t ohci_physaddr_t;
#define OHCI_NO_INTRS 32
struct ohci_hcca {
ohci_physaddr_t hcca_interrupt_table[OHCI_NO_INTRS];
u_int32_t hcca_frame_number;
ohci_physaddr_t hcca_done_head;
#define OHCI_DONE_INTRS 1
};
#define OHCI_HCCA_SIZE 256
#define OHCI_HCCA_ALIGN 256
#define OHCI_PAGE_SIZE 0x1000
#define OHCI_PAGE(x) ((x) &~ 0xfff)
#define OHCI_PAGE_OFFSET(x) ((x) & 0xfff)
typedef struct {
u_int32_t ed_flags;
#define OHCI_ED_GET_FA(s) ((s) & 0x7f)
#define OHCI_ED_ADDRMASK 0x0000007f
#define OHCI_ED_SET_FA(s) (s)
#define OHCI_ED_GET_EN(s) (((s) >> 7) & 0xf)
#define OHCI_ED_SET_EN(s) ((s) << 7)
#define OHCI_ED_DIR_MASK 0x00001800
#define OHCI_ED_DIR_TD 0x00000000
#define OHCI_ED_DIR_OUT 0x00000800
#define OHCI_ED_DIR_IN 0x00001000
#define OHCI_ED_SPEED 0x00002000
#define OHCI_ED_SKIP 0x00004000
#define OHCI_ED_FORMAT_GEN 0x00000000
#define OHCI_ED_FORMAT_ISO 0x00008000
#define OHCI_ED_GET_MAXP(s) (((s) >> 16) & 0x07ff)
#define OHCI_ED_SET_MAXP(s) ((s) << 16)
#define OHCI_ED_MAXPMASK (0x7ff << 16)
ohci_physaddr_t ed_tailp;
ohci_physaddr_t ed_headp;
#define OHCI_HALTED 0x00000001
#define OHCI_TOGGLECARRY 0x00000002
#define OHCI_HEADMASK 0xfffffffc
ohci_physaddr_t ed_nexted;
} ohci_ed_t;
/* #define OHCI_ED_SIZE 16 */
#define OHCI_ED_ALIGN 16
typedef struct {
u_int32_t td_flags;
#define OHCI_TD_R 0x00040000 /* Buffer Rounding */
#define OHCI_TD_DP_MASK 0x00180000 /* Direction / PID */
#define OHCI_TD_SETUP 0x00000000
#define OHCI_TD_OUT 0x00080000
#define OHCI_TD_IN 0x00100000
#define OHCI_TD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */
#define OHCI_TD_SET_DI(x) ((x) << 21)
#define OHCI_TD_NOINTR 0x00e00000
#define OHCI_TD_INTR_MASK 0x00e00000
#define OHCI_TD_TOGGLE_CARRY 0x00000000
#define OHCI_TD_TOGGLE_0 0x02000000
#define OHCI_TD_TOGGLE_1 0x03000000
#define OHCI_TD_TOGGLE_MASK 0x03000000
#define OHCI_TD_GET_EC(x) (((x) >> 26) & 3) /* Error Count */
#define OHCI_TD_GET_CC(x) ((x) >> 28) /* Condition Code */
#define OHCI_TD_NOCC 0xf0000000
ohci_physaddr_t td_cbp; /* Current Buffer Pointer */
ohci_physaddr_t td_nexttd; /* Next TD */
ohci_physaddr_t td_be; /* Buffer End */
} ohci_td_t;
/* #define OHCI_TD_SIZE 16 */
#define OHCI_TD_ALIGN 16
#define OHCI_ITD_NOFFSET 8
typedef struct {
u_int32_t itd_flags;
#define OHCI_ITD_GET_SF(x) ((x) & 0x0000ffff)
#define OHCI_ITD_SET_SF(x) ((x) & 0xffff)
#define OHCI_ITD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */
#define OHCI_ITD_SET_DI(x) ((x) << 21)
#define OHCI_ITD_NOINTR 0x00e00000
#define OHCI_ITD_GET_FC(x) ((((x) >> 24) & 7)+1) /* Frame Count */
#define OHCI_ITD_SET_FC(x) (((x)-1) << 24)
#define OHCI_ITD_GET_CC(x) ((x) >> 28) /* Condition Code */
#define OHCI_ITD_NOCC 0xf0000000
ohci_physaddr_t itd_bp0; /* Buffer Page 0 */
ohci_physaddr_t itd_nextitd; /* Next ITD */
ohci_physaddr_t itd_be; /* Buffer End */
u_int16_t itd_offset[OHCI_ITD_NOFFSET]; /* Buffer offsets */
#define itd_pswn itd_offset /* Packet Status Word*/
#define OHCI_ITD_PAGE_SELECT 0x00001000
#define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff))
#define OHCI_ITD_PSW_LENGTH(x) ((x) & 0xfff) /* Transfer length */
#define OHCI_ITD_PSW_GET_CC(x) ((x) >> 12) /* Condition Code */
} ohci_itd_t;
/* #define OHCI_ITD_SIZE 32 */
#define OHCI_ITD_ALIGN 32
#define OHCI_CC_NO_ERROR 0
#define OHCI_CC_CRC 1
#define OHCI_CC_BIT_STUFFING 2
#define OHCI_CC_DATA_TOGGLE_MISMATCH 3
#define OHCI_CC_STALL 4
#define OHCI_CC_DEVICE_NOT_RESPONDING 5
#define OHCI_CC_PID_CHECK_FAILURE 6
#define OHCI_CC_UNEXPECTED_PID 7
#define OHCI_CC_DATA_OVERRUN 8
#define OHCI_CC_DATA_UNDERRUN 9
#define OHCI_CC_BUFFER_OVERRUN 12
#define OHCI_CC_BUFFER_UNDERRUN 13
#define OHCI_CC_NOT_ACCESSED 15
/* Some delay needed when changing certain registers. */
#define OHCI_ENABLE_POWER_DELAY 5
#define OHCI_READ_DESC_DELAY 5
#endif /* _DEV_PCI_OHCIREG_H_ */
......@@ -60,7 +60,6 @@ MasterPICMask # 1
SlavePICMask # 1
UARTFCRSoftCopy # 1
PCIState # 4 ; pointer to C PCI workspace
USBHALws # 4 ; " " C USB keyboard scan workspace
RTCDeviceStruct # 80
IDEDeviceStruct # 76+4
i80321DMAWS # i80321DMA_WorkspaceSize
......
......@@ -190,6 +190,7 @@ HALdescriptor DATA
IMPORT HAL_UARTModemControl
IMPORT HAL_UARTModemStatus
IMPORT HAL_UARTDevice
IMPORT HAL_UARTDefault
IMPORT HAL_MachineID
......@@ -207,10 +208,7 @@ HALdescriptor DATA
IMPORT HAL_PCISlotTable
IMPORT HAL_PCIAddresses
IMPORT HAL_KbdScanSetup
IMPORT HAL_KbdScan
IMPORT HAL_KbdScanFinish
IMPORT HAL_KbdScanInterrupt
IMPORT HAL_KbdScanDependencies
HAL_EntryTable DATA
HALEntry HAL_Init
......@@ -308,8 +306,7 @@ HAL_EntryTable DATA
HALEntry HAL_UARTModemControl
HALEntry HAL_UARTModemStatus
HALEntry HAL_UARTDevice
HALEntry HAL_Reset
HALEntry HAL_UARTDefault
HALEntry HAL_DebugRX
HALEntry HAL_DebugTX
......@@ -331,14 +328,14 @@ HAL_EntryTable DATA
HALEntry HAL_InitDevices
HALEntry HAL_KbdScanSetup
HALEntry HAL_KbdScan
HALEntry HAL_KbdScanFinish
HALEntry HAL_KbdScanInterrupt
HALEntry HAL_KbdScanDependencies
NullEntry ; Unused
NullEntry ; Unused
NullEntry ; Unused
HALEntry HAL_PhysInfo
NullEntry ;HALEntry HAL_USBControllerInfo
HALEntry HAL_Reset
HALEntry HAL_IRQMax
......
; Copyright 2017 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:HALEntries
AREA |Asm$$Code|, CODE, READONLY, PIC
EXPORT HAL_KbdScanDependencies
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
HAL_KbdScanDependencies ROUT
ADR a1, %FT10
MOV pc, lr
10
; Modules needed for keyboard scanning, no need to list those
; before 'FirstUnpluggableModule' since they can't be unplugged
DCB "SharedCLibrary,BufferManager,DeviceFS,USBDriver,"
DCB "OHCIDriver,EHCIDriver,InternationalKeyboard", 0
END
......@@ -478,18 +478,6 @@ alloc_contig
free_contig
MOV pc, lr
EXPORT alloc_usbhal
alloc_usbhal
MOV a4, lr
BL hal_alloc
STR a1, USBHALws
MOV pc, a4
EXPORT get_usbhal
get_usbhal
LDR a1, USBHALws
MOV pc, lr
EXPORT pci_set_state
pci_set_state
STR a1, PCIState
......
......@@ -33,6 +33,7 @@
EXPORT HAL_UARTModemControl
EXPORT HAL_UARTModemStatus
EXPORT HAL_UARTDevice
EXPORT HAL_UARTDefault
GET Hdr:ListOpts
GET Hdr:Macros
......@@ -436,4 +437,12 @@ HAL_UARTDevice
MOV a1, #Device_UART2
MOV pc, lr
; int Default(void)
;
; Return the default UART for the OS to use, or -1 for none
;
HAL_UARTDefault
MOV a1, #-1
MOV pc, lr
END
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