GitLab

Detail:
  hdr/CPUClk, hdr/SR37x, s/Boot, s/CPUClk, s/SR37x - Modifed CPU clock drivers to allow the core speed & voltage to be reset to the power on defaults prior to reset/poweroff. This fixes an issue seen on Pandora where Linux will often fail to boot after RISC OS has been run, presumably due to VDD1 being too low for the initial clock speed Linux switches to.
  s/Boot - Place EHCI PHY in reset prior to reset/power off. May help with a reported issue of USB host being unreliable after RISC OS has been run (although reset/poweroff should reset the GPIO anyway)
Admin:
  Tested on Pandora & BB-xM


Version 0.82. Tagged as 'OMAP3-0_82'

Detail:
  s/SR37x, hdr/SR37x - New files containing SmartReflex driver targeting AM/DM37x chips. Initialises SmartReflex for both VDD1 & VDD2, but currently only VDD1/DPLL1 settings can be adjusted at runtime (via CPUClk HAL device)
  Makefile - Add SR37x to object list
  hdr/CPUClk - Adjust OPPTbl_Max so CPUClk workspace size is >= SR37x workspace size (both drivers share their HAL workspace, since only one can be active at once)
  hdr/GPIO - Add TPS_GPPUPDCTR1 definition
  hdr/PRCM - Add SmartReflex related registers
  hdr/omap3530 - Add "control device status" register & extra AM/DM37x revision numbers
  s/CPUClk:
  - Modify CPUClk_PreInit to try initialising the SmartReflex driver.
  - Ensure SmartReflex is disabled in the TPS if using CPUClk driver.
  - Fix 'OPP60' typo in AMDM37x table.
  - Move DPLL adjustment code into its own function to allow it to be shared with SmartReflex driver.
  - Add a few ROUTs and ASSERTs for safety.
Admin:
  Both new & old CPUClk devices tested on BB-xM


Version 0.62. Tagged as 'OMAP3-0_62'