Program the gamma table in the Pandora's LCD

Detail:
  s/Video - Added code to program the gamma table in the Pandora's LCD, as the power-on settings aren't very good
  s/Boot - Initialise the LCD at the right time
  hdr/SPI - SPI register definitions, for programming the gamma table and (eventually) a full SPI driver
Admin:
  Tested on Pandora


Version 0.84. Tagged as 'OMAP3-0_84'

VersionASM

@@ -11,13 +11,13 @@
                         GBLS    Module_HelpVersion
                         GBLS    Module_ComponentName
                         GBLS    Module_ComponentPath
-Module_MajorVersion     SETS    "0.83"
-Module_Version          SETA    83
+Module_MajorVersion     SETS    "0.84"
+Module_Version          SETA    84
 Module_MinorVersion     SETS    ""
-Module_Date             SETS    "21 Nov 2012"
-Module_ApplicationDate  SETS    "21-Nov-12"
+Module_Date             SETS    "13 Jan 2013"
+Module_ApplicationDate  SETS    "13-Jan-13"
 Module_ComponentName    SETS    "OMAP3"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/HAL/OMAP3"
-Module_FullVersion      SETS    "0.83"
-Module_HelpVersion      SETS    "0.83 (21 Nov 2012)"
+Module_FullVersion      SETS    "0.84"
+Module_HelpVersion      SETS    "0.84 (13 Jan 2013)"
                         END

VersionNum

-/* (0.83)
+/* (0.84)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        0.83
+#define Module_MajorVersion_CMHG        0.84
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                21 Nov 2012
+#define Module_Date_CMHG                13 Jan 2013
 
-#define Module_MajorVersion             "0.83"
-#define Module_Version                  83
+#define Module_MajorVersion             "0.84"
+#define Module_Version                  84
 #define Module_MinorVersion             ""
-#define Module_Date                     "21 Nov 2012"
+#define Module_Date                     "13 Jan 2013"
 
-#define Module_ApplicationDate          "21-Nov-12"
+#define Module_ApplicationDate          "13-Jan-13"
 
 #define Module_ComponentName            "OMAP3"
 #define Module_ComponentPath            "castle/RiscOS/Sources/HAL/OMAP3"
 
-#define Module_FullVersion              "0.83"
-#define Module_HelpVersion              "0.83 (21 Nov 2012)"
-#define Module_LibraryVersionInfo       "0:83"
+#define Module_FullVersion              "0.84"
+#define Module_HelpVersion              "0.84 (13 Jan 2013)"
+#define Module_LibraryVersionInfo       "0:84"

hdr/SPI

+; Copyright 2013 Castle Technology Ltd
+;
+; Licensed under the Apache License, Version 2.0 (the "License");
+; you may not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+;     http://www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+
+; SPI registers - relative to L4_McSPI1, L4_McSPI2, etc.
+MCSPI_REVISION        * &00
+MCSPI_SYSCONFIG       * &10
+MCSPI_SYSSTATUS       * &14
+MCSPI_IRQSTATUS       * &18
+MCSPI_IRQENABLE       * &1C
+MCSPI_WAKEUPENABLE    * &20
+MCSPI_SYST            * &24
+MCSPI_MODULCTRL       * &28
+MCSPI_CHxCONF         * &2C
+MCSPI_CHxSTAT         * &30
+MCSPI_CHxCTRL         * &34
+MCSPI_TXx             * &38
+MCSPI_RXx             * &3C
+MCSPI_XFERLEVEL       * &7C
+
+; Stride between per-channel registers
+MCSPI_STRIDE          * &14
+
+; Interrupt numbers
+SPI1_IRQ        * 65
+SPI2_IRQ        * 66
+SPI3_IRQ        * 91
+SPI4_IRQ        * 48
+
+        END

s/Boot

@@ -183,6 +183,7 @@ HALdescriptor   DATA
         IMPORT   BMUParams_TPS65950_TouchBook
         IMPORT   BMUParams_BQ27200_TouchBook
         IMPORT   BMUParams_BQ27500_Pandora
+        IMPORT   Video_SetPandoraGamma
 
         EXPORT   Board_Init_BeagleBoard
         EXPORT   Board_Init_DevKit8000
@@ -937,6 +938,8 @@ Board_InitDevices_Pandora
         ADRL    a1, BMUWS1
         ADRL    a2, BMUParams_BQ27500_Pandora
         BL      BMU_InitDevice
+        ; LCD gamma (done here for simplicity)
+        BL      Video_SetPandoraGamma
         EXIT
 
 Board_InitDevices_IGEPv2

s/Video

@@ -30,6 +30,7 @@
         GET     hdr.GPIO
         GET     hdr.CoPro15ops
         GET     hdr.Timers
+        GET     hdr.SPI
 
         AREA    |Asm$$Code|, CODE, READONLY, PIC
 
@@ -54,10 +55,12 @@
         EXPORT  Video_Power_VBC_DVI
         EXPORT  Video_Power_VBC_Pandora
         EXPORT  Video_Power_VBC_TouchBook
+        EXPORT  Video_SetPandoraGamma
 
         IMPORT  memcpy
         IMPORT  GPIOx_SetAsOutput
         IMPORT  GPIOx_SetOutput
+        IMPORT  HAL_CounterDelay
 
         MACRO
         CallOS  $entry
@@ -278,5 +281,121 @@ Video_TVDet_Func
         GPIO_GetInput a1, a1, a2
         EXIT
 
+Video_SetPandoraGamma ROUT
+        Entry   "v1-v4"
+        ADR     a1, PandoraGamma
+        ; Reset McSPI1 and configure channel 1
+        LDR     a2, L4_Core_Log
+        ADD     a2, a2, #L4_McSPI1-L4_Core
+        MOV     a3, #2
+        STR     a3, [a2, #MCSPI_SYSCONFIG]
+10
+        LDR     a3, [a2, #MCSPI_SYSSTATUS]
+        TST     a3, #1
+        BEQ     %BT10
+        MOV     a3, #1
+        STR     a3, [a2, #MCSPI_MODULCTRL]
+        LDR     v4, =(7<<2)+(1<<6)+(15<<7)+(2<<12)+(1<<16)
+        ADD     a2, a2, #MCSPI_STRIDE
+        STR     v4, [a2, #MCSPI_CHxCONF]
+        ; Configure display
+        MOV     a3, #2
+        MOV     a4, #&f
+        BL      td043_write
+        MOV     a3, #3
+        MOV     a4, #&df
+        BL      td043_write
+        MOV     a3, #&20
+        MOV     a4, #&f0
+        BL      td043_write
+        MOV     a3, #&21
+        MOV     a4, #&f0
+        BL      td043_write
+        ; Process gamma table
+        ; Bits 9-8 of table entries
+        MOV     v1, #2
+20
+        MOV     a4, #0
+        MOV     v2, #3
+30
+        ADD     v3, v2, v1, LSL #2
+        ADD     v3, a1, v3, LSL #1
+        ADD     ip, v2, #1
+        LDRH    v3, [v3]
+        MOV     ip, ip, LSL #1
+        AND     v3, v3, #&300
+        ORR     a4, a4, v3, LSR ip
+        SUBS    v2, v2, #1
+        BGE     %BT30
+        ADD     a3, v1, #&11
+        BL      td043_write
+        SUBS    v1, v1, #1
+        BGE     %BT20
+        ; bits 7-0
+        MOV     v1, #0
+40
+        LDRH    a4, [a1], #2
+        ADD     a3, v1, #&14
+        AND     a4, a4, #255
+        BL      td043_write
+        ADD     v1, v1, #1
+        CMP     v1, #12
+        BLT     %BT40
+        ; Done
+        EXIT
+
+td043_write     ROUT
+        Entry   "a1-a2"
+        ; In:
+        ;  a2 = SPI register block
+        ;  a3 = register
+        ;  a4 = data
+        ;  v4 = channel config
+        ; Out:
+        ;  a3-a4 corrupt
+        ; Construct 16 bit SPI data word
+        ORR     a3, a4, a3, LSL #10
+        ORR     a3, a3, #1<<8
+        ; Set force flag
+        ORR     a4, v4, #1<<20
+        STR     a4, [a2, #MCSPI_CHxCONF]
+        ; Enable channel
+        MOV     a4, #1
+        STR     a4, [a2, #MCSPI_CHxCTRL]
+        ; Write data
+        STR     a3, [a2, #MCSPI_TXx]
+        ; Wait for transmission
+10
+        LDR     a4, [a2, #MCSPI_CHxSTAT]
+        AND     a4, a4, #6
+        TEQ     a4, #6
+        BNE     %BT10
+        ; Disable channel
+        MOV     a4, #0
+        STR     a4, [a2, #MCSPI_CHxCTRL]
+        ; Clear force flag
+        STR     v4, [a2, #MCSPI_CHxCONF]
+        ; TD043 datasheet says a minimum 1ns period is needed between transfers
+        ; Chances are that amount of time has already passed, but play it safe
+        ; and wait for 1us
+        MOV     a1, #1
+        BL      HAL_CounterDelay
+        EXIT
+
+        ; Default gamma table used by Linux
+PandoraGamma
+        DCW 105
+        DCW 315
+        DCW 381
+        DCW 431
+        DCW 490
+        DCW 537
+        DCW 579
+        DCW 686
+        DCW 780
+        DCW 837
+        DCW 880
+        DCW 1023
+
         END