Use DSB/ISB directly

Reflects similar change in OMAP4-0_28.
Built, but not tested.

Version 0.95. Tagged as 'OMAP3-0_95'

VersionNum

-/* (0.94)
+/* (0.95)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  * Last processed by srccommit version: 1.1.
  *
  */
-#define Module_MajorVersion_CMHG        0.94
+#define Module_MajorVersion_CMHG        0.95
 #define Module_MinorVersion_CMHG        
-#define Module_Date_CMHG                17 Dec 2013
+#define Module_Date_CMHG                08 Mar 2014
 
-#define Module_MajorVersion             "0.94"
-#define Module_Version                  94
+#define Module_MajorVersion             "0.95"
+#define Module_Version                  95
 #define Module_MinorVersion             ""
-#define Module_Date                     "17 Dec 2013"
+#define Module_Date                     "08 Mar 2014"
 
-#define Module_ApplicationDate          "17-Dec-13"
+#define Module_ApplicationDate          "08-Mar-14"
 
 #define Module_ComponentName            "OMAP3"
 #define Module_ComponentPath            "castle/RiscOS/Sources/HAL/OMAP3"
 
-#define Module_FullVersion              "0.94"
-#define Module_HelpVersion              "0.94 (17 Dec 2013)"
-#define Module_LibraryVersionInfo       "0:94"
+#define Module_FullVersion              "0.95"
+#define Module_HelpVersion              "0.95 (08 Mar 2014)"
+#define Module_LibraryVersionInfo       "0:95"

s/Boot

@@ -31,7 +31,6 @@
         GET     hdr.Interrupts
         GET     hdr.Timers
         GET     hdr.GPIO
-        GET     hdr.Copro15ops
         GET     hdr.UART
         GET     hdr.PRCM
         GET     hdr.GPMC
@@ -848,11 +847,11 @@ HAL_InitDevices
         ; Sync cache
         MOV     a1, #0
         MCR     p15, 0, a1, c7, c11, 1 ; Clean DCache by VA to PoU
-        myDSB ; wait for clean to complete
+        DSB     SY ; wait for clean to complete
         MCR     p15, 0, a1, c7, c5, 1 ; invalidate ICache entry (to PoC)
         MCR     p15, 0, a1, c7, c5, 6 ; invalidate entire BTC
-        myDSB ; wait for cache invalidation to complete
-        myISB ; wait for BTC invalidation to complete?
+        DSB     SY ; wait for cache invalidation to complete
+        ISB     SY ; wait for BTC invalidation to complete?
         ; Now reconfigure the USER button (GPIO 4/7) to fire an FIQ
         LDR     a2, L4_Wakeup_Log
         ADD     a2, a2, #(L4_CONTROL_IDCODE-L4_Wakeup) :AND: &FF00
@@ -1226,7 +1225,7 @@ FIQRoutine
         MOV     r10, #2
         STR     r10, [r8, #INTCPS_CONTROL]
         ; Data synchronisation barrier to make sure INTC gets the message
-        myDSB
+        DSB     SY
    [ {FALSE} ; Code to call DebugCallstack on any button press
         ; Switch back to original mode
         MRS     r8, CPSR

s/Interrupts

@@ -25,7 +25,6 @@
         GET     hdr.StaticWS
         GET     hdr.Interrupts
         GET     hdr.Timers
-        GET     hdr.CoPro15ops
 
         AREA    |Asm$$Code|, CODE, READONLY, PIC
 
@@ -172,7 +171,7 @@ HAL_IRQClear
         MOV     a1, #1
         STR     a1, [a2, #INTCPS_CONTROL]
         ; Data synchronisation barrier to make sure INTC gets the message
-        myDSB
+        DSB     SY
  [ DebugInterrupts
         MOV     a1, #-1
         STR     a1, LastInterrupt_IRQ
@@ -229,7 +228,7 @@ HAL_IRQSource
         MOV     a3, #1
         STR     a3, [a2, #INTCPS_CONTROL]
         ; Data synchronisation barrier to make sure INTC gets the message
-        myDSB
+        DSB     SY
         MOV     pc, lr
 
 HAL_IRQStatus
@@ -371,7 +370,7 @@ HAL_FIQDisableAll_Loop3
         MOV     a1, #2
         STR     a1, [a2, #INTCPS_CONTROL]
         ; Data synchronisation barrier to make sure INTC gets the message
-        myDSB
+        DSB     SY
  [ DebugInterrupts
         MOV     a1, #-1
         STR     a1, LastInterrupt_FIQ
@@ -384,7 +383,7 @@ HAL_FIQClear
         MOV     a1, #2
         STR     a1, [a2, #INTCPS_CONTROL]
         ; Data synchronisation barrier to make sure INTC gets the message
-        myDSB
+        DSB     SY
  [ DebugInterrupts
         MOV     a1, #-1
         STR     a1, LastInterrupt_FIQ
@@ -455,7 +454,7 @@ HAL_FIQSource
         MOV     a3, #2
         STR     a3, [a2, #INTCPS_CONTROL]
         ; Data synchronisation barrier to make sure INTC gets the message
-        myDSB
+        DSB     SY
         MOV     pc, lr
 
 HAL_IRQMax

s/RAM

@@ -386,8 +386,8 @@ clear_ram
         MOV     a1, #0
         MCR     p15, 0, a1, c7, c5, 0
         MCR     p15, 0, a1, c7, c5, 6
-        myDSB
-        myISB
+        DSB     SY
+        ISB     SY
  ]
         MOV     pc, lr
 

s/Top

@@ -31,7 +31,6 @@
         GET     hdr.UART
         GET     hdr.Post
         GET     hdr.SDRC
-        GET     hdr.Copro15ops
         GET     hdr.GPIO
 
         AREA    |!!!ROMStart|, CODE, READONLY, PIC
@@ -263,8 +262,8 @@ relocate_code
         MOV     a1, #0
         MCR     p15, 0, a1, c7, c5, 0
         MCR     p15, 0, a1, c7, c5, 6
-        myDSB ; Wait for I-cache invalidation to complete
-        myISB ; Wait for branch predictor invalidation to complete?
+        DSB     SY ; Wait for I-cache invalidation to complete
+        ISB     SY ; Wait for branch predictor invalidation to complete?
         DebugChar a1,a2,68
         ; Jump to our new copy
         ADR     a1, relocate_code ; Keep things simple by just running through the same code again
@@ -298,7 +297,7 @@ relocate_code
 ;        MRC     p15, 0, a1, c1, c0, 2
 ;        ORR     a1, a1, #&F<<20
 ;        MCR     p15, 0, a1, c1, c0, 2
-;        DCI     &F57FF06F ; ISB {SY}
+;        ISB     SY
 ;        ; Now enable the unit
 ;        MOV     a1, #1<<30 ; EN bit
 ;        DCI     &EEE80A10 ; VMSR FPEXC, a1

s/Video

@@ -28,7 +28,6 @@
         GET     hdr.StaticWS
         GET     hdr.PRCM
         GET     hdr.GPIO
-        GET     hdr.CoPro15ops
         GET     hdr.Timers
         GET     hdr.SPI