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; Copyright 2009 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;     http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;

        GET     Hdr:ListOpts
        GET     Hdr:Macros
        GET     Hdr:System
        GET     Hdr:Machine.<Machine>
        GET     Hdr:ImageSize.<ImageSize>

        GET     Hdr:MEMM.ARM600

        GET     Hdr:Proc
        GET     Hdr:OSEntries
        GET     Hdr:HALEntries

        GET     hdr.omap3530
        GET     hdr.StaticWS
        GET     hdr.UART
        GET     hdr.Post
        GET     hdr.SDRC
        GET     hdr.Copro15ops
        GET     hdr.GPIO

        AREA    |!!!ROMStart|, CODE, READONLY, PIC

        ; Note: there must be only one fixed link from "Top" to "Boot" at +&2000
        IMPORT  rom_checkedout_ok
        EXPORT  HAL_Base
        IMPORT  HAL_DebugTX

HAL_Base

        B       start
        B       .
        B       .
        B       .
        B       .
        B       .
        B       .
        B       .
        DCD     1024*1024       ; image size (temp hack)

        ASSERT  . - HAL_Base < 0x60
        %       0x60 - (. - HAL_Base)
ROMsize
        DCD     0                               ; patched in by build system

        ENTRY
start
        DebugChar  a1,a2,65
        DebugChar  a1,a2,48
;        MVN     a1, #0
;        BL      hexnumber
;        MVN     a1, #0
;        BL      hexnumber
;        MRS     a1, CPSR ; CPSR 200001d3 - SVC32 FIQ IRQ ImpAbrt
;        BL      hexnumber
;        MRC     p15, 0, a1, c1, c0, 0 ; control register 00c5187a - IZA
;        BL      hexnumber
;        MRC     p15, 0, a1, c1, c0, 1 ; aux control register 00000042 - IBE L2EN
;        BL      hexnumber
;        MRC     p15, 1, a1, c0, c0, 1 ; cache level id register 0a000023 - OK
;        BL      hexnumber
;        MRC     p15, 0, a1, c1, c1, 2 ; nonsecure access control register 00070c00 - PLE, TLB, CL, CP10, CP11 available
;        BL      hexnumber
;        MRC     p15, 0, a1, c1, c0, 2 ; coprocessor access control register 00000000 - all disabled
;        BL      hexnumber
        B       restart

;hexnumber ; Output a1 in hex to the serial port
;        LDR     a2, =L4_UART3
;        ADR     a3, hextab
;        MOV     a4, #8
;10
;        LDRB    v1, [a2, #UART_LSR]
;        TST     v1, #THRE
;        BEQ     %BT10
;        LDRB    v1, [a3, a1, LSR #28]
;        STRB    v1, [a2, #UART_THR]
;        MOV     a1, a1, LSL #4
;        SUBS    a4, a4, #1
;        BNE     %BT10
;20
;        LDRB    v1, [a2, #UART_LSR]
;        TST     v1, #THRE
;        BEQ     %BT20
;        MOV     v1, #13
;        STRB    v1, [a2, #UART_THR]
;30
;        LDRB    v1, [a2, #UART_LSR]
;        TST     v1, #THRE
;        BEQ     %BT30
;        MOV     v1, #10
;        STRB    v1, [a2, #UART_THR]
;
;        MOV     pc, lr
;
;hextab  DCB "0123456789abcdef"

        LTORG

        MACRO
        CallOSM $entry, $reg
        LDR     ip, [v8, #$entry*4]
        MOV     lr, pc
        ADD     pc, v8, ip
        MEND

; ------------------------------------------------------------------------------
; Perform some Cortex-A8 specific CPU setup
; Then start looking for RAM
restart
        DebugChar a3,a4,48
        MSR     CPSR_c, #F32_bit+I32_bit+SVC32_mode
        DebugChar a3,a4,49
        MOV     a1, #&78 ; Matches MMUC_L+MMUC_D+MMUC_P+MMUC_W, which are now reserved bits in the Cortex spec, but should be written as 1
        MCR     p15, 0, a1, c1, c0, 0              ; MMU, caches etc off
        DebugChar a3,a4,50
        MRC     p15, 0, a1, c1, c0, 1
        BIC     a1, a1, #2
        MCR     p15, 0, a1, c1, c0, 1 ; Ensure L2 cache disabled
        DebugChar a3,a4,51

        MOV     a1, #0
        MCR     p15, 0, a1, c7, c5, 0           ; invalidate instruction cache
        DebugChar a3,a4,52
        MCR     p15, 0, a1, c8, c7, 0           ; invalidate TLBs
        DebugChar a3,a4,53

        ; Invalidate data caches. To do this we must query their sizes
        ; The register describes up to 8 cache levels, so to provide some future-proofing I might as well implement a full cache clean routine here
        MRC     p15, 1, a1, c0, c0, 1 ; Cache level ID register
        DebugChar a3,a4,54
        BIC     a1, a1, #&FF000000 ; Discard unification/coherency bits
        MOV     a2, #0 ; Current cache level
20
        DebugChar a3,a4,49
        ANDS    a3, a1, #7 ; Get flags
        BEQ     %FT10 ; Cache clean complete
        MCR     p15, 2, a2, c0, c0, 0 ; Program cache size selection register
        MRC     p15, 1, a3, c0, c0, 0 ; Get size info
        AND     v1, a3, #&7 ; log2(Line size)-2
        BIC     a3, a3, #&F0000007 ; Clear flags & line size
        MOV     v2, a3, LSL #19 ; Number of ways-1 in upper 10 bits
        MOV     v3, a3, LSR #13 ; Number of sets-1 in lower 15 bits
        ; Way number needs to be packed right up at the high end of the data word; shift it up
        CLZ     a4, v2
        MOV     v2, v2, LSL a4
        ; Set number needs to start at log2(Line size)+2
        MOV     v3, v3, LSL #4 ; Start at bit 4
        MOV     v3, v3, LSL v1 ; Start at log2(Line size)+2
        ; Now calculate the offset numbers we will use to increment sets & ways
        BIC     v4, v2, v2, LSL #1 ; Way increment
        BIC     v5, v3, v3, LSL #1 ; Set increment
        ; Now we can finally clean this cache!
        ORR     a3, a2, v3 ; Current way (0), set (max), and level
30
        MCR     p15, 0, a3, c7, c6, 2 ; Invalidate
        ADDS    a3, a3, v4 ; Increment way
        BCC     %BT30 ; Overflow will occur once ways are enumerated
        TST     a3, v3 ; Are set bits all zero?
        SUBNE   a3, a3, v5 ; No, so decrement set and loop around again
        BNE     %BT30
        ; This cache is now clean. Move on to the next level.
        DebugChar a3,a4,50
        ADD     a2, a2, #2
        MOVS    a1, a1, LSR #3
        BNE     %BT20
10
        DebugChar a1,a2,51

        ADRL    v1, HAL_Base + 64*1024          ; v1 -> RISC OS image

        LDR     v8, [v1, #OSHdr_Entries]
        ADD     v8, v8, v1                      ; v8 -> RISC OS entry table

        ARM_read_control a1
        ; We assume that ARMs with an I cache can have it enabled while the MMU is off.
        [ :LNOT:CacheOff
        ORR   a1, a1, #MMUC_I
        ]
        ARM_write_control a1                                ; whoosh

        ; Keep a soft copy of the CR in a banked register (R13_und)
        MSR     CPSR_c, #F32_bit+I32_bit+UND32_mode
        MOV     sp, a1
        ; Switch into SVC32 mode (we may have been in SVC26 before).
        MSR     CPSR_c, #F32_bit+I32_bit+SVC32_mode

        MOV     sb, #0

        ; Initialise RAM
        BL      init_ram

        ; The first 4K of the first registered block of RAM is used by RISC OS's init code, and also contains the stack
        ; To keep things simple and safe, we'll relocate the HAL and OS image to the top end of RAM
        ; Although with the beagleboard we know we'll be booted from RAM, this code has been written so that it should work if running from ROM

        ; First, identify the top end of RAM
        ; Then check if we intersect it
        ; If we do, first copy ourselves down
        ; Then copy ourselves up

relocate_code
        DebugChar a1,a2,66
        BL      get_end_of_ram
        DebugChar v1,v2,67

        ; How big are we?
        ADRL    v1, HAL_Base + 64*1024
        LDR     v2, [v1, #OSHdr_ImageSize]
        SUB     v1, v1, #64*1024 ; Start of HAL
        ADD     v2, v2, #64*1024 ; Size of HAL+OS
        ADD     v3, v1, v2 ; End of OS
        MOV     v4, a1 ; End of RAM
        SUB     v5, v4, v2 ; New start address of HAL
        CMP     v1, v5
        BEQ     %FT10 ; No copy needed
        BGT     %FT20 ; We're in some ROM above RAM. OK to continue with copy.
        CMP     v3, v5
        BLE     %FT20 ; We're in some ROM/RAM below our copy destination. OK to continue with copy.
        ; Else we currently overlap the area we want to copy ourselves into.
        SUB     v5, v1, v2 ; Copy the HAL+OS to just before itself
20
        MOV     a1, v5
        MOV     a2, v1 ; Copy source
        MOV     a3, v2
30
        LDR     a4, [a2], #4
        STR     a4, [a1], #4
        SUBS    a3, a3, #4
        BGT     %BT30
        ; Invalidate I-cache
        MOV     a1, #0
        MCR     p15, 0, a1, c7, c5, 0
        DebugChar a1,a2,68
        ; Jump to our new copy
        ADR     a1, relocate_code ; Keep things simple by just running through the same code again
        SUB     a2, v5, v1
        ADD     a1, a1, a2 ; relocate our branch target
        ADD     v8, v8, a2 ; Update OS entry table ptr
        MOV     pc, a1
10
        ; Copy completed OK.
        ; v2 = size of HAL+OS
        ; v4 = end of OS/RAM
        ; v5 = start of HAL
        ; v8 = OS entry table ptr
        DebugChar a1,a2,69
        ; Clear RAM up to v5
        MOV     a1, v5
        BL      clear_ram

        DebugChar a1,a2,70

        B       rom_checkedout_ok

; ------------------------------------------------------------------------------
; The RAM setup is locked in the first 8k of ROM
; as is the flash recovery code
        GET     RAM.s
        LTORG
        ALIGN   sizeofRecoveryArea

        END