Commit 5992585c authored by John Ballance's avatar John Ballance
Browse files

Added SWI to expose receive fifo thresholds and flow control parameters

Detail:
Admin:


Version 0.25. Tagged as 'EtherTH-0_25'
parent 477befd4
......@@ -11,13 +11,13 @@
GBLS Module_HelpVersion
GBLS Module_ComponentName
GBLS Module_ComponentPath
Module_MajorVersion SETS "0.24"
Module_Version SETA 24
Module_MajorVersion SETS "0.25"
Module_Version SETA 25
Module_MinorVersion SETS ""
Module_Date SETS "28 Nov 2016"
Module_ApplicationDate SETS "28-Nov-16"
Module_Date SETS "20 Jan 2017"
Module_ApplicationDate SETS "20-Jan-17"
Module_ComponentName SETS "EtherTH"
Module_ComponentPath SETS "mixed/RiscOS/Sources/Networking/Ethernet/EtherTH"
Module_FullVersion SETS "0.24"
Module_HelpVersion SETS "0.24 (28 Nov 2016)"
Module_FullVersion SETS "0.25"
Module_HelpVersion SETS "0.25 (20 Jan 2017)"
END
/* (0.24)
/* (0.25)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.24
#define Module_MajorVersion_CMHG 0.25
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 28 Nov 2016
#define Module_Date_CMHG 20 Jan 2017
#define Module_MajorVersion "0.24"
#define Module_Version 24
#define Module_MajorVersion "0.25"
#define Module_Version 25
#define Module_MinorVersion ""
#define Module_Date "28 Nov 2016"
#define Module_Date "20 Jan 2017"
#define Module_ApplicationDate "28-Nov-16"
#define Module_ApplicationDate "20-Jan-17"
#define Module_ComponentName "EtherTH"
#define Module_ComponentPath "mixed/RiscOS/Sources/Networking/Ethernet/EtherTH"
#define Module_FullVersion "0.24"
#define Module_HelpVersion "0.24 (28 Nov 2016)"
#define Module_LibraryVersionInfo "0:24"
#define Module_FullVersion "0.25"
#define Module_HelpVersion "0.25 (20 Jan 2017)"
#define Module_LibraryVersionInfo "0:25"
......@@ -123,6 +123,26 @@ EnetRxBLast # 4 ; mbuf linking to this, or null
EnetRxBNext # 4 ; mbuf this links to, or null
EnetRxBSize # 0 ; size of this
; Flow control values
EnetPauseLen * 1000*24 ; 1000 full packets
; 0xffff max * 512bit times
; hence 1536 byte packet is
; (1536 * 8) / 512 = 24 (0x18)
EnetInterPkt * 27 ; 8 to 27 byte times(64-217bits)
; next 2 control fifo -> ram dma
EnetRxSecFull * 0x10 ; 8 byte lumps .. flag data in
; fifo above this so start dma
; MUST be > EnetRxAmty
; if 0, then only transfr when
; frame is completely received
EnetRxAmty * 0x8 ; (min 6)stop rx dma below this
; next 2 control chip -> fifo dma
EnetRxSecMty * 0x84 ; flag to remote that fifo is
; getting full, send pause frame
; till it gets below this, then
; send continue
EnetRxAfull * 0x4 ; (min 4) min free space for MAC
; to leave in FIFO
;
; Ethernet chip register address offsets from chip base
......
......@@ -581,21 +581,14 @@ ChipInit
ldr r0, [r4, #HW_ENET_MIBC_ADDR]
bic r0, r0, #(1<<BIT_ENET_MIBC_DIS)
str r0, [r4, #HW_ENET_MIBC_ADDR]
ldr r0, =&1fff0 ; pause duration
str r0, [r4, #HW_ENET_OPD_ADDR]
ldr r3, =EnetPauseLen +(EnetInterPkt<<16)
ldr r2, =EnetRxSecFull+(EnetRxAmty<<8)+(EnetRxAfull<<16)+(EnetRxSecMty<<24)
bl SetThresholds
mov r0, #&100 ; tx store and forward enable,
; whoe frame to fifo before tx
; whole frame to fifo before tx
; mov r0, #&24 ; tx store and forward disable,
; &600 bytes before mac startstart
; &600 bytes before mac start
str r0, [r4, #HW_ENET_TFWR_ADDR]
mov r0, #&0 ; (* 8 bytes) (0 = whole thing)
str r0, [r4, #HW_ENET_RSFL_ADDR] ; rx section full
mov r0, #&6 ; (* 8 bytes)
str r0, [r4, #HW_ENET_RAEM_ADDR] ; rx almost empty
mov r0, #&4 ; (* 8 bytes)
str r0, [r4, #HW_ENET_RAFL_ADDR] ; rx almost full
mov r0, #&4 ; (* 8 bytes)
str r0, [r4, #HW_ENET_RSEM_ADDR] ; rx section empty
mov r0, #&0 ; (* 8 bytes) (0=never)
str r0, [r4, #HW_ENET_TSEM_ADDR] ; tx section empty
mov r0, #&4 ; min for AEM is 4
......@@ -745,6 +738,49 @@ ChipInit
2
EXIT
;
; r2 = RSFL << 0
; + RAEM << 8
; + RAFL << 16
; + RSEM << 24
; r3 = PauseDuration
; + TIPG << 16
SetThresholds
Entry "r0,r1,r4"
ldr r4, ChipBase ; point to ethernet chip
and r0, r2, #&ff ; (* 8 bytes) (0 = whole thing)
str r0, [r4, #HW_ENET_RSFL_ADDR] ; rx section full
mov r0, r2, lsr #8
and r0, r0, #&ff ; (* 8 bytes)
str r0, [r4, #HW_ENET_RAEM_ADDR] ; rx almost empty
mov r0, r2, lsr #16
and r0, r0, #&ff ; (* 8 bytes)
str r0, [r4, #HW_ENET_RAFL_ADDR] ; rx almost full
mov r0, r2, lsr #24
and r0, r0, #&ff ; (* 8 bytes)
str r0, [r4, #HW_ENET_RSEM_ADDR] ; rx section empty
mov r0, r3, lsr #16
and r0, r0, #&1f ; min 8, max 27
str r0, [r4, #HW_ENET_TIPG_ADDR] ; set
mov r0, r3, lsl #16
mov r0, r0, lsr #16
str r0, [r4, #HW_ENET_OPD_ADDR] ; * 512bit periods
EXIT
GetThresholds
Entry "r0,r1,r4"
ldr r4, ChipBase ; point to ethernet chip
ldr r2, [r4, #HW_ENET_RSEM_ADDR] ; rx section empty
ldr r0, [r4, #HW_ENET_RAFL_ADDR] ; rx almost full
orr r2, r0, r2, lsl #8
ldr r0, [r4, #HW_ENET_RAEM_ADDR] ; rx almost empty
orr r2, r0, r2, lsl #8
ldr r0, [r4, #HW_ENET_RSFL_ADDR] ; rx section full
orr r2, r0, r2, lsl #8
ldr r3, [r4, #HW_ENET_OPD_ADDR] ; * 512bit periods
bic r3, r3, #&10000 ; clear the opcode bit
ldr r0, [r4, #HW_ENET_TIPG_ADDR] ;
orr r3, r3, r0, lsl #16
EXIT
LTORG
; get a free claim buf
......
......@@ -438,6 +438,7 @@ SWI_DecodeTable
DCB "Filter",0
DCB "Stats",0
DCB "MulticastRequest",0
DCB "GetSetThresholds",0
ALIGN
SWI_Code ROUT
......@@ -464,6 +465,7 @@ JumpTable
b swi_Filter
b swi_Stats
b swi_MulticastRequest
b swi_GetSetThresholds
EndOfJumpTable
; on exit r1 = 404, the version of DCI we support
......@@ -747,6 +749,30 @@ swi_MulticastRequest
; DebugReg r1,"SWIMulticast for unit "
EXIT
; on entry,
; r1 = unit (currently only 0)
; r2 = -1 to read
; returns r2, r3 as below
; else
; r2 = RSFL << 0
; + RAEM << 8
; + RAFL << 16
; + RSEM << 24
; r3 = PauseDuration
; + TIPG << 16
; returns new r2, r3 values
;
swi_GetSetThresholds
Entry
cmp r2, #-1
; DebugReg r1,"SWIGetSetThresholds for unit "
blne SetThresholds
; now build return values
buildret
bl GetThresholds
EXIT
DIBname = EtherTHDCIName,0
ModLocn = "iMx6 CPU",0
VarValName = "Inet$$EtherType",0
......
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