* Added support for 24LC64 8K EEPROM (untested).

* Integrated Ursula fast service call dispatch code.
* Added Interruptible32bitModes from Ursula.
* Stopped allowing ROM modules (other than the Kernel/UtilityModule) to write
  to the hardware vectors in 26-bit mode.

Version 4.81. Tagged as 'Kernel-4_81'

VersionASM

@@ -6,9 +6,9 @@
 			GBLS	Module_MinorVersion
 			GBLS	Module_Date
 			GBLS	Module_FullVersion
-Module_MajorVersion	SETS    "4.80"
-Module_Version          SETA    480
+Module_MajorVersion	SETS    "4.81"
+Module_Version          SETA    481
 Module_MinorVersion	SETS	""
-Module_Date		SETS    "04 Jun 1999"
-Module_FullVersion      SETS    "4.80"
+Module_Date		SETS    "03 Aug 1999"
+Module_FullVersion      SETS    "4.81"
                         END

VersionNum

-/* (4.80)
+/* (4.81)
  *
  * This file is automatically maintained by srccommit, do not edit manually.
  *
  */
-#define Module_MajorVersion_CMHG     	4.80
+#define Module_MajorVersion_CMHG     	4.81
 #define Module_MinorVersion_CMHG	
-#define Module_Date_CMHG      		04 Jun 1999
+#define Module_Date_CMHG      		03 Aug 1999
 
-#define Module_MajorVersion     	"4.80"
-#define Module_Version                  480
+#define Module_MajorVersion     	"4.81"
+#define Module_Version                  481
 #define Module_MinorVersion		""
-#define Module_Date      		"04 Jun 1999"
+#define Module_Date      		"03 Aug 1999"
 
-#define Module_FullVersion              "4.80"
+#define Module_FullVersion              "4.81"

hdr/KernelWS

@@ -965,6 +965,15 @@ SyncCodeA_sema  #       1       ; re-entrancy semaphore for SynchroniseCodeAreas
  ! 0, "ARMA_Cleaner_flipflop at ":CC::STR:(ARMA_Cleaner_flipflop)
  ! 0, "SyncCodeA_sema (byte) at ":CC::STR:(SyncCodeA_sema)
                ]
+
+                AlignSpace 4
+Serv_SysChains          # 4          ;anchor for block handling 'system' service numbers, in range 1 to 255
+Serv_UsrChains          # 4          ;anchor for block handling 'user' service numbers, > 255
+Serv_AwkwardChain       # 4          ;anchor for chain handling non-compliant modules (no service table)
+      ! 0, "Serv_SysChains        at ":CC::STR:(Serv_SysChains)
+      ! 0, "Serv_UsrChains        at ":CC::STR:(Serv_UsrChains)
+      ! 0, "Serv_AwkwardChain     at ":CC::STR:(Serv_AwkwardChain)
+
  [ StorkPowerSave
 ;;;   AlignSpace 4
 ;;;VIDCExternalSoftCopy #  4       ; soft copy of VIDCExternal

s/ARM600

@@ -3595,14 +3595,23 @@ ProcessTransfer ENTRY "r1-r7,r12"
 ; do it in words if >= 4 bytes, so word writes to VIDC work for example
 
 25
- [ {TRUE}
         CMP     r2, #&1C                                ; if in abort area (but allow any access to &1C)
- |
-        CMP     r2, #&20                                ; if in abort area
- ]
+  [ OnlyKernelCanAccessHardwareVectors
+        BHS     %FT22
+        CMP     r4, #ROM                                ; and executing outside the kernel
+        BLO     %FT23
+        ADRL    lr, EndOfKernel
+        CMP     r4, lr
+        BLO     %FT22
+23
+        MOV     r5, #&20                                ; then set end-of-section = 32
+        B       Fault                                   ; and check user list
+22
+  |
         CMPCC   r4, #ROM                                ; and executing out of RAM
         MOVCC   r5, #&20                                ; then set end-of-section = 32
         BCC     Fault                                   ; and check user list
+  ]
 
         SetMode SVC32_mode, lr                          ; go into SVC32 so we can poke or peek vector area
 

s/ArthurSWIs

@@ -706,6 +706,89 @@ Issue_Service ROUT             ; R1 is service number, R2 may be a parameter
        CMP      r1, #Service_NewApplication
        BEQ      checkmoshandlers
 
+
+  [ ChocolateService
+05
+       CMP      R1,#ServMinUsrNumber
+       BHS      %FT84
+;call anyone on the appropriate Sys chain
+       LDR      R10,=Serv_SysChains
+       LDR      R10,[R10]
+       CMP      R10,#0
+       BEQ      %FT88
+       LDR      R11,[R10,R1,LSL #2]             ;pick up the chain anchor
+80
+;call everyone on the chain, passing R1 value from chain if appropriate
+       CMP      R11,#0
+       BEQ      %FT88
+       LDR      R10,[R11,#ServChain_Size]
+       ADD      R11,R11,#ServChain_HdrSIZEOF    ;start of chain
+       ADD      R10,R10,R11                     ;end of chain
+82
+       CMP      R11,R10
+       BHS      %FT88
+       Push     "R10"
+       MOV      R10,R1
+       LDR      R9,[R11,#ServEntry_R1]
+       TEQ      R9,#0                           ; 0 means pass service number as normal
+       MOVNE    R1,R9                           ; else pass R1 value from chain (will be service index)
+       LDR      R12,[R11,#ServEntry_WSpace]
+       LDR      R9,[R11,#ServEntry_Code]
+       MOV      lr, pc                          ; link inc. PSR, mode
+       MOV      pc, R9
+       CMP      R1, #Service_Serviced
+       MOVNE    R1,R10                          ; restore R1 unless claimed
+       Pull     "R10"
+       BEQ      %FT01
+       ADD      R11,R11,#ServEntry_SIZEOF
+       B        %BT82
+;
+;call anyone on the appropriate Usr chain
+84
+       LDR      R10,=Serv_UsrChains
+       LDR      R10,[R10]
+       CMP      R10,#0
+       BEQ      %FT88
+       ServHashFunction R9,R1
+       LDR      R11,[R10,R9,LSL #2]             ;pick up the chain-array anchor
+       CMP      R11,#0
+       BEQ      %FT88
+       LDR      R10,[R11,#ServUChArray_Size]
+       ADD      R11,R11,#ServUChArray_HdrSIZEOF ;start of list
+       ADD      R10,R10,R11                     ;end of list
+86
+       CMP      R11,R10
+       BHS      %FT88
+       LDR      R9,[R11,#ServUChEntry_ServiceNo]
+       TEQ      R9,R1
+       ADDNE    R11,R11,#ServUChEntry_SIZEOF
+       BNE      %BT86
+       LDR      R11,[R11,#ServUChEntry_ChainAnchor]  ;found chain for this service number
+       B        %BT80
+;
+;call everyone on the chain of Awkward modules, always passing service number in R1
+88
+       LDR      R10,=Serv_AwkwardChain
+       LDR      R11,[R10]
+       CMP      R11,#0
+       BEQ      %FT01
+       LDR      R10,[R11,#ServChain_Size]
+       ADD      R11,R11,#ServChain_HdrSIZEOF    ;start of chain
+       ADD      R10,R10,R11                     ;end of chain
+90
+       CMP      R11,R10
+       BHS      %FT01
+       LDR      R12,[R11,#ServEntry_WSpace]
+       LDR      R9,[R11,#ServEntry_Code]
+       MOV      lr, pc                          ; link inc. PSR, mode
+       MOV      pc, R9
+       CMP      R1, #Service_Serviced
+       BEQ      %FT01
+       ADD      R11,R11,#ServEntry_SIZEOF
+       B        %BT90
+
+  | ;IF/ELSE ChocolateService
+
 05     MOV      R10, #Module_List
 03     LDR      R10, [R10, #Module_chain_Link]
        CMP      R10, #0
@@ -747,6 +830,8 @@ Issue_Service ROUT             ; R1 is service number, R2 may be a parameter
        BNE      %BT04
        Pull    "R9-R12, PC"
 
+  ] ;ChocolateService
+
 01     CMP      R1, #Service_ReleaseFIQ
        Pull    "R9-R12, PC",NE
        STRB     R1, [R1, #MOShasFIQ-Service_ReleaseFIQ]

s/GetAll

@@ -326,6 +326,15 @@ LateAborts      SETL    MEMM_Type = "ARM600" :LAND: {TRUE}
                 GBLL    ShrinkableDAs           ; if true, support Shrinkable Dynamic Areas (eg. CacheFS)
 ShrinkableDAs   SETL    {TRUE}
 
+                GBLL    Interruptible32bitModes
+Interruptible32bitModes SETL {TRUE}             ;if true, limited 32-bit mode code support (interrupt handler does not assume
+                                                ; 26-bit foreground), also allows faster, 32-bit APCS version of FPEmulator
+
+                GBLL    OnlyKernelCanAccessHardwareVectors
+OnlyKernelCanAccessHardwareVectors SETL {TRUE}  ; if true, only the Kernel is permitted to write to the hardware vectors
+                                                ; while in 26-bit mode. If false, the whole ROM can (including BASIC
+                                                ; and the Shared C Library - eg any memcpy!)
+
                 GBLL    StrongARM
                 GBLL    SAWBbroken              ;whether StrongARM Write Buffer is broken (pass 1 silicon only)
                 GBLL    SAcleanflushbroken      ;whether StrongARM single MCR for DC clean+flush broken (is always for SA110)
@@ -352,6 +361,20 @@ ARM810fastclock        SETL {FALSE} :LAND: ARM810support
 ARM810usePLL           SETL {TRUE}  :LAND: ARM810fastclock
 ARM810_POST            SETL {FALSE} :LAND: ARM810support
 
+                ;mjs
+                ;Chocolate flavours implemented for Ursula, but they are generally useful performance enhancements
+                ;(not all Ursula performance improvements are flagged with Chocolate - eg. simple changes such as slicker SWI
+                ;despatch and wider SWI hashing)
+                ;
+                ;disabled at run time if not StrongARM
+                GBLL    ChocolateOSMod          ;whether to reduce SysHeap stress in module handling
+                GBLL    ChocolateService        ;whether to implement fast module service call distribution (uses table introduced
+                                                ;into module format by Ursula API
+
+ChocolateOSMod         SETL {TRUE}
+ChocolateService       SETL {TRUE}
+
+
                 GBLL    VCOstartfix              ;code in early kernel to fix VCO start problem on A7000 (esp. 7500FE)
 VCOstartfix     SETL    {TRUE}
 

s/HeapMan

@@ -383,8 +383,12 @@ inspect_IRQ_stack
         LDR     R11, [R11]
         CMP     R11, #0
         BEQ     iis_end
+   [ Interruptible32bitModes
+        LDR     R10, [R11, #4*8]        ; Get LR from IRQ stack
+   |
         LDR     R10, [R11, #4*7]
         BIC     R10, R10, #ARM_CC_Mask
+   ]
         ADR     R12, first_heap_address_to_trap
         CMP     R10, R12
         ADRGEL  R12, HeapCode_end
@@ -405,8 +409,16 @@ inspect_IRQ_stack
      $HeapBadAsModuleKET
 
          ADRL   R10, heapopdoneinbackground
+     [ Interruptible32bitModes
+         STR    R10, [R11, #4*8]               ; return address zapped
+         LDR    R10, [R11, #4*6]               ; get stored SPSR
+         BIC    R10, R10, #&FF
+         ORR    R10, R10, #I32_bit:OR:SVC26_mode
+         STR    R10, [R11, #4*6]               ; return into SVC26 mode with IRQs disabled
+     |
          ORR    R10, R10, #SVC_mode+I_bit
          STR    R10, [R11, #4*7]               ; return address zapped
+     ]
 
          Push  "R0-R3, lr"
 

s/Kernel

@@ -845,6 +845,72 @@ Do_CallBack                                    ; CallBack allowed:
         MOV     R12, #CallAd_ws
         LDMIA   R12, {R12, PC}                ; jump to CallBackHandler
 
+; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;
+; Ursula:
+; this is only used by the interrupt handler, to allow callbacks when
+; foreground is 32-bit user, rather than 26-bit user
+;
+; currently only supports transient callbacks - traditional callback handler
+; cannot be called because it contains its own 32-bit unaware return sequence
+;
+
+back_to_user32
+        mrs    AL, r10, CPSR_all
+        ORR    r10, r10, #I32_bit :OR: SVC32_mode ;move up to SVC32 from SVC26, interrupts off
+        msr    AL, CPSR_all, r10
+        Pull   "r10"
+        msr    AL, SPSR_all, r10                  ;PSR for return, stacked by interrupt handler
+        Pull   "r10-r12"
+        MOVS    PC, lr                            ;return to address in lr, restoring CPSR from SPSR
+
+Do_CallBack32                                  ; CallBack allowed:
+        TST     r11, #CBack_VectorReq          ; now process any vector entries
+        Push    lr, NE
+        BLNE    process_callback_chain
+        Pull    lr, NE
+
+  [ {TRUE}   ;currently can't allow call to Callback handler
+
+        B       back_to_user32
+
+  |
+        ;this won't work with traditional callback handler (which has its own
+        ;return code that won't return successfully to 32-bit user mode)
+
+        TST     r11, #CBack_OldStyle
+        BEQ     back_to_user32
+
+; Check that SVC_sp is empty (apart from r10-r12), i.e. system truly is idle
+        LDR     r11, =SVCSTK-3*4                ; What SVC_sp should be if system idle
+        CMP     sp, r11                         ; Stack empty?
+        BLO     back_to_user32                  ; No then no call back
+
+        TEQP    PC, #SVC_mode+I_bit             ; ints off while flag updated
+        LDRB    r11, [r10, #CallBack_Flag]
+        BIC     r11, r11, #CBack_Postpone+CBack_OldStyle
+        STRB    r11, [r10, #CallBack_Flag]
+
+        MOV     r12, #0
+        LDR     R12, [R12, #CallBf]
+        STR     r14, [r12, #4*15]             ; user PC
+        MOV     r14, r12
+        Pull   "r10-r12"
+  [ SASTMhatbroken
+        STMIA   r14!,{r0-r12}
+        STMIA   r14,{r13,r14}^                ; user registers
+        NOP
+        SUB     r14,r14,#13*4
+  |
+        STMIA   r14, {r0-r14}^                ; user registers
+  ]
+
+        MOV     R12, #CallAd_ws
+        LDMIA   R12, {R12, PC}                ; jump to CallBackHandler
+
+  ]
+
+
 ; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 ; Also called from source.pmf.key, during readc
 

s/NewIRQs

@@ -31,6 +31,107 @@
         ALIGN 32
         ]
 
+    [ Interruptible32bitModes
+
+Initial_IRQ_Code ROUT
+        SUB     lr, lr, #4
+        Push    "r0, lr"
+        mrs     AL, lr, SPSR_all
+        Push    "r1-r3, r11, r12, lr"
+; ** For Pete's sake remember to change the heap manager if you change the above
+; ** register list!!!!!!! And the [sp_irq, #4*5] below
+
+        BIC     r0, lr, #&1F            ; clear out foreground mode bits
+        ORR     r0, r0, #I32_bit + IRQ26_mode ; force IRQ_26 mode and I_bit set
+        msr     AL, CPSR_all, r0
+
+        MOV     r12, #0
+        LDR     r0, [r12, #IRQsema]
+        Push    r0
+        STR     sp_irq, [r12, #IRQsema]
+        MOV     lr, pc
+        LDR     pc, [r12, #IRQ1V]
+
+; IRQ1V called with r0-r3,r11,r12 trashable. r12=0
+
+; Stu has a theory that 1N cycle can be saved by the default IRQ1V pointing
+; at a location containing a branch to our code; we then do something like
+;  LDR R0, [R12, #IRQ1V]
+;  CMP R0, #OurIRQ1V
+;  BNE somebodysonIRQ1V
+;  .... fall into default IRQ1V code
+
+        MOV      r11, #0
+        Pull     r0
+        STR      r0, [r11, #IRQsema]
+
+        mrs      AL, r0, CPSR_all
+        ORR      r0, r0, #&10
+        msr      AL, CPSR_all, r0               ; switch back to IRQ32 mode
+
+        LDRB     r11, [r11, #CallBack_Flag]
+        TEQ      r11, #0
+        Pull     "r1-r3, r11, r12, lr", EQ
+        msr      EQ, SPSR_all, lr
+        Pull     "r0, pc", EQ, ^
+
+        TST      r11, #CBack_Postpone
+        LDREQ    lr, [sp_irq, #4*5]     ; get SPSR off stack
+        TSTEQ    lr, #I32_bit :OR: &0F  ; check we came from USR26 or USR32 mode, with IRQs enabled
+        Pull     "r1-r3, r11, r12, lr", NE
+        msr      NE, SPSR_all, lr
+        Pull     "r0, pc", NE, ^
+
+        TST      lr, #&10               ; check whether USR26 or USR32
+        BNE      IRQ_callback32
+
+; Do a CallBack: asked for, not postponed, and we're returning into USR26 mode.
+
+        ASSERT   IRQ32_mode :AND: SVC32_mode = IRQ32_mode ; so the following dodgy ops work
+
+        Pull     "r1-r3, r11, r12"
+        mrs      AL, r0, CPSR_all
+        ORR      r0, r0, #SVC32_mode
+        msr      AL, CPSR_all, r0
+        Push     "r10-r12"                               ; push r10-r12 onto the SVC stack
+        BIC      r0, r0, #IRQ32_mode :EOR: SVC32_mode
+        msr      AL, CPSR_all, r0
+        Pull     "r10-r12"                      ; SPSR, R0, LR really
+        BIC      r0, r0, #&1F
+        ORR      r0, r0, #SVC26_mode
+        msr      AL, CPSR_all, r0
+        AND      r0, r10, #&F0000000            ; plop flags into LR...
+        ORR      lr, r12, r0
+        AND      r0, r10, #I32_bit:OR:F32_bit
+        ORR      lr, lr, r0, LSL #IF32_26Shift  ; and the I and F flags (32-bit mode)
+        MOV      r0, r11                        ; restore original R0
+        MOV      r10, #0
+        LDRB     r11, [r10, #CallBack_Flag]
+        B        Do_CallBack
+
+; Do a CallBack32: asked for, not postponed, and we're returning into USR32 mode.
+;
+IRQ_callback32
+        Pull     "r1-r3, r11, r12"
+        mrs      AL, r0, CPSR_all
+        ORR      r0, r0, #SVC32_mode
+        msr      AL, CPSR_all, r0
+        Push     "r10-r12"                               ; push r10-r12 onto the SVC stack
+        BIC      r0, r0, #IRQ32_mode :EOR: SVC32_mode
+        msr      AL, CPSR_all, r0
+        Pull     "r10-r12"                      ; SPSR, R0, LR really
+        BIC      r0, r0, #&1F
+        ORR      r0, r0, #SVC26_mode
+        msr      AL, CPSR_all, r0
+        Push     "r10"                          ; push SPSR onto SVC stack (PSR for return)
+        MOV      lr, r12                        ; address for return
+        MOV      r0, r11                        ; restore original R0
+        MOV      r10, #0
+        LDRB     r11, [r10, #CallBack_Flag]
+        B        Do_CallBack32
+
+  | ;Interruptible32bitModes
+
 Initial_IRQ_Code ROUT
         SUB      lr, lr, #4
         Push     "r0-r3, r11, r12, lr"
@@ -41,8 +142,6 @@ Initial_IRQ_Code ROUT
  ]
 
  [ CPU_Type = "ARM600"
-        BIC     pc, pc, #&FC000000      ; get back out of shadow ROM
-        NOP                             ; (this instruction skipped)
         mrs     AL, r0, SPSR_all        ; r0 = saved PSR
         AND     r1, r0, #I32_bit + F32_bit ; r1 = caller I&F flags, in ARM6 place
         ORR     lr, lr, r1, LSL #IF32_26Shift ; put IF in place
@@ -100,6 +199,8 @@ Initial_IRQ_Code ROUT
         LDRB     r11, [r10, #CallBack_Flag]
         B        Do_CallBack
 
+  ] ;Interruptible32bitModes
+
         LTORG
 
 ; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

s/PMF/i2cutils

@@ -34,6 +34,7 @@
 ; 12-Jun-97  TMD   (Really) fix OTP access problem.
 ; 17-Sep-98  KJB   Add support for 16K 24C128 EEPROM.
 ; 21-Sep-98  KJB   Add OS_NVMemory SWI.
+; 30-Jul-99  KJB   Add support for 8K 24C64 EEPROM.
 
 PhysChecksum	*	(((CheckSumCMOS + &30) :MOD: &F0) + &10)
 
@@ -46,6 +47,7 @@ RTCAddress		*	&a0     ; traditional RTC / 240 byte CMOS
 E2ROMAddress		*	&a8     ; 24C08 device - 512 byte or 1K
 E2ROMAddress2K		*	&e0     ; 24C174 device - 2K
 E2ROMAddress2K_OTP	*	&60     ; 24C174 device - OTP section
+E2ROMAddress8K          *       &a2     ; 24C64 device - 8K
 E2ROMAddress16K         *       &a8     ; 24C128 device - 16K
   ]
 
@@ -1555,6 +1557,19 @@ InitCMOSCache	ENTRY "r0-r5"
       [ ClockNVMemoryFast
         MOVVC   R3, #3          ; Fast speed setting (1.5s delays)
       ]
+        BVC     %FT5
+
+; Have we got an 8K device?
+
+        MOV     r1, #E2ROMAddress8K
+	MOV	r0, #E2ROMAddress8K
+	BL	DummyAccess
+	MOVVC	R4, #32
+        MOVVC   R5, #5          ; 32 byte page size
+      [ ClockNVMemoryFast
+        MOVVC   R3, #3          ; Fast speed setting (1.5s delays)
+      ]
+
 	MOVVS   R1, #RTCAddress
         MOVVS   R5, #8          ; 256 byte page size for CMOS
 

s/Utility

@@ -46,11 +46,30 @@ UtilityMod
 Module_BaseAddr SETA UtilityMod
 
  [ :LNOT: DriversInKernel
+  [ ChocolateService
+    ;service table
+    ;
+        ASSERT Service_BufferStarting < Service_DeviceFSCloseRequest
+    ;
+Util_ChocServTab
+        DCD    0                            ;flags word
+        DCD    Util_ChocService-UtilityMod  ;offset to handler
+        DCD    Service_BufferStarting       ;service 1
+        DCD    Service_DeviceFSCloseRequest ;service 2
+        DCD    0                            ;terminator
+        DCD    Util_ChocServTab-UtilityMod  ;table anchor
+  ]
 Util_Service ROUT
+  [ ChocolateService
+        MOV     r0, r0   ;magic instruction for new service table format
+  ]
         TEQ     r1, #Service_BufferStarting
         TEQNE   r1, #Service_DeviceFSCloseRequest
         MOVNES  pc, lr
-
+  [ ChocolateService
+    ;entry point excluding pre-rejection code
+Util_ChocService
+  ]
         TEQ     r1, #Service_BufferStarting
         BNE     %FT10
         Push    "r0-r3,lr"