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Commit f39e1298 authored by Mike Stephens's avatar Mike Stephens
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StrongARM is back, and this time it's provisional! 

IOMD HAL:
  enables fast clock for StrongARM on Medusa h/w

Kernel:
  ARMops for StrongARM implemented. Tested moderately on
  HAL/32-bit minimal desktop build for Risc PC. Could do
  with more testing later. eg. does reentrant cache
  cleaning support really work?
  Lazy task swapping is enabled for revT or later, wahey.

Version 5.35, 4.79.2.42. Tagged as 'Kernel-5_35-4_79_2_42'
parent 63a6ffec
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VersionASM
View file @ f39e1298
......@@ -13,12 +13,12 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.41"
Module_Date SETS "26 Jun 2001"
Module_ApplicationDate2 SETS "26-Jun-01"
Module_ApplicationDate4 SETS "26-Jun-2001"
Module_MinorVersion SETS "4.79.2.42"
Module_Date SETS "27 Jun 2001"
Module_ApplicationDate2 SETS "27-Jun-01"
Module_ApplicationDate4 SETS "27-Jun-2001"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.41)"
Module_HelpVersion SETS "5.35 (26 Jun 2001) 4.79.2.41"
Module_FullVersion SETS "5.35 (4.79.2.42)"
Module_HelpVersion SETS "5.35 (27 Jun 2001) 4.79.2.42"
END
VersionNum
View file @ f39e1298
......@@ -4,19 +4,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.41
#define Module_Date_CMHG 26 Jun 2001
#define Module_MinorVersion_CMHG 4.79.2.42
#define Module_Date_CMHG 27 Jun 2001
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.41"
#define Module_Date "26 Jun 2001"
#define Module_MinorVersion "4.79.2.42"
#define Module_Date "27 Jun 2001"
#define Module_ApplicationDate2 "26-Jun-01"
#define Module_ApplicationDate4 "26-Jun-2001"
#define Module_ApplicationDate2 "27-Jun-01"
#define Module_ApplicationDate4 "27-Jun-2001"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.41)"
#define Module_HelpVersion "5.35 (26 Jun 2001) (4.79.2.41)"
#define Module_FullVersion "5.35 (4.79.2.42)"
#define Module_HelpVersion "5.35 (27 Jun 2001) (4.79.2.42)"
hdr/ARMops
View file @ f39e1298
......@@ -26,6 +26,7 @@ ARM610 # 1
ARM700 # 1
ARM710 # 1
ARM710a # 1
SA110_preRevT # 1
SA110 # 1
ARM7500 # 1
ARM7500FE # 1
......@@ -43,6 +44,7 @@ CPUFlag_No26bitMode * 1:SHL:8
CPUFlag_VectorReadException * 1:SHL:9
CPUFlag_SplitCache * 1:SHL:10
CPUFlag_NoWBDrain * 1:SHL:11
CPUFlag_AbortRestartBroken * 1:SHL:12
; The macro to do an ARM operation. All ARM operations are expected
; to corrupt a1 only
......
hdr/KernelWS
View file @ f39e1298
......@@ -1163,26 +1163,29 @@ HAL_Descriptor # 4
HAL_Workspace # 4
HAL_WsSize # 4
ICache_Info # 0
ICache_NSets # 4
ICache_Size # 4
ICache_LineLen # 1
ICache_Associativity # 1
Cache_Type # 1
Cache_Flags # 1
DCache_Info # 0
DCache_NSets # 4
DCache_Size # 4
DCache_LineLen # 1
DCache_Associativity # 1
# 2
DCache_IndexBit # 4
DCache_IndexSegStart # 4
DCache_RangeThreshold # 4
ProcessorArch # 1
ICache_Info # 0
ICache_NSets # 4
ICache_Size # 4
ICache_LineLen # 1
ICache_Associativity # 1
Cache_Type # 1
Cache_Flags # 1
DCache_Info # 0
DCache_NSets # 4
DCache_Size # 4
DCache_LineLen # 1
DCache_Associativity # 1
# 2
DCache_CleanBaseAddress # 0 ; word used either for IndexBit or CleanBaseAddress
DCache_IndexBit # 4
DCache_CleanNextAddress # 0 ; word used either for IndexSegStart or CleanNextAddress
DCache_IndexSegStart # 4
DCache_RangeThreshold # 4
ProcessorArch # 1
AlignSpace
......
s/AMBControl/main
View file @ f39e1298
......@@ -95,6 +95,8 @@ AMBControl_Init
TST R0,#CPUFlag_BaseRestored
MOVEQ R1,#AMBFlag_LazyMapIn_disable ;laziness not supported if we can't trivially restart after abort (because we're lazy!)
MOVNE R1,#0 ;yipee, laziness enabled (and not suspended)
TST R0,#CPUFlag_AbortRestartBroken ;but wait! can't use for bugged chips (eg. pre rev T StrongARM)
MOVNE R1,#AMBFlag_LazyMapIn_disable
STR R1,AMBFlags
]
MOV R0,#AMBControl_ws
......
s/ARMops
View file @ f39e1298
......@@ -67,7 +67,7 @@ ARM_Analyse
ARM_read_cachetype v2
MOV v6, #ZeroPage
ADR v7, KnownCPUTable
ADRL v7, KnownCPUTable
FindARMloop
LDMIA v7!, {a1, a2} ; See if it's a known ARM
CMP a1, #-1
......@@ -164,6 +164,9 @@ FindARMloop
TEQ a2, #CT_ctype_WB_CR7_LDa
BEQ Analyse_WB_CR7_LDa ; eg. ARM9
TEQ a2, #CT_ctype_WB_Crd
BEQ Analyse_WB_Crd ; eg. StrongARM
; others ...
WeirdARMPanic
......@@ -308,11 +311,70 @@ Analyse_WB_CR7_LDa_L1
MUL a4, a2, a4
STR a4, [a1, #DCache_IndexSegStart]
MOV a2, #32*1024 ; arbitrary-ish
STR a1, [a1, #DCache_RangeThreshold]
MOV a2, #64*1024 ; arbitrary-ish
STR a2, [a1, #DCache_RangeThreshold]
B %FT90
Analyse_WB_Crd
TST v5, #CPUFlag_SplitCache
BEQ WeirdARMPanic ; currently, only support harvard
ADRL a1, Cache_CleanInvalidateAll_WB_Crd
STR a1, [v6, #Proc_Cache_CleanInvalidateAll]
ADRL a1, Cache_CleanAll_WB_Crd
STR a1, [v6, #Proc_Cache_CleanAll]
ADRL a1, Cache_InvalidateAll_WB_Crd
STR a1, [v6, #Proc_Cache_InvalidateAll]
ADRL a1, Cache_RangeThreshold_WB_Crd
STR a1, [v6, #Proc_Cache_RangeThreshold]
ADRL a1, TLB_InvalidateAll_WB_Crd
STR a1, [v6, #Proc_TLB_InvalidateAll]
ADRL a1, TLB_InvalidateEntry_WB_Crd
STR a1, [v6, #Proc_TLB_InvalidateEntry]
ADRL a1, WriteBuffer_Drain_WB_Crd
STR a1, [v6, #Proc_WriteBuffer_Drain]
ADRL a1, IMB_Full_WB_Crd
STR a1, [v6, #Proc_IMB_Full]
ADRL a1, IMB_Range_WB_Crd
STR a1, [v6, #Proc_IMB_Range]
ADRL a1, MMU_Changing_WB_Crd
STR a1, [v6, #Proc_MMU_Changing]
ADRL a1, MMU_ChangingEntry_WB_Crd
STR a1, [v6, #Proc_MMU_ChangingEntry]
ADRL a1, MMU_ChangingUncached_WB_Crd
STR a1, [v6, #Proc_MMU_ChangingUncached]
ADRL a1, MMU_ChangingUncachedEntry_WB_Crd
STR a1, [v6, #Proc_MMU_ChangingUncachedEntry]
ADRL a1, MMU_ChangingEntries_WB_Crd
STR a1, [v6, #Proc_MMU_ChangingEntries]
ADRL a1, MMU_ChangingUncachedEntries_WB_Crd
STR a1, [v6, #Proc_MMU_ChangingUncachedEntries]
MOV a1, #0
LDR a2, =DCacheCleanAddress
STR a2, [a1, #DCache_CleanBaseAddress]
STR a2, [a1, #DCache_CleanNextAddress]
MOV a2, #64*1024 ;arbitrary-ish threshold
STR a2, [a1, #DCache_RangeThreshold]
B %FT90
90
Pull "v1,v2,v5,v6,v7,pc"
......@@ -392,45 +454,47 @@ $var SETA $var+(CT_M_$sz:SHL:CT_M_pos)
KnownCPUTable
; /------Cache Type register fields-----\
; ID reg Mask Arch Type S Dsz Das Dln Isz Ias Iln
CPUDesc ARM600, &000600, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARM610, &000610, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARMunk, &000000, &00F000, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARM700, &007000, &FFFFF0, ARMv3, WT, 0, 8K, 4, 8
CPUDesc ARM710, &007100, &FFFFF0, ARMv3, WT, 0, 8K, 4, 8
CPUDesc ARM710a, &047100, &FDFFF0, ARMv3, WT, 0, 8K, 4, 4
CPUDesc ARM7500, &067100, &FFFFF0, ARMv3, WT, 0, 4K, 4, 4
CPUDesc ARM7500FE,&077100, &FFFFF0, ARMv3, WT, 0, 4K, 4, 4
CPUDesc ARMunk, &007000, &80F000, ARMv3, WT, 0, 8K, 4, 4
CPUDesc ARM720T, &807200, &FFFFF0, ARMv4T, WT, 0, 8K, 4, 4
CPUDesc ARMunk, &807000, &80F000, ARMv4T, WT, 0, 8K, 4, 4
CPUDesc SA110, &01A100, &0FFFF0, ARMv4, WB_Crd, 1, 16K, 32, 8, 16K, 32, 8
CPUDesc SA1100, &01A110, &0FFFF0, ARMv4, WB_Crd, 1, 8K, 32, 8, 16K, 32, 8
CPUDesc SA1110, &01B110, &0FFFF0, ARMv4, WB_Crd, 1, 8K, 32, 8, 16K, 32, 8
CPUDesc ARM920T, &029200, &0FFFF0, ARMv4T, WB_CR7_LDa, 1, 16K, 64, 8, 16K, 64, 8
CPUDesc ARM922T, &029220, &0FFFF0, ARMv4T, WB_CR7_LDa, 1, 8K, 64, 8, 8K, 64, 8
CPUDesc X80200, &052000, &0FFFF0, ARMv5TE, WB_Cal_LD, 1, 32K, 32, 8, 32K, 32, 8
; /------Cache Type register fields-----\
; ID reg Mask Arch Type S Dsz Das Dln Isz Ias Iln
CPUDesc ARM600, &000600, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARM610, &000610, &00FFF0, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARMunk, &000000, &00F000, ARMv3, WT, 0, 4K, 64, 4
CPUDesc ARM700, &007000, &FFFFF0, ARMv3, WT, 0, 8K, 4, 8
CPUDesc ARM710, &007100, &FFFFF0, ARMv3, WT, 0, 8K, 4, 8
CPUDesc ARM710a, &047100, &FDFFF0, ARMv3, WT, 0, 8K, 4, 4
CPUDesc ARM7500, &067100, &FFFFF0, ARMv3, WT, 0, 4K, 4, 4
CPUDesc ARM7500FE, &077100, &FFFFF0, ARMv3, WT, 0, 4K, 4, 4
CPUDesc ARMunk, &007000, &80F000, ARMv3, WT, 0, 8K, 4, 4
CPUDesc ARM720T, &807200, &FFFFF0, ARMv4T, WT, 0, 8K, 4, 4
CPUDesc ARMunk, &807000, &80F000, ARMv4T, WT, 0, 8K, 4, 4
CPUDesc SA110_preRevT, &01A100, &0FFFFC, ARMv4, WB_Crd, 1, 16K, 32, 8, 16K, 32, 8
CPUDesc SA110, &01A100, &0FFFF0, ARMv4, WB_Crd, 1, 16K, 32, 8, 16K, 32, 8
CPUDesc SA1100, &01A110, &0FFFF0, ARMv4, WB_Crd, 1, 8K, 32, 8, 16K, 32, 8
CPUDesc SA1110, &01B110, &0FFFF0, ARMv4, WB_Crd, 1, 8K, 32, 8, 16K, 32, 8
CPUDesc ARM920T, &029200, &0FFFF0, ARMv4T, WB_CR7_LDa, 1, 16K, 64, 8, 16K, 64, 8
CPUDesc ARM922T, &029220, &0FFFF0, ARMv4T, WB_CR7_LDa, 1, 8K, 64, 8, 8K, 64, 8
CPUDesc X80200, &052000, &0FFFF0, ARMv5TE, WB_Cal_LD, 1, 32K, 32, 8, 32K, 32, 8
DCD -1
; Peculiar characteristics of individual ARMs not deducable otherwise. First field is
; flags to set, second flags to clear.
KnownCPUFlags
DCD 0, 0 ; ARM 600
DCD 0, 0 ; ARM 610
DCD 0, 0 ; ARM 700
DCD 0, 0 ; ARM 710
DCD 0, 0 ; ARM 710a
DCD 0, 0 ; SA 110
DCD 0, 0 ; ARM 7500
DCD 0, 0 ; ARM 7500FE
DCD 0, 0 ; SA 1100
DCD 0, 0 ; SA 1110
DCD CPUFlag_NoWBDrain, 0 ; ARM 720T
DCD 0, 0 ; ARM 920T
DCD 0, 0 ; ARM 922T
DCD 0, 0 ; X80200
DCD 0, 0 ; ARM 600
DCD 0, 0 ; ARM 610
DCD 0, 0 ; ARM 700
DCD 0, 0 ; ARM 710
DCD 0, 0 ; ARM 710a
DCD CPUFlag_AbortRestartBroken, 0 ; SA 110 pre revT
DCD 0, 0 ; SA 110 revT or later
DCD 0, 0 ; ARM 7500
DCD 0, 0 ; ARM 7500FE
DCD 0, 0 ; SA 1100
DCD 0, 0 ; SA 1110
DCD CPUFlag_NoWBDrain, 0 ; ARM 720T
DCD 0, 0 ; ARM 920T
DCD 0, 0 ; ARM 922T
DCD 0, 0 ; X80200
; --------------------------------------------------------------------------
; ----- ARMops -------------------------------------------------------------
......@@ -640,8 +704,6 @@ Cache_RangeThreshold_Writethrough
; ----- ARMops for ARM9 and the like ---------------------------------------
; --------------------------------------------------------------------------
; Support for ARM9 or similar
;
; WB_CR7_LDa refers to ARMs with writeback data cache, cleaned with
; register 7, lockdown available (format A)
;
......@@ -855,6 +917,215 @@ MMU_ChangingUncachedEntries_WB_CR7_LDa ROUT
MOV pc, lr
; --------------------------------------------------------------------------
; ----- ARMops for StrongARM and the like ----------------------------------
; --------------------------------------------------------------------------
; WB_Crd is Writeback data cache, clean by reading data from cleaner area
; Currently no support for mini data cache on some StrongARM variants. Mini
; cache is always writeback and must have cleaning support, so is very
; awkward to use for cacheable screen, say.
; Global cache cleaning requires address space for private cleaner areas (not accessed
; for any other reason). Cleaning is normally with interrupts enabled (to avoid a latency
; hit), which means that the cleaner data is not invalidated afterwards. This is fine for
; RISC OS - where the private area is not used for anything else, and any re-use of the
; cache under interrupts is safe (eg. a page being moved is *never* involved in any
; active interrupts).
; Mostly, cleaning toggles between two separate cache-sized areas, which gives minimum
; cleaning cost while guaranteeing proper clean even if previous clean data is present. If
; the clean routine is re-entered, an independent, double sized clean is initiated. This
; guarantees proper cleaning (regardless of multiple re-entrancy) whilst hardly complicating
; the routine at all. The overhead is small, since by far the most common cleaning will be
; non-re-entered. The upshot is that the cleaner address space available must be at least 4
; times the cache size:
; 1 : used alternately, on 1st, 3rd, ... non-re-entered cleans
; 2 : used alternately, on 2nd, 4th, ... non-re-entered cleans
; 3 : used only for first half of a re-entered clean
; 4 : used only for second half of a re-entered clean
;
; DCache_CleanBaseAddress : start address of total cleaner space
; DCache_CleanNextAddress : start address for next non-re-entered clean, or 0 if re-entered
Cache_CleanAll_WB_Crd ROUT
;
; - cleans data cache (and invalidates it as a side effect)
; - can be used with interrupts enabled (to avoid latency over time of clean)
; - can be re-entered
; - see remarks at top of StrongARM ops for discussion of strategy
;
Push "a2-a4, v1, v2, lr"
MOV lr, #0
LDR a1, [lr, #DCache_CleanBaseAddress]
LDR a2, =DCache_CleanNextAddress
LDR a3, [lr, #DCache_Size]
LDRB a4, [lr, #DCache_LineLen]
MOV v2, #0
SWP v1, v2, [a2] ; read current CleanNextAddr, zero it (semaphore)
TEQ v1, #0 ; but if it is already zero, we have re-entered
ADDEQ v1, a1, a3, LSL #1 ; if re-entered, start clean at Base+2*Cache_Size
ADDEQ v2, v1, a3, LSL #1 ; if re-entered, do a clean of 2*Cache_Size
ADDNE v2, v1, a3 ; if not re-entered, do a clean of Cache_Size
10
LDR lr, [v1], a4
TEQ v1, v2
BNE %BT10
ADD v2, a1, a3, LSL #1 ; compare end address with Base+2*Cache_Size
CMP v1, v2
MOVEQ v1, a1 ; if equal, not re-entered and Next wraps back
STRLS v1, [a2] ; if lower or same, not re-entered, so update Next
MCR p15, 0, a1, c7, c10, 4 ; drain WBuffer
Pull "a2-a4, v1, v2, pc"
Cache_CleanInvalidateAll_WB_Crd ROUT
IMB_Full_WB_Crd
;
;does not truly invalidate DCache, but effectively invalidates (flushes) all lines not
;involved in interrupts - this is sufficient for OS requirements, and means we don't
;have to disable interrupts for possibly slow clean
;
Push "lr"
BL Cache_CleanAll_WB_Crd ;clean DCache (wrt to non-interrupt stuff)
MCR p15, 0, a1, c7, c5, 0 ;flush ICache
Pull "pc"
Cache_InvalidateAll_WB_Crd
;
; no clean, assume caller knows what is happening
;
MCR p15, 0, a1, c7, c7, 0 ;flush ICache and DCache
MCR p15, 0, a1, c7, c10, 4 ;drain WBuffer
MOV pc, lr
Cache_RangeThreshold_WB_Crd
MOV a1, #0
LDR a1, [a1, #DCache_RangeThreshold]
MOV pc, lr
TLB_InvalidateAll_WB_Crd
MMU_ChangingUncached_WB_Crd
MCR p15, 0, a1, c8, c7, 0 ;flush ITLB and DTLB
MOV pc, lr
TLB_InvalidateEntry_WB_Crd
MMU_ChangingUncachedEntry_WB_Crd
MCR p15, 0, a1, c8, c6, 1 ;flush DTLB entry
MCR p15, 0, a1, c8, c5, 0 ;flush ITLB
MOV pc, lr
WriteBuffer_Drain_WB_Crd
MCR p15, 0, a1, c7, c10, 4 ;drain WBuffer
MOV pc, lr
IMB_Range_WB_Crd ROUT
SUB a2, a2, a1
CMP a2, #64*1024 ;arbitrary-ish range threshold
ADD a2, a2, a1
BHS IMB_Full_WB_Crd
Push "lr"
MOV lr, #0
LDRB lr, [lr, #DCache_LineLen]
10
MCR p15, 0, a1, c7, c10, 1 ;clean DCache entry
ADD a1, a1, lr
CMP a1, a2
BLO %BT10
MCR p15, 0, a1, c7, c10, 4 ;drain WBuffer
MCR p15, 0, a1, c7, c5, 0 ;flush ICache
Pull "pc"
MMU_Changing_WB_Crd
Push "lr"
BL Cache_CleanAll_WB_Crd ;clean DCache (wrt to non-interrupt stuff)
MCR p15, 0, a1, c7, c5, 0 ;flush ICache
MCR p15, 0, a1, c8, c7, 0 ;flush ITLB and DTLB
Pull "pc"
MMU_ChangingEntry_WB_Crd ROUT
;
;there is no clean&invalidate DCache instruction, however we can do clean
;entry followed by invalidate entry without an interrupt hole, because they
;are for the same virtual address (and that virtual address will not be
;involved in interrupts, since it is involved in remapping)
;
Push "a2, lr"
ADD a2, a1, #PageSize
MOV lr, #0
LDRB lr, [lr, #DCache_LineLen]
10
MCR p15, 0, a1, c7, c10, 1 ;clean DCache entry
MCR p15, 0, a1, c7, c6, 1 ;flush DCache entry
ADD a1, a1, lr
CMP a1, a2
BLO %BT10
SUB a1, a1, #PageSize
MCR p15, 0, a1, c7, c10, 4 ;drain WBuffer
MCR p15, 0, a1, c7, c5, 0 ;flush ICache
MCR p15, 0, a1, c8, c6, 1 ;flush DTLB entry
MCR p15, 0, a1, c8, c5, 0 ;flush ITLB
Pull "a2, pc"
MMU_ChangingEntries_WB_Crd ROUT
;
;same comments as MMU_ChangingEntry_WB_Crd
;
Push "a2, a3, lr"
MOV a2, a2, LSL #Log2PageSize
MOV a3, #0
LDR a3, [a3, #DCache_RangeThreshold] ;check whether cheaper to do global clean
CMP a2, a3
BHS %FT30
ADD a2, a2, a1 ;clean end address (exclusive)
MOV a3, #0
LDRB a3, [a3, #DCache_LineLen]
MOV lr, a1
10
MCR p15, 0, a1, c7, c10, 1 ;clean DCache entry
MCR p15, 0, a1, c7, c6, 1 ;flush DCache entry
ADD a1, a1, a3
CMP a1, a2
BLO %BT10
MCR p15, 0, a1, c7, c10, 4 ;drain WBuffer
MCR p15, 0, a1, c7, c5, 0 ;flush ICache
MOV a1, lr ;restore start address
20
MCR p15, 0, a1, c8, c6, 1 ;flush DTLB entry
ADD a1, a1, #PageSize
CMP a1, a2
BLO %BT20
MCR p15, 0, a1, c8, c5, 0 ;flush ITLB
Pull "a2, a3, pc"
;
30
BL Cache_CleanAll_WB_Crd ;clean DCache (wrt to non-interrupt stuff)
MCR p15, 0, a1, c7, c5, 0 ;flush ICache
MCR p15, 0, a1, c8, c7, 0 ;flush ITLB and DTLB
Pull "a2, a3, pc"
MMU_ChangingUncachedEntries_WB_Crd ROUT
CMP a2, #32 ;arbitrary-ish threshold
BHS %FT20
Push "lr"
MOV lr, a2
10
MCR p15, 0, a1, c8, c6, 1 ;flush DTLB entry
ADD a1, a1, #PageSize
SUBS lr, lr, #1
BNE %BT10
MCR p15, 0, a1, c8, c5, 0 ;flush ITLB
Pull "pc"
;
20
MCR p15, 0, a1, c8, c7, 0 ;flush ITLB and DTLB
MOV pc, lr
; --------------------------------------------------------------------------
......@@ -882,7 +1153,8 @@ PNameTable
DCW PName_ARM700 - PNameTable
DCW PName_ARM710 - PNameTable
DCW PName_ARM710a - PNameTable
DCW PName_SA110 - PNameTable
DCW PName_SA110 - PNameTable ; pre rev T
DCW PName_SA110 - PNameTable ; rev T or later
DCW PName_ARM7500 - PNameTable
DCW PName_ARM7500FE - PNameTable
DCW PName_SA1100 - PNameTable
......
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