Assorted kernel fixes for ARMv6/ARMv7

Detail:
  s/ARMops - Fix IMB_Range_WB_CR7_Lx to clean the correct number of cache lines
  s/HAL - Change CP15 control register flags so unaligned loads are enabled on ARMv6 (to simplify support for ARMv7 where unaligned loads are always enabled, and to match the behaviour expected by the example code in Hdr:CPU.Arch)
  s/AMBControl/memmap - Make AMB_LazyFixUp use the correct L2PT protection flags depending on ARM600/VMSAv6 MMU model. Also guard against problems caused by future L2PT flag changes.
  s/vdu/vdugrafj - Fix previously undiscovered 32bit incompatability in GetSprite (OS_SpriteOp 14/16)
Admin:
  Tested on rev C2 beagleboard


Version 5.35, 4.79.2.98.2.5. Tagged as 'Kernel-5_35-4_79_2_98_2_5'

VersionASM

@@ -13,11 +13,11 @@
                         GBLS    Module_ComponentPath
 Module_MajorVersion     SETS    "5.35"
 Module_Version          SETA    535
-Module_MinorVersion     SETS    "4.79.2.98.2.4"
-Module_Date             SETS    "24 Apr 2009"
-Module_ApplicationDate  SETS    "24-Apr-09"
+Module_MinorVersion     SETS    "4.79.2.98.2.5"
+Module_Date             SETS    "10 May 2009"
+Module_ApplicationDate  SETS    "10-May-09"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.35 (4.79.2.98.2.4)"
-Module_HelpVersion      SETS    "5.35 (24 Apr 2009) 4.79.2.98.2.4"
+Module_FullVersion      SETS    "5.35 (4.79.2.98.2.5)"
+Module_HelpVersion      SETS    "5.35 (10 May 2009) 4.79.2.98.2.5"
                         END

VersionNum

@@ -5,19 +5,19 @@
  *
  */
 #define Module_MajorVersion_CMHG        5.35
-#define Module_MinorVersion_CMHG        4.79.2.98.2.4
-#define Module_Date_CMHG                24 Apr 2009
+#define Module_MinorVersion_CMHG        4.79.2.98.2.5
+#define Module_Date_CMHG                10 May 2009
 
 #define Module_MajorVersion             "5.35"
 #define Module_Version                  535
-#define Module_MinorVersion             "4.79.2.98.2.4"
-#define Module_Date                     "24 Apr 2009"
+#define Module_MinorVersion             "4.79.2.98.2.5"
+#define Module_Date                     "10 May 2009"
 
-#define Module_ApplicationDate          "24-Apr-09"
+#define Module_ApplicationDate          "10-May-09"
 
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.35 (4.79.2.98.2.4)"
-#define Module_HelpVersion              "5.35 (24 Apr 2009) 4.79.2.98.2.4"
+#define Module_FullVersion              "5.35 (4.79.2.98.2.5)"
+#define Module_HelpVersion              "5.35 (10 May 2009) 4.79.2.98.2.5"
 #define Module_LibraryVersionInfo       "5:35"

s/AMBControl/memmap

@@ -107,8 +107,15 @@ AMB_LazyFixUp ROUT
         ADD     r1,r1,#AMBNode_pages
         ADD     r1,r1,r0,LSL #2                          ;r1 -> page involved, in node page list
         LDR     r2,AMBPhysBin
+
+; Calculate the L2PT protection bits in a nice way that won't produce broken code if we change MMU model
+   [ MEMM_Type = "VMSAv6"
+        MOV     r3,#(AP_Full*L2X_APMult)+L2_ExtPage+L2_C+L2_B
+   |
+        ASSERT  (AP_Full*L2X_APMult)+L2_ExtPage+L2_C+L2_B = &FFE
         MOV     r3,#&FF0
-        ORR     r3,r3,#&E                                ;&FFE = L2PT protection bits for ordinary page
+        ORR     r3,r3,#&E
+   ]
         LDR     r4,[r1]
         MOV     r6,r4
         PageNumToL2PT r4,r2,r3,r5

s/ARMops

@@ -2055,7 +2055,8 @@ IMB_Full_WB_CR7_Lx ROUT
 IMB_Range_WB_CR7_Lx ROUT
         SUB     a2, a2, a1
         CMP     a2, #32*1024 ; Maximum L1 cache size on Cortex-A8 is 32K, use that to guess what approach to take
-        BGE     IMB_Full_WB_CR7_Lx
+        ADD     a2, a2, a1
+        BHS     IMB_Full_WB_CR7_Lx
         Push    "a3,lr"
         MOV     lr, #0
         LDRB    lr, [lr, #DCache_LineLen] ; log2(line len)-2

s/HAL

@@ -37,7 +37,7 @@ mmuc_table ; Table of MMUC init values. First word is value to ORR, second is va
  DCD MMUC_F+MMUC_L+MMUC_D+MMUC_P, MMUC_B+MMUC_W+MMUC_C+MMUC_A+MMUC_M+MMUC_RR+MMUC_V+MMUC_I+MMUC_Z+MMUC_R+MMUC_S ; ARMv5T
  DCD MMUC_F+MMUC_L+MMUC_D+MMUC_P, MMUC_B+MMUC_W+MMUC_C+MMUC_A+MMUC_M+MMUC_RR+MMUC_V+MMUC_I+MMUC_Z+MMUC_R+MMUC_S ; ARMv5TE
  DCD MMUC_F+MMUC_L+MMUC_D+MMUC_P, MMUC_B+MMUC_W+MMUC_C+MMUC_A+MMUC_M+MMUC_RR+MMUC_V+MMUC_I+MMUC_Z+MMUC_R+MMUC_S ; ARMv5TEJ
- DCD MMUC_F+MMUC_L+MMUC_D+MMUC_P, MMUC_B+MMUC_W+MMUC_C+MMUC_A+MMUC_M+MMUC_RR+MMUC_V+MMUC_I+MMUC_Z+MMUC_R+MMUC_S+MMUC_VE+MMUC_EE+MMUC_L2 ; ARMv6
+ DCD MMUC_F+MMUC_L+MMUC_D+MMUC_P+MMUC_U, MMUC_B+MMUC_W+MMUC_C+MMUC_A+MMUC_M+MMUC_RR+MMUC_V+MMUC_I+MMUC_Z+MMUC_R+MMUC_S+MMUC_VE+MMUC_EE+MMUC_L2 ; ARMv6
  ; Skip undefined architecture numbers
 mmuc_table_armvf
  DCD 0, MMUC_C+MMUC_A+MMUC_M+MMUC_V+MMUC_I+MMUC_Z+MMUC_RR+MMUC_TRE+MMUC_AFE+MMUC_TE ; ARMvF (Cortex)

s/vdu/vdugrafj

@@ -159,7 +159,11 @@ GetSpr05
       ]
         BEQ     %BT75                   ; then error
 
-        ADR     R14, %FT95 + SVC_mode
+ [ No26bitCode
+        ADR     R14, %FT95
+ |
+        ADR     R14, %FT95+SVC_mode ; Enable interrupts on return from PostCreateHeader
+ ]
         Push    "R1, R14"
         ADD     R8, WsPtr, #NameBuf
         LDMIA   R8, {R9-R11}            ; load 3 words of name
@@ -204,6 +208,10 @@ GetSpr05
 ; R1 -> sprite area, R2 -> sprite, R3 = no. of words to extend by
 
 95
+ [ No26bitCode
+; Enable interrupts here for 32bit machines
+        WritePSRc SVC_mode, R14
+ ]
         BL      GetSpriteData
         BL      SelectSprite