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Commit c9cdb689 authored by Mike Stephens's avatar Mike Stephens
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spectacular new OS_Memory reason codes 13 map permanent I/O space, return... 

spectacular new OS_Memory reason codes 13 map permanent I/O space, return logical address 14 access temporary physical mapping 15 release temporary physical mapping

DA creation and I/O space creation now avoid collision if address
space fills

Version 5.35, 4.79.2.28. Tagged as 'Kernel-5_35-4_79_2_28'
parent 45c8debd
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Showing with 217 additions and 77 deletions
VersionASM
View file @ c9cdb689
......@@ -13,12 +13,12 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.27"
Module_Date SETS "20 Apr 2001"
Module_ApplicationDate2 SETS "20-Apr-01"
Module_ApplicationDate4 SETS "20-Apr-2001"
Module_MinorVersion SETS "4.79.2.28"
Module_Date SETS "01 May 2001"
Module_ApplicationDate2 SETS "01-May-01"
Module_ApplicationDate4 SETS "01-May-2001"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.27)"
Module_HelpVersion SETS "5.35 (20 Apr 2001) 4.79.2.27"
Module_FullVersion SETS "5.35 (4.79.2.28)"
Module_HelpVersion SETS "5.35 (01 May 2001) 4.79.2.28"
END
VersionNum
View file @ c9cdb689
......@@ -4,19 +4,19 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.27
#define Module_Date_CMHG 20 Apr 2001
#define Module_MinorVersion_CMHG 4.79.2.28
#define Module_Date_CMHG 01 May 2001
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.27"
#define Module_Date "20 Apr 2001"
#define Module_MinorVersion "4.79.2.28"
#define Module_Date "01 May 2001"
#define Module_ApplicationDate2 "20-Apr-01"
#define Module_ApplicationDate4 "20-Apr-2001"
#define Module_ApplicationDate2 "01-May-01"
#define Module_ApplicationDate4 "01-May-2001"
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.27)"
#define Module_HelpVersion "5.35 (20 Apr 2001) (4.79.2.27)"
#define Module_FullVersion "5.35 (4.79.2.28)"
#define Module_HelpVersion "5.35 (01 May 2001) (4.79.2.28)"
hdr/KernelWS
View file @ c9cdb689
......@@ -248,6 +248,7 @@ ScreenMaxSize * 480*1024
RMAMaxSize * &00F00000 ; temporary - should be max
IOLimit * &BA000000 ; initial lower limit on room for IO space (DA creation may move limit up)
IO * &FA000000 ; works downwards
HALWorkspace * &FA000000
IRQStackAddress * &FA100000
......@@ -1234,8 +1235,8 @@ Export_DebuggerSpace # 16*8 ; Debugger module needs some zero page
; NVRAM support
NVRamSize # 1 ; Size of NVRam (E2ROM & CMOS) fitted in 256byte units
RTCFitted # 1 ; flag =1 iff RTC is fitted
NVRamSize # 1 ; Size of NVRam (E2ROM & CMOS) fitted in 256byte units
RTCFitted # 1 ; flag =1 iff RTC is fitted
NVRamBase # 1 ; Base of NVRam
NVRamSpeed # 1 ; Clock hold time in 0.5s units
NVRamPageSize # 1 ; Page size for writing (log2)
......@@ -1262,6 +1263,9 @@ EnvString # 256
CamMapCorruptDebugBlock # &40 ; somewhere to dump registers in case of emergency
IOAllocPtr # 4 ; current lowpoint of mapped I/O space (also upper limit on DAs)
IOAllocLimit # 4 ; current lowest allowed I/O space (DA creation may move this up)
[ :DEF: ShowWS
! 0, "Free space after CamMap debug block = ":CC::STR:((JordanWS+256*4)-@)
]
......@@ -1279,7 +1283,7 @@ MaxCamEntry # 4 ; maximum index into the cam map, ie
RAMLIMIT # 4
IOAllocPtr # 4
# 4 ; spare
HiServ_ws # 4
HiServ # 4
......
s/ChangeDyn
View file @ c9cdb689
......@@ -758,6 +758,14 @@ DynArea_ErrorTranslateAndExit
MOV r7, #0 ; initial size is zero
STR r7, [r2, #DANode_Size] ; before we grow it
[ HAL
; update lower limit on IO space growth, if this DA exceeds previous limit
LDR r6, [r7, #IOAllocLimit]
ADD lr, r3, r5
CMP lr, r6
STRHI lr, [r7, #IOAllocLimit]
]
; now make copy of string - first find out length of string
MOV r7, r8
......@@ -1121,7 +1129,14 @@ CheckForOverlappingAreas Entry "r0-r5"
ADDS r5, r5, r3 ; r5 -> end +1
BHI %FT20 ; if CS, indicating wrap, and not EQ (ie just ending at 0), then bad
; First, check against list of fixed areas
[ HAL
MOV lr, #0
LDR r0, [lr, #IOAllocPtr]
CMP r5, r0 ; end must be below I/O space (allocated down from high memory)
BHI %FT20
]
; check against list of fixed areas
ADR lr, FixedAreasTable
10
......@@ -1172,7 +1187,6 @@ CheckForOverlappingAreas Entry "r0-r5"
FixedAreasTable ; table of fixed areas (address, size)
[ HAL
! 0, "Sort out FixedAreasTable"
& 0, AplWorkMaxSize ; application space
& CursorChunkAddress, 64*1024 ; 32K for cursor, 32K for "nowhere"
[ OSROM_ImageSize > 8192
......@@ -1180,7 +1194,7 @@ FixedAreasTable ; table of fixed areas (
|
& &03000000, 16*1024*1024 ; I/O + ROM
]
& IO, &FFFFFFFF-IO ; Kernel workspace (fix - what about dynamic allocs)
& IO, &FFFFFFFF-IO ; Kernel workspace (code will also check dynamic value IOAllocPtr)
|
& 0, AplWorkMaxSize ; application space
& UndStackSoftCamChunk, 1024*1024 ; undefined stack / soft cam map
......@@ -1232,11 +1246,18 @@ AllocateAreaAddress Entry "r0-r2,r4-r7"
10
ADDS r7, r3, r5 ; r7 is our end+1
BHI %FT90 ; if we wrapped (but not end+1=0) then we failed
[ HAL
MOV lr, #0
LDR r2, [lr, #IOAllocPtr]
CMP r7, r2
BHI %FT90 ; if we walked into IOspace (assumed higher than any DA space) then we failed
]
15
BL GetNextRange ; get next range from either list (r2=start, r6=end+1)
CMP r7, r2 ; if end(ours) <= start(next) then this is OK
BLS %FT80 ; (note this also works when r2=-1)
CMP r3, r6 ; else if start(ours) >= end(next)
BCS %BT10 ; then get another
BCS %BT15 ; then get another
MOV r3, r6 ; else make start(ours) := end(next)
B %BT10 ; and go back for another try
......
s/HAL
View file @ c9cdb689
......@@ -623,8 +623,10 @@ MMUon_nol1ptoverlap
LDR a3, [a2, #HAL_WsSize]
BL memset
LDR a1, =IO
MOV a2, #ZeroPage
LDR a1, =IOLimit
STR a1, [a2, #IOAllocLimit]
LDR a1, =IO
STR a1, [a2, #IOAllocPtr]
BL SetUpHALEntryTable
......@@ -1423,61 +1425,93 @@ InitProcVec_FIQ
DCD 0
InitProcVecsEnd
; In: a1 = flags
; a2 = physical address
; a3 = size
RISCOS_MapInIO
;
; In: a1 = flags (only L1_B currently allowed)
; a2 = physical address
; a3 = size
; Out: a1 = assigned logical address, or 0 if failed (no room)
;
; Will detect and return I/O space already mapped appropriately, or map and return new space
; For simplicity and speed of search, works on a section (1Mb) granularity
;
RISCOS_MapInIO ROUT
Entry "v1-v4"
MOV v4, a2 ; v4 = original requested address
ADD a3, a2, a3 ; a3 -> end
MOV a2, a2, LSR #12
MOV a2, a2, LSL #12 ; round a2 down to a page boundary
SUB v4, v4, a2 ; v4 = offset of original within page-aligned area
MOV lr, a3, LSR #12
TEQ a3, lr, LSL #12
ADD a3, a2, a3 ; a3 -> end (exclusive)
MOV a2, a2, LSR #20
MOV a2, a2, LSL #20 ; round a2 down to a section boundary
SUB v4, v4, a2 ; v4 = offset of original within section-aligned area
MOV lr, a3, LSR #20
TEQ a3, lr, LSL #20
ADDNE lr, lr, #1
MOV a3, lr, LSL #12 ; round a3 up to a page boundary
SUB a4, a3, a2 ; a4 = area size
AND a3, a1, #L2_C
ORR a3, a3, #AP_None * L2_APMult ; a3 = access permissions
MOV a1, a2 ; a1 = physical base
Push "a1,a3,a4"
BL FindIOLogicalAddress
MOV a2, a1 ; a2 = logical address of page-aligned area
ADD v4, a1, v4 ; v4 = logical address of requested physical address
Pull "a1,a3,a4"
MOV ip, #ZeroPage
LDR v1, [ip, #InitUsedBlock]
LDR v2, [ip, #InitUsedEnd]
MOV v3, #0
BL Init_MapIn
MOV a1, v4
MOV ip, #ZeroPage
STR v1, [ip, #InitUsedBlock]
STR v2, [ip, #InitUsedEnd]
EXIT
MOV a3, lr, LSL #20 ; round a3 up to a section boundary
; In: a1 = Physical address
; a3 = flags
; a4 = size
; Out: a1 = Logical address
FindIOLogicalAddress
MOV a2, a4, LSR #12
TEQ a4, a2, LSL #12
ADDNE a2, a2, #1
MOV a4, a2, LSL #12 ; a4 = size rounded up
ORR a2, a1, a4
MOVS ip, a2, LSL #12 ; EQ if megabyte aligned
LDR ip, =ZeroPage
LDR a4, =L1PT
AND a1, a1, #L1_B ; only allow bufferable as flags option
LDR v2, =IO ; logical end (exclusive) of currently mapped IO
LDR v1, [ip, #IOAllocPtr] ; logical start (inclusive)
SUB v1, v1, #&100000
10
ADD v1, v1, #&100000 ; next mapped IO section
CMP v1, v2
BHS %FT32 ; no more currently mapped IO
LDR v3, [a4, v1, LSR #(20-2)] ; L1PT entry (must be for mapped IO)
MOV lr, v3, LSR #20 ; physical address bits
CMP lr, a2, LSR #20
BNE %BT10 ; no address match
AND lr, v3, #L1_B
TEQ lr, a1
BNE %BT10 ; no flags match
;
; alright, found start of requested IO already mapped, and with required L1_B
;
Push "a2, v1"
20
ADD a2, a2, #&100000
CMP a2, a3
Pull "a2, v1", HS
BHS %FT40 ; its all there already!
ADD v1, v1, #&100000 ; next mapped IO section
CMP v1, v2
BHS %FT30 ; not all there in this mapping
LDR v3, [a4, v1, LSR #(20-2)] ; L1PT entry
MOV lr, v3, LSR #20 ; physical address bits
CMP lr, a2, LSR #20
BNE %FT30 ; address match failed
AND lr, v3, #L1_B
TEQ lr, a1
BEQ %BT20 ; address and flags match so far
30
Pull "a2, v1"
;
; request not currently mapped, only partially mapped, or mapped with wrong L1_B
;
32
MOV ip, #ZeroPage
LDR a3, [ip, #IOAllocPtr]
MOVEQ a3, a3, LSR #20
MOVEQ a3, a3, LSL #20
SUB a1, a3, a4
STR a1, [ip, #IOAllocPtr]
MOV pc, lr
LDR v2, [ip, #IOAllocPtr]
ADD v1, v2, a2
SUB v1, v1, a3 ; attempt to allocate size of a3-a2
LDR v3, [ip, #IOAllocLimit] ; can't extend down below limit
CMP v1, v3
MOVLS a1, #0
BLS %FT90
STR v1, [ip, #IOAllocPtr]
ORR a2, a2, a1
ORR a2, a2, #AP_None * L1_APMult
ORR a2, a2, #L1_Section ; first L1PT value
34
STR a2, [a4, v1, LSR #(20-2)]
ADD a2, a2, #&100000
ADD v1, v1, #&100000 ; next section
CMP a2, a3
BLO %BT34
LDR v1, [ip, #IOAllocPtr]
40
ADD a1, v1, v4 ; logical address for request
90
EXIT
SetUpHALEntryTable ROUT
......
s/MemInfo
View file @ c9cdb689
......@@ -50,19 +50,22 @@ MemReturn
ExitSWIHandler
30
B MemoryConvert
B MemoryConvert ; 0
B %BT20 ; Reason codes 1-5 are reserved.
B %BT20
B %BT20
B %BT20
B %BT20
B MemoryPhysSize
B MemoryReadPhys
B MemoryAmounts
B MemoryIOSpace
B MemoryPhysSize ; 6
B MemoryReadPhys ; 7
B MemoryAmounts ; 8
B MemoryIOSpace ; 9
B %BT20 ; Reason code 10 reserved (for MemoryFreePoolLock).
B %BT20 ; Reason code 11 reserved (for PCImapping).
B RecommendPage
B RecommendPage ; 12
B MapIOpermanent ; 13
B AccessPhysAddr ; 14
B ReleasePhysAddr ; 15
40
......@@ -772,4 +775,82 @@ RP_error
DCB "No chunk available (OS_Memory 12)",0
ALIGN
;----------------------------------------------------------------------------------------
;MapIOpermanent - map IO space (if not already mapped) and return logical address
;
; In: r0 bits 0..7 = 13 (reason code 13)
; r0 bit 8 = 1 to map bufferable space (0 is normal, non-bufferable)
; r0 bits 9..31 = 0 (reserved flags)
; r1 = physical address of base of IO space required
; r2 = size of IO space required (bytes)
;
; Out: r3 = logical address of base of IO space
; - or error if not possible (no room)
;
MapIOpermanent ROUT
Push "r0-r2,r12,lr"
TST r0, #&100 ;test bufferable bit
MOVNE r0, #L1_B
MOVEQ r0, #0
BL RISCOS_MapInIO
MOV r3, r0
CMP r3, #0 ;MOV,CMP rather than MOVS to be sure to clear V
Pull "r0-r2,r12,pc",NE
ADR r0, MIp_error
SETV
STR r0, [sp]
Pull "r0-r2,r12,pc"
MIp_error
DCD 0
DCB "No room for IO space (OS_Memory 13)",0
ALIGN
;----------------------------------------------------------------------------------------
;AccessPhysAddr - claim temporary access to given physical address (in fact,
; controls access to the 1Mb aligned space containing the address)
; The access remains until the next AccessPhysAddr or until a
; ReleasePhysAddr (although interrupts or subroutines may temporarily
; make their own claims, but restore on Release before returning)
;
; In: r0 bits 0..7 = 14 (reason code 14)
; r0 bit 8 = 1 to map bufferable space, 0 for unbufferable
; r0 bits 9..31 = 0 (reserved flags)
; r1 = physical address
;
; Out: r2 = logical address corresponding to phys address r1
; r3 = old state (for ReleasePhysAddr)
;
; Use of multiple accesses: it is fine to make several Access calls, and
; clean up with a single Release at the end. In this case, it is the old state
; (r3) of the *first* Access call that should be passed to Release in order to
; restore the state before any of your accesses. (The r3 values of the other
; access calls can be ignored.)
;
AccessPhysAddr ROUT
Push "r0,r1,r12,lr"
TST r0, #&100 ;test bufferable bit
MOVNE r0, #L1_B
MOVEQ r0, #0
SUB sp, sp, #4 ; word for old state
MOV r2, sp ; pointer to word
BL RISCOS_AccessPhysicalAddress
MOV r2, r0
Pull r3 ; old state
Pull "r0,r1,r12,pc"
;----------------------------------------------------------------------------------------
;ReleasePhysAddr - release temporary access that was claimed by AccessPhysAddr
;
; In: r0 bits 0..7 = 15 (reason code 15)
; r0 bits 8..31 = 0 (reserved flags)
; r1 = old state to restore
;
ReleasePhysAddr
Push "r0-r3,r12,lr"
MOV r0, r1
BL RISCOS_ReleasePhysicalAddress
Pull "r0-r3,r12,pc"
END
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