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Commit c3d9625b authored by Neil Turton's avatar Neil Turton
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Import from SrcFiler

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TestSrc/Begin
View file @ c3d9625b
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TestSrc/ExtIO
View file @ c3d9625b
......@@ -23,28 +23,29 @@
; 15-May-90 ArtG Added ReadyByte : improves synchronization
; when ExtCmd execution toggles A21/A22.
; 18-Jun-90 ArtG Added CPR15 read/write functions
;
;
; 04-Oct-96 JRH Updated comments to refer to test box on A23.
; Added support for speaking to the test box when
; running from the 2nd ROM bank, conditioned on
; CanLiveOnROMCard. Needed because 2nd ROM bank
; isn't ghosted on the A23 line like the 1st bank.
;------------------------------------------------------------------------
SUBT Test adapter interface
;
; The test adapter senses an access to the ROM with address line A21 high.
; Current (2M addressing space) ROMs only use address lines A2 to A20,
; so if A21 to A22 are asserted they will be ignored (the ROMS are aliased
; into 8M of space). With no test adapter, the aliased ROM location will
; The test adapter senses an access to the ROM with address line A23 high.
; Current (8M addressing space) ROMs only use address lines A2 to A22,
; so if A23 is asserted it will be ignored (the ROMS are aliased
; into 16M of space). With no test adapter, the aliased ROM location will
; be read and may be recognised. The test adapter may selectively disable
; ROMs when A21 is high, causing arbitrary data to be read. This data
; ROMs when A23 is high, causing arbitrary data to be read. This data
; should be dependent on the previous ROM read operation, and will
; therefore be predictably not equal to the data read when the ROMs are
; aliased.
; The assumption that A21 is unused may be invalidated by a later issue
; of the PCB. A22 is therefore asserted at the same time : this will then
; be used on a PCB where A22 is tracked to a test connector and 8Mbit ROMS
; are used. Machines using larger ROMs than 8 Mbit (4M addressing space)
; will require explicit decoding or a new communication scheme.
; The assumption that A23 is unused may be invalidated by a later issue
; of the PCB. Machines using larger ROMs than 8Mbytes will require explicit
; decoding or a new communication scheme.
;
......@@ -82,7 +83,7 @@ ts_GetCommand ROUT
;
; Load up the registers for the test interface communication -
;
[ :LNOT: CanLiveOnROMCard
LDR r0,%01 ; set zero in r0
ADD pc,pc,r0 ;(generally useful constant - especially for skip)
01
......@@ -98,7 +99,22 @@ ts_GetCommand ROUT
ADDS r2,pc,r2 ; adjust r2 for ROM-relative address
ADDS r4,r0,r0 ; clear output accumulator
04 ; where pc is when added to r2
|
; Point r2 at a word which contains 0 in 0-8MB physical space.
; Note that this code doesn't cope with the case where it can't find a zero
; word anywhere in the whole ROM. I don't think that this is a problem.
MOV r0, #0 ; expected below
MOV r2, #0 ; start of physical space
01
LDR r1, [r2, #4]!
TEQ r1, r0 ; is it zero?
BNE %01
ADD r2, r2, #ts_Alias_bits ; point to zero word in ghost
MOV r1, #-1 ; expected below
04
]
; do an RD operation (four strobes) to ensure interface cleared
LDR r3,[r2]
......@@ -613,7 +629,7 @@ ts_PosText ROUT
;
ts_SendLCDCmd
[ :LNOT: CanLiveOnROMCard
LDR r0,%01 ; set zero in r0
ADD pc,pc,r0
01
......@@ -629,7 +645,23 @@ ts_SendLCDCmd
ADDS r2,pc,r2 ; adjust r2 for ROM-relative address
ADDS r0,r0,r0 ; dummy (to keep labels nearby !)
04 ; where pc points when added to r2
|
; Point r2 at a word which contains 0 in 0-8MB physical space.
; If this word still reads as 0 when its ghost/alias is read from 8-16MB space
; (A23 set) then we don't have a test box, otherwise we do.
; Note that this code doesn't cope with the case where it can't find a zero
; word anywhere in the whole ROM. I don't think that this is a problem.
MOV r0, #0 ; ts_send_command_byte expects r0=0
MOV r2, #0 ; start of physical space
01
LDR r1, [r2, #4]!
TEQ r1, r0 ; is it zero?
BNE %01
ADD r2, r2, #ts_Alias_bits ; point to zero word in ghost
04
]
; Wait - gap between successive WS attempts or successive bytes
......
TestSrc/InitModule 0 → 100644
View file @ c3d9625b
; > InitModule
; Source for Pre_InitModule, PostInitModule im_InitModules & im_Pre_InitPodMod functions
;
; ***********************************
; *** C h a n g e L i s t ***
; ***********************************
;
; Date Who Version Description
; ---- --- ------- -----------
; 13-Jun-96 BAR 0.01 Started
; 27-Jun-96 BAR 0.02 Added code to check the type of reset we
; just had. If power-on then we can display
; messages, else exit back.
;
;
; Provides functions to display messages for when we initiliseing the
; modules. Messages are only sent to the display adapator, if the Reset Type
; is Power On Reset. The code uses the constant ResetType, defined in
; kernel.hdr.KernelWS. This is the address of a memory location, where the
; type of reset is stored. ResetType is a sigle bit flag, in bit 0 of the
; memory location. The constant PowerOnReset is used, which is defined in
; Kernel.s.newReset. This defines the value that a power-on reset should be.
; The value of PowerOnReset should always be 1. (This corresponds to the
; value of the bit 4 of IOMD's IRQA Status register, where the Power-on
; reset status is initially stored.) The value of ResetType can vary between
; different versions of the operating system.
;
;
; im_Pre_InitModule is called before a module is started
; im_Post_InitModule is called after a module is started, only if there was
; an error
; im_InitModules is called at the start of initiliseing the modules.
; im_Pre_InitPodMod is called when we start the podule manager.
;
; All the functions will push registers r0-r12 to the stack, check the
; poweron reset status, if power on reset, then send a message to the
; display adaptor and then pull them off at the end.
;
;
im_Pre_InitModule ROUT
Push "r0-r12" ; Put r0->r12 on to stack
; Get the type of reset we had, if power-on - can use display adaptor
LDR r1,=ResetType ; Load r1 with address of ResetType
LDR r0,[r1] ; Get contents of ResetType = what type of reset
CMPS r0,#PowerOnReset ; Compare with PowerOnReset (1)
;if equel send message
LDREQ r4,[r11,#ROMModule_Name] ; Put ptr to mod name in r4
BLEQ ts_SendText ; Send the txt to disp adaptor
;restore the reg's.
Pull "r0-r12" ; Get r0->r12 from the stack
MOV pc,r14 ; Return to caller
im_Post_InitModule ROUT
1
= "Module Bad",0
Push "r0-r12" ; Put r0->r12 on to stack
; Get the type of reset we had, if power-on - can use display adaptor
LDR r1,=ResetType ; Load r1 with address of ResetType
LDR r0,[r1] ; Get contents of ResetType = what type of reset
CMPS r0,#PowerOnReset ; Compare with PowerOnReset (1)
BNE %FT2 ; IF not equal jump to 2 AKA don't send msg.
Push "r0" ; Put r0 in stack again
ADR r4, %BT1 ; r4 = bad module msg
BL ts_SendText ; Send the txt to disp adaptor
Pull "r0" ; Get r0 from the stack
ADDVC r4,r0,#4 ; If V Clr add 4 to r0 - point to err txt
BLVC ts_SendText ; Send the txt to disp adaptor
2
Pull "r0-r12" ; Get r0->r12 from the stack
MOV pc,r14 ; Return to caller
im_InitModules ROUT
1
= "Init Modules :",0
Push "r0-r12" ; Put r0->r12 on to stack
; Get the type of reset we had, if power-on - can use display adaptor
LDR r1,=ResetType ; Load r1 with address of ResetType
LDR r0,[r1] ; Get contents of ResetType = what type of reset
CMPS r0,#PowerOnReset ; Compare with PowerOnReset (1)
;if equel send message
ADREQ r4, %BT1 ; r4 = init msg
BLEQ ts_SendText ; Send the txt to disp adaptor
;restore the reg's.
Pull "r0-r12" ; Get r0->r12 from the stack
MOV pc,r14 ; Return to caller
im_Pre_InitPodMod ROUT
1
= "Podule",0
Push "r0-r12" ; Put r0->r12 on to stack
; Get the type of reset we had, if power-on - can use display adaptor
LDR r1,=ResetType ; Load r1 with address of ResetType
LDR r0,[r1] ; Get contents of ResetType = what type of reset
CMPS r0,#PowerOnReset ; Compare with PowerOnReset (1)
;if equel send message
ADREQ r4, %BT1 ; r4 = init msg
BLEQ ts_SendText ; Send the txt to disp adaptor
;restore the reg's.
Pull "r0-r12" ; Get r0->r12 from the stack
MOV pc,r14 ; Return to caller
END
TestSrc/Ioc
View file @ c3d9625b
......@@ -3,7 +3,7 @@
TTL RISC OS 2+ POST IO controller
;
; This initial IOC test simply reports the content of the IRQ and FIRQ
; registers, to show any unexpected pending IRQs.
; registers, to show any unexpected pending IRQs.
; Certain of these should really be cleared, and the effect of an
; interrupt tested.
;
......@@ -16,27 +16,31 @@
; 29-Nov-91 ArtG Added IOC bus test using mask registers
; 20-Jun-93 ArtG Modified for 29-bit IOMD test
; 18-Nov-94 RCM Morris changes
; 15-May-96 BAR Changes for 7500FE - new IOMD ID code.
; Now list 3 ID codes.
; 17-Jun-96 BAR Change ts_IOMD_IDn definitions to point to
; definitions in IOMDL
; 09-Jul-96 BAR Improve IOMD ID code.
;
;
;------------------------------------------------------------------------
[ IO_Type = "IOMD"
[ IO_Type = "IOMD"
ts_IObase * IOMD_Base
ts_IOmask * &00fffff0 ;&1fffffff
ts_IOreg1 * IOMD_VIDEND ;IOMD_VIDCUR
ts_IOreg2 * IOMD_VIDSTART
ts_IObswap * 32
ts_IOMD_ID * &D4E7
[ MorrisSupport
ts_IOMD_IDmorris * &5B98
]
|
ts_IOMD_ID1 * IOMD_Original
ts_IOMD_ID2 * IOMD_7500
ts_IOMD_ID3 * IOMD_7500FE
|
ts_IObase * IOC
ts_IOmask * &ff0000
ts_IOreg1 * IOCIRQMSKA
ts_IOreg2 * IOCIRQMSKB
ts_IObswap * 16
]
]
ts_IOCreg
MOV r0,#0 ; zero error accumulator
......@@ -64,27 +68,31 @@ ts_IOCreg
LDR r8, =ts_IOmask
ANDS r8, r0, r8
MOV pc,r14 ; return error if any bit failed
MOV pc,r14 ; return error if any bit failed
ts_IOCstat
LDR r3, =ts_IObase
MOV r0,#0
[ IO_Type = "IOMD"
LDRB r1,[r3,#IOMD_ID1]
ORR r0,r0,r1, LSL #(32-24)
LDRB r1,[r3,#IOMD_ID0]
ORR r0,r0,r1
LDR r1,=ts_IOMD_ID
CMPS r0,r1 ; check IOMD identity
[ MorrisSupport
LDRNE r1,=ts_IOMD_IDmorris ; allow for Morris variant
CMPNES r0,r1
]
MOV r0,r0,LSL #16
LDRB r1,[r3,#IOMD_VERSION]
ORR r8,r0,r1, LSL #12
MOV pc,r14
|
LDR r3, =ts_IObase ; r3 points to IO Chip base address
MOV r0,#0 ; clear r0
[ IO_Type = "IOMD"
; Check IOMD chip variants
LDRB r1,[r3,#IOMD_ID1] ; load r1 with IOMD ID high byte
LDRB r0,[r3,#IOMD_ID0] ; load r1 with IOMD ID low byte
ORR r0,r0,r1, LSL #8 ; Or r0 and r1 - shifted left 8, put in r0
LDR r1,=ts_IOMD_ID1 ; get Ref IOMD ID code #1
CMPS r0,r1 ; check =to IOMD ID Code #1
LDRNE r1,=ts_IOMD_ID2 ; If not ID1, get Ref IOMD ID code #2
CMPNES r0,r1 ; If not ID1, check =to IOMD ID Code #2
LDRNE r1,=ts_IOMD_ID3 ; if not ID1 and ID2, get Ref IOMD ID code #3
CMPNES r0,r1 ; If not ID1 and ID2, check =to IOMD ID Code #3
MOV r0,r0,LSL #16 ; Move ID code in to top 16 bits
LDRB r1,[r3,#IOMD_VERSION] ; Load r with IOMD Version number
ORR r8,r0,r1, LSL #12 ; Or r0 and r1 - shifted left 12, put in r8
MOV pc,r14 ; extit to whence came from.
|
; Check IOC chip variants
LDRB r1,[r3,#IOCControl]
ORR r0,r0,r1, LSL #(32 - 8)
LDRB r1,[r3,#IOCIRQSTAA]
......@@ -96,7 +104,7 @@ ts_IOCstat
ANDS r1,r1,#0 ; return zero flag (OK)
MOV pc,r14
]
]
END
END
TestSrc/LEDDelay 0 → 100644
View file @ c3d9625b
; > LEDDelay
; Source for LEDDelay function
;
; ***********************************
; *** C h a n g e L i s t ***
; ***********************************
;
; Date Who Version Description
; ---- --- ------- -----------
; 30-May-96 BAR 0.01 Started
;
; Will provide a 1/4 second delay for flashing the LED's
ld_quarter_sec * (35000*8) ; 1/4 Second delay !
ld_LED_Delay ROUT
; Generate the required delay between changing the LED status
; On entry ....
; r4 = required delay time
; Register usage ....
; r0, general scratch pad
;
01 LDR r0,=ld_quarter_sec ; Load r0 with 1/4 seconds delay
02 SUBS r0,r0,#1 ; subtract one
BNE %02 ; back we go .... pause for a 1/4 second
SUBS r4,r4,#1 ; subtract one
BNE %01 ; repeat the pause for the flash duration
MOV pc,r14 ; Return to caller
END
TestSrc/Mem1IOMD
View file @ c3d9625b
......@@ -13,7 +13,13 @@
; ---- ---- -------
; 1-Jun-93 ArtG Derived from Mem1 for use on Medusa
; 18-Nov-94 RCM Morris changes
;
; 24-Jun-96 BAR Change the IOMD ID code checking code,
; instead of checking for ARM7500 and skipping
; ARM7500 specifi code if not equal, not
; checks for original (RriscPC) IOM ID code
; and skip if equal, thus ARM7500 and
; ARM7500FE parts still do correct test.
; 08-Jul-96 BAR Ensure r0 is cleared before checking IOMD vsn no.
;
;------------------------------------------------------------------------
......@@ -40,17 +46,25 @@
ts_LineTest
[ MorrisSupport
MOV r12, #IOMD_Base
LDRB r0, [r12, #IOMD_ID0]
CMP r0, #&98
LDRB r0, [r12, #IOMD_ID1]
CMPEQ r0, #&5B
BNE ts_LineTestIOMD ; NOT MORRIS assume Medusa hardware
MOV r0,#0 ; Clear out r0
LDRB r1,[r12,#IOMD_ID1] ; load r1 with IOMD ID high byte
ORR r0,r0,r1, LSL #8 ; Or r0 and r1 - shifted left 8, put in r0
LDRB r1,[r12,#IOMD_ID0] ; load r1 with IOMD ID low byte
ORR r0,r0,r1 ; Or r0 and r1, put in r0
LDR r1,=ts_IOMD_ID1 ; get Ref IOMD ID code #1 (Original)
CMPS r0,r1 ; check for IOMD ID Code #1
BEQ ts_LineTestIOMD ; Original IOMD, not 7500 or 7500FE, assume RiscPC hardware
;
; ts_LineTest for Morris
; Here bceause its an ARM7500 or ARM7500 'FE' variant : Morris H/W
;
MOV r11, #IOMD_DRAMWID_DRAM_32bit * &0F ;set all 4 banks to be 32bit initially
LDR r1, =ts_IOMD_ID3
TEQ r0, r1 ; are we on FE part?
ORREQ r11, r11, #IOMD_DRAMWID_EDO_Enable :OR: IOMD_DRAMWID_RASCAS_3 :OR: IOMD_DRAMWID_RASPre_4
; if so, then enable EDO and slower RASCAS and RASPre times
; ts_LineTest for Morris
;
MOV r14, #IOMD_Base
STRB r11, [r14, #IOMD_DRAMWID]
MOV r0,#MMUC_D ; enable 32-bit addressing of data
......@@ -226,7 +240,7 @@ ts_LineTest
; If the RAM found still seems OK, add it's size into the r10 accumulator
; Working or not, carry on to check the next bank.
ADD r10,r10,r13 ; accumulate DRAM if any found
ADD r10,r10,r13 ; accumulate DRAM if any found
ADD r12, r12, #DRAM1PhysRam-DRAM0PhysRam ; move onto next bank
MOV r9, r9, LSL #1 ; shunt up position in DRAMWID
CMP r9, #&0010 ; if more banks to do
......@@ -283,10 +297,10 @@ ts_LineTestIOMD
22
ADR r4,%BT5 ; Add size (in hex Mbyte)
MOV r8,r9, LSL #24 ; to "VRam : " message
BL ts_MoreText
BL ts_MoreText
; Worked out what size VRAM is, and set up IOMD register.
; Do a data line test on the resulting array, repeated at oddword address to
; Worked out what size VRAM is, and set up IOMD register.
; Do a data line test on the resulting array, repeated at oddword address to
; ensure both banks get tested with walking 0 and walking 1
ADR r4,%BT4
......@@ -443,7 +457,7 @@ ts_LineTestIOMD
; If the RAM found still seems OK, add it's size into the r10 accumulator
; Working or not, carry on to check the next bank.
ADD r10,r10,r13 ; accumulate DRAM if any found
ADD r10,r10,r13 ; accumulate DRAM if any found
ADD r12, r12, #DRAM1PhysRam-DRAM0PhysRam ; move onto next bank
MOV r9, r9, LSL #2 ; shunt up position in DRAMCR
CMP r9, #&100 ; if more banks to do
......@@ -510,7 +524,7 @@ ts_Dataline ROUT
;
10 MOV r6,r1 ; set pointer for a write loop
MOV r5,#1 ; set initial test pattern
MVN r4,r5 ; and it's inverse
MVN r4,r5 ; and it's inverse
11
STMIA r6!,{r4-r5} ; write the patterns
......@@ -522,7 +536,7 @@ ts_Dataline ROUT
;
MOV r6,r1 ; set pointer for a read loop
MOV r5,#1 ; set initial test pattern
MVN r4,r5 ; and it's inverse
MVN r4,r5 ; and it's inverse
MOV r0,#0 ; accumulate result
21
LDMIA r6!,{r2-r3} ; read the patterns
......@@ -537,7 +551,7 @@ ts_Dataline ROUT
;
; After all checks at this address group, report back errors
;
MOVS r0,r0 ; check for any result bits set
MOVS r0,r0 ; check for any result bits set
MOV pc,r14 ; return r0 with error map (or 0)
......@@ -555,7 +569,7 @@ ts_Dataline ROUT
;
; It works something like :
;
; MaxRam = PhysRam | (Memory size - 4);
; MaxRam = PhysRam | (Memory size - 4);
; for (pattern = 4; pattern < memsize; pattern <<= 1 )
; *(PhysRam ^ pattern) = pattern;
; *(MaxRam ^ pattern) = ~pattern;
......@@ -658,7 +672,7 @@ ts_Byteword ROUT
STRB r2,[r1,r2] ; write byte (0, 1, 2 or 3)
MOV r4,r2,LSL #3 ; calculate expected result
MOV r5,#&ff
MOV r5,#&ff
MVN r5,r5,LSL r4
AND r5,r5,r3 ; word signature, byte removed
ORR r5,r5,r2,LSL r4 ; byte signature inserted
......@@ -673,7 +687,7 @@ ts_Byteword ROUT
; Loop for next byte
;
ADD r2,r2,#1 ; Bump byte counter
CMPS r2,#4 ; ... until 4 byte strobes tested
CMPS r2,#4 ; ... until 4 byte strobes tested
BLO %BT02
;
; byte strobes all tested : check for errors
......@@ -687,5 +701,4 @@ ts_Byteword ROUT
ts_endline
END
\ No newline at end of file
END
TestSrc/Mem3
View file @ c3d9625b
......@@ -6,6 +6,8 @@
; 24.04.90 0.10 ArtG Added ROM size test
; 15.05.90 1.00 ArtG Changed to put checksum at (end - 2 words)
; 17.05.90 1.01 ArtG Changed to get ROM length from vectot table
; 16-Aug-96 1.02 JRH Gets ROM start using PC-relative addressing,
; to support OSimages in 1st or 2nd ROM bank
;
;
; This file will perform quick checksum test on the OS ROMS.
......@@ -37,7 +39,8 @@ ts_CRCsize * (2 * 4)
ts_ROM_checksum
MOV r1, #&00 ; initialise accumulator
LDR r0, =PhysROM ; initialise pointer
ADRL r0, ROM ; initialise pointer using PC-relative
; addressing (could be 1st or 2nd bank)
LDR r2, [r0, #ts_ROMSIZE] ; initialise endstop
ADD r2, r2, r0 ; - must be at least 8 words
SUB r2, r2, #(10 * 4) ; below the real endpoint
......@@ -93,7 +96,8 @@ loop1 LDMIA r0!, {r4 - r11} ;LOAD r4 TO r11 WITH THE CONTENTS
ts_ROM_alias ROUT
MOV r0,#PhysROM ; get some words from ROM start
ADRL r0, ROM ; initialise pointer using PC-relative
; addressing (could be 1st or 2nd bank)
LDR r3,[r0, #ts_ROMSIZE] ; get the ROM length word
LDMIA r0,{r4,r5,r6,r7}
MOV r1,#(16 * 1024)
......
TestSrc/ROMCard 0 → 100644
View file @ c3d9625b
; > TestSrc.ROMCard
TTL NCOS Support for ROM Cards
;
; Tests for presence of a 2,4 or 8MB OS image in 2nd ROM bank and jumps to it.
;
; This doesn't really belong in the POST sources, but lives here because it
; needs to happen soon after boot. This file is included inline by Begin before
; it starts calculating the ROM checksum
;
; Relies on width of the 2nd ROM bank already being set to 32bit.
; If 16bit extension ROM support is required then s.ARM600 must set ROMCR1 back
; to 16bit-wide.
;
; No registers are preserved and, unlike some other parts of the POST code, it
; assumes it is running on a fully-functional ARM & IOMD.
;
;------------------------------------------------------------------------
; History
;
; Date Name Comment
; ---- ---- -------
; 16-Aug-96 JRH First release
; 05-Sep-96 BAR Add code to switch out the progress colour screens.
; See begin (2.17 for details).
; Can't have CanLiveOnROMCard TRUE without ROMCardSupport
ASSERT ROMCardSupport
GBLL DebugROMCard
DebugROMCard SETL {FALSE}
ts_RC_MinOSsize * (2*1024*1024)
ts_RC_MaxOSsize * (8*1024*1024)
ts_RC_2ndbank * (16*1024*1024)
ts_RC_idoffset * -16 ; offset from end of image
ROMCardTest ROUT
; DEBUG: set up VIDC for VGA, assuming 32M clock
[ DebugROMCard
MOV r1, #ts_VIDCPhys
LDR r0, =&40ffffff ; White
STR r0, [r1]
]
[ CanLiveOnROMCard
TST pc, #ts_RC_2ndbank ; running out of 2nd ROM bank?
BNE %FT99 ; skip all this if so
]
[ DebugROMCard
LDR r0, =&4000ffff ; Yellow
STR r0, [r1]
]
MOV r12, #ts_RC_MinOSsize ; start with this size image
B %FT00
ts_RC_idword = "NCOS" ; id string
ts_RC_LDRPCInst & &E59FF
00
ADD r2, r12, #ts_RC_2ndbank ; end of image
LDR r1, ts_RC_idword ; id word to look for
LDR r0, [r2, #ts_RC_idoffset]
CMP r0, r1
BNE %FT90 ; try next size if no match
; Found the id string, now see if it checksums to 0.
; Following code ripped off from Mem3.
;
; r0 IS A POINTER TO THE LOCATIONS IN MEMORY.
; r1 HAS THE CALCULATED CHECKSUM.
; r2 HOLDS A COUNTER INDICATION HOW MANY WORDS ARE LEFT TO GET
; r3 is a temporary variable (no it isn't)
; r4 TO r11 ARE USED TO LOAD THE CONTENTS OF 8 LOCATIONS FROM THE ROM.
;
[ DebugROMCard
MOV r1,#ts_VIDCPhys
LDR r0, =&407f7fff ; Fetching Pink
STR r0, [r1]
]
MOV r1, #&00 ; initialise accumulator
MOV r0, #ts_RC_2ndbank ; initialise pointer
ADD r2, r0, r12 ; initialise endstop, >= 8 words
SUB r2, r2, #(8 * 4) ; below the real endpoint
RC_loop1
LDMIA r0!, {r4 - r11} ; get 8 words & post-inc
01
ADD r1, r1, r4
ADD r1, r1, r5
ADD r1, r1, r6
ADD r1, r1, r7
ADD r1, r1, r8
ADD r1, r1, r9
ADD r1, r1, r10
ADD r1, r1, r11
02
ASSERT ((%02 - %01) = 32) ; else r2 won't count down correctly
CMP r0, r2
BNE RC_loop1 ; loop until pointer reaches endstop
LDMIA r0, {r4 - r9} ; get last 6 words (miss last 2 in ROM)
03
ADD r1, r1, r4
ADD r1, r1, r5
ADD r1, r1, r6
ADD r1, r1, r7
ADD r1, r1, r8
ADDS r1, r1, r9 ; NOTE: Z set => checksum OK
04
ASSERT (((%04 - %03) + (2*4)) = 32)
BNE %FT90 ; Skip if checksum not zero
; We have a valid image. Now work out where to jump to in it.
; Can't just jump to the start because 1st instruction is an LDR PC.
; Code ripped off from Tim's Softloader (thanks Tim)
[ DontShowProgressColours
; Display "Jumping to 2nd ROM bank" colour
MOV_fiq r0,r12_fiq ; restore the faultcode bits
ANDS r0,r0,#(R_EXTERN :OR: R_TESTED) ; If test adapter present,
; NE : Adaptor fitted, show progress.
; EQ : No Adaptor fitted, don't show progress
BEQ %FT10 ; EQ : Don't show colours
]
MOV r1, #ts_VIDCPhys
LDR r0, =C_2NDBANK
STR r0, [r1]
10
[ DebugROMCard
; Delay
MOV r0, #0
MOV r1, #(2*1024*1024)
15
LDMIA r0!, {r2}
CMP r0, r1
BNE %BT15
]
MOV r0, #ts_RC_2ndbank ; start of 2nd ROM image
LDR r3, [r0] ; load 1st instruction of ROM image
AND r2, r3, #&FF000000
TEQ r2, #&EA000000 ; is it a branch
BNE %FT20 ; [no, so try something else]
MOV r3, r3, LSL #(32-21) ; extract offset within ROM
ADD r0, r0, r3, LSR #(32-21-2) ; convert to byte offset
ADD pc, r0, #8 ; allow for pre-fetch
; check for LDR PC, [PC, +/-#x]
20 MOV r4, r3, LSR #12
LDR r5, ts_RC_LDRPCInst
ORR r4, r4, #1 << (23-12)
TEQ r4, r5
30 ; endlessloop
BNE %BT30 ; not either, so stuck
EOR r3, r3, r4, LSL #12 ; extract offset, and up/down bit
TST r3, #1 << 23 ; NE => bit was 0, so -ve
RSBNE r3, r3, #1 << 23 ; get rid of bit 23 and negate
ADD r3, r3, #8 ; offset in ROM we're reading
LDR r3, [r0, r3] ; address to jump to
ADD pc, r0, r3 ; jump to it
; Try next image size up
90 MOV r12, r12, LSL #1 ; double the size
CMP r12, #ts_RC_MaxOSsize
BLE %BT00
[ DebugROMCard
MOV r1, #ts_VIDCPhys
LDR r0, =&407fff7f ; Pale Green
STR r0, [r1]
; Delay
MOV r0, #0
MOV r1, #(2*1024*1024)
95
LDMIA r0!, {r2}
CMP r0, r1
BNE %BT95
B %FT99 ; No image found
LTORG
]
; Fall through to POST code
99
END
TestSrc/ShowIOMDRs 0 → 100644
View file @ c3d9625b
; > ShowIOMDRs
; Source for ShowIOMDRegisters functions
;
; ***********************************
; *** C h a n g e L i s t ***
; ***********************************
;
; Date Who Version Description
; ---- --- ------- -----------
; 24-Jun-96 BAR 0.01 Started.
; 05-Jul-96 BAR 0.02 Fix all sorts of bugs ... !
; 08-Jul-96 BAR 0.03 Fixed some more bugs ... hopfully !
; 25-Jul-96 BAR 0.04 Fixed some more bugs ... hopfuly !
; 29-Jul-96 BAR 0.05 Changed not to show skipped.
; Basically working now.
;
; Will show the contents of selected IOMD registers via the display adaptor.
;
; Show contents of IOMD Regs via display adaptor
; Note : Contents of the registers are not checked, therefore this code will
; not thus won't cause a failure. Contents can't be relied upon,
; because of changes to H/W OS etc..
;
ALIGN
sir_IgnoreTable & &88888888 ;+00C,+008,+004,+000
& &88888888 ;+01C,+018,+014,+010
& &88888888 ;+02C,+028,+024,+020
& &88888888 ;+03C,+038,+034,+030
& &88888888 ;+04C,+048,+044,+040
& &88888888 ;+05C,+058,+054,+050
& &88888888 ;+06C,+068,+064,+060
& &00888888 ;+07C,+078,+074,+070
& &88008888 ;+08C,+088,+084,+080
& &88888800 ;+09C,+098,+094,+090
& &88880000 ;+0AC,+0A8,+0A4,+0A0
& &00000000 ;+0BC,+0B8,+0B4,+0B0
& &88888800 ;+0CC,+0C8,+0C4,+0C0
& &00008888 ;+0DC,+0D8,+0D4,+0D0
& &90888888 ;+0EC,+0E8,+0E4,+0E0
& &00909090 ;+0FC,+0F8,+0F4,+0F0
& &00000000 ;+10C,+108,+104,+100
& &00000000 ;+11C,+118,+114,+110
& &00000000 ;+12C,+128,+124,+120
& &00000000 ;+13C,+138,+134,+130
& &00000000 ;+14C,+148,+144,+140
& &00000000 ;+15C,+158,+154,+150
& &00000000 ;+16C,+168,+164,+160
& &00000000 ;+17C,+178,+174,+170
& &A0A0A0A0 ;+18C,+188,+184,+180
& &00008888 ;+19C,+198,+194,+190
& &00000000 ;+1AC,+1A8,+1A4,+1A0
& &00000000 ;+1BC,+1B8,+1B4,+1B0
& &00A0A0A0 ;+1CC,+1C8,+1C4,+1C0
& &A0A0A0A0 ;+1DC,+1D8,+1D4,+1D0
& &00A00088 ;+1EC,+1E8,+1E4,+1E0
& &00888888 ;+1FC,+1F8,+1F4,+1F0
;
; The above is the Show Register Ignore table. It defines if a register is ;
; to be shown and if it is what size the register is. Registers are ;
; expressed as an offset from the base address of IOMD. The registers are ;
; word aligned. To reduce size this table uses one byte per register. The
; table is arranged so that each word repesents 4 registers. The size of the
; register is either 8, 16 or 32 bits, which can be repesented in hex as
; &08, &10 and &20. Threrefore the maximum bit in any byte needed for size
; is bit 5. Therefore bit 8 is used as the flag to indicate if the register
; is to be used, whilst the remaining 7 bits are used for the size. A size
; of 0 is not allowed, therfore the following values for each byte can be
; expected :-
; <= &80 Register will be skipped
; = &88 Show the register and its 8 bits wide
; = &90 Show the register and its 16 bits wide
; = &A0 Show the register and its 32 bits wide
; Any other value is liable to cause havoc !
sir_ShowIOMDRegs ROUT
;
; Read the IOMD Register.
;
; Display Adaptor has a 16 char display.
; 32bit no. is 8 chars long
; Display Columns &80+ : 0123456789012345
; Start message : IOMD Regs:
; Each location read : +01FC 12345678
; Each location skipped : +01FC Skipped
;
; Define the messages
;"0123456789ABCDEF"
ALIGN
1
= "IOMD Regs:",0
ALIGN
2
= "+",&FF,&FF,&FF,&8B,&FF,&FF,&FF,&FF,&FF,0
;"+123 12345"
ALIGN
3
= "+",&FF,&FF,&FF,&89,"Skipped",0
;"+123 Skipped"
ALIGN
4
= "+",&FF,&FF,&FF,0
;"+123"
ALIGN
5
= &88,&FF,&FF,&FF,&FF,&FF,&FF,&FF,&FF,0
;" 12345678"
ALIGN
;
; Define some constants
;
sir_mask8 * &FF ; 8 bit register mask
sir_mask16 * &FFFF ; 16 bit register mask
sir_mask32 * &FFFFFFFF ; 32 bit register mask
sir_MaxOffset * &1FC ; Maximum register offset.
;
; ts_showtext I/f is :-
; r4 = text string to leave
; r8 = number to subsitute
; r0 - r3, r5 - r7 corrupted
;
; r9 = table loop counter +1
; r10 = iomd offset loop counter +4
; r11 = iomd base
; tempory copy of r1, contents of IOMD - 32bit data
; r12 = table address
;
MOV r13,r14 ; Put r14 in r13 for later use.
MOV r0,#0 ; data read from the Ignore table
MOV r1,#0 ; data read from iomd
MOV r4,#0 ; Pointer to string for display adaptor
MOV r8,#0 ; Number to subsitue in display adaptor
MOV r9,#0 ; Ignore table counter (+1)
MOV r10,#0 ; IOMD Offset counter (+4)
MOV r11,#0 ; IOMD's base address.
; Tempory copy of r1.
ADR r12,sir_IgnoreTable ; Get IOMD Ignore table address.
;
sir_loop
; ok, lets do some work here guys
LDRB r0,[r12,r9] ; Get data from Ignore Table
CMPS r0,#&80 ; Check top bit set
; BLE sir_DisplaySkip ; Jump to display skip msg if skipped
; Don't show skipped - makes post too long,
; Remove comment to re-instate and comment line below
BLE sir_LoopControl ; Jump to loop control.
AND r0,r0,#&7F ; Mask off top bit to get reg size
CMPS r0,#&08 ; Is reg size = 8
LDREQ r0,=sir_mask8 ; If yes : mask = &FF
BEQ sir_cont ; Jump on to continue
CMPS r0,#&10 ; Is reg size = 16
LDREQ r0,=sir_mask16 ; If yes : mask = &FFFF
BEQ sir_cont ; Jump on to continue
CMPS r0,#&20 ; Is reg size = 32
LDREQ r0,=sir_mask32 ; If yes : mask = &FFFFFFFF
sir_cont
; Ok, we've got the mask in r0, lets get the data from IOMD
LDR r11,=IOMD_Base ; Get IOMD's base address.
; Need to 'cos r11 is also used as tmp store for r1
LDR r1,[r11,r10] ; Get data from IOMD (base [r11] + offsert [r10])
AND r1,r1,r0 ; Mask off the reqd. data
MOV r8,r10,LSL #20 ; Put offset that was read into r8 and
; shifted left 20 to fill top 3 nibles
MOV r2,#&10 ; Put CMP data in r2, this will be shift left 12
CMPS r0,r2,LSL #12 ; Is mask < &10000 ? (&10<<12)
BHI sir_TwoLine ; Mask > &10000 : jump to code to show
; offset & data on two lines
; The mask is less then &10000
ADD r8,r8,r1 ; Add to r8 the masked data
ADR r4,%BT2 ; r4 -> result message #2
BL ts_SendText ; Anyway : Display the message :-
; Mask < &10000 : +XXX XXXXX
B sir_LoopControl ; Go to loop control
sir_TwoLine
; Code to disply the offset and data on two lines, because the data is 32
; bits wide.
; The mask is greater then &1000
; r1 has the data read from IOMD in it.
ADR r4,%BT4 ; r4 -> result message #4
MOV r11,r1 ; Need to make a tempory copy of R1
BL ts_SendText ; Anyway : Display the message :-
; Mask > &10000 : +XXX
MOV r8,r11 ; r8 = the masked data
; r11 is the tempory copy of r1
ADR r4,%BT5 ; r4 -> result message #5
BL ts_MoreText ; Add the data to the line.
B sir_LoopControl ; Go to loop control
sir_DisplaySkip
; Ok, we don't want to display this register
MOV r8,r10,LSL #20 ; Mask < &10000 : r8 = offset that was read
; shifted left 20 to fill top 3 nibles
; r8 = offset that was skipped
ADR r4,%BT3 ; R4 -> skipping message
BL ts_SendText ; Display the message
sir_LoopControl
; ok lets see if we need to do some more
ADD r9,r9,#1 ; Increment table counter
ADD r10,r10,#4 ; Increment IOMD offset counter
CMP r10,#sir_MaxOffset ; Have we reached the end ?
BLE sir_loop ; If <= end then loop back
; Nop, that's it all done !
MOV pc,r13 ; Return to caller, r13 help retn addr.
END
TestSrc/ToggleLED 0 → 100644
View file @ c3d9625b
; > ToggleLED
; Source for ToggleLED function
;
; ***********************************
; *** C h a n g e L i s t ***
; ***********************************
;
; Date Who Version Description
; ---- --- ------- -----------
; 29-May-96 BAR 0.01 Started
;
; This file will provide support to flash the standby/on LED's.
;
IOMD_IOLINES * (IOMD_Base+&0C)
IOMD_IOLINES_INPUTS * &7B
IOMD_STANDBY_LED_BIT * 1<<7
tl_Toggle_LEDs ROUT
; Toggle the standby/on LEDs
; On entry ....
; Nothing.
; Register usage ....
; r0, general scratch pad
; r1, addr of IOMD_IOLINES
;
LDR r1, =IOMD_IOLINES ; r1 = addr of IOMD_IOLINES
LDRB r0,[r1] ; load r0 with the byte pointed to by r1
EOR r0,r0,#IOMD_STANDBY_LED_BIT ; Toggle the LED bit; ExOR
ORR r0,r0,#IOMD_IOLINES_INPUTS ; OR with the default I/O settings
STRB r0,[r1] ; store a byte of r0 in to loc pointed to by r1
MOV pc, r14 ; Return to caller
END
Version
View file @ c3d9625b
......@@ -4,8 +4,8 @@
GBLS VString
GBLS Date
Version SETA 360
VString SETS "3.60"
Date SETS "13 Apr 1995" ; release/srcfiler vers 4.27
Version SETA 452
VString SETS "4.52"
Date SETS "07 Nov 1996"
END
hdr/ExportVals/s/GetVals
View file @ c3d9625b
......@@ -16,9 +16,15 @@
GET Hdr:Macros
GET Hdr:System
GET Hdr:Machine.<Machine>
; Hack!
GBLL med_00001_debug
med_00001_debug SETL {FALSE}
GET ^.PublicWS
GET ^.KernelWS
MACRO
LabelValue $LabelName
LCLS String
......@@ -65,5 +71,6 @@ String SETS "$String" :CC: ", R" :CC: ((:STR: Register) :RIGHT: 1)
LabelValue VDWSSize
LabelValue ScreenBlankFlag
LabelValue ScreenBlankDPMSState
LabelValue Export_ResetType
END
hdr/ExportVals/values
View file @ c3d9625b
......@@ -13,6 +13,7 @@
; limitations under the License.
;
ARM stand alone Macro Assembler Version 2.00
VideoPhysAddr held at 00000170
Label Export_BgEcfOraEor has the value &000004C0
Label Export_FgEcfOraEor has the value &00000480
Label Export_BranchToSWIExit has the value &01F037FC
......@@ -35,3 +36,4 @@ Label Export_VduDriverWorkSpace has the value &00001000
Label VDWSSize has the value &00003000
Label ScreenBlankFlag has the value &0000047C
Label ScreenBlankDPMSState has the value &0000047D
Label Export_ResetType has the value &00000322
hdr/KernelWS
View file @ c3d9625b
......@@ -194,7 +194,10 @@ OldOpt SETA {OPT}
; 31-Oct-94 AMcC/RM/WT Added CLine_Softcopy for Morris monitor id
; 03-Nov-94 AMcC Export ScreenBlankFlag and ScreenBlankDPMSState
; (for DPMSUtils: part of RISC OS releases 3.50 and 3.60)
; 28-Mar-95 JRH Added NVRamSize and RTCFitted, conditioned on E2ROMSupport
; 06-Feb-95 SMC Increased SVC stack size to 12K.
; 18-Jan-96 JRH Removed CLine_Softcopy cos not needed
; 06-Feb-96 SMC Increased DefIRQ1Vspace for IRQC registers
;
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Memory map:
......@@ -955,7 +958,7 @@ DRAMSizeExtra # 4 * 12 ; blocks so allocate 3 extra word pairs per bank
PhysRamTableEnd # 0
! 0, "VideoPhysAddr held at ":CC::STR:(VideoPhysAddr)
VRAMSize # 4 ; Amount of VRAM (in bytes) (may be more than 2M)
VRAMSize # 4 ; Amount of VRAM (in bytes) (may be more than 2M) (at &200 last time I checked)
VRAMWidth # 4 ; 0 => no VRAM, 1 => 32-bits wide, 2 => 64-bits wide
VideoBandwidth # 4 ; video bandwidth in bytes/sec
L2PTSize # 4 ; Amount of memory (in bytes) used for static L2PT
......@@ -964,13 +967,22 @@ L2PTSize # 4 ; Amount of memory (in bytes) used for static L2
SoftCamMapSize # 4 ; Amount of memory (in bytes) used for soft CAM map
; (whole number of pages)
InitKbdWs # 16 ; Workspace for reset keyboard IRQ code (was 12 changed for Morris)
CLine_Softcopy # 1 ; Added for Morris - Monitor id
AlignSpace 16 ; skipped bit must end on 16-byte boundary
SkippedTablesEnd # 0
CMOSRAMCache # 240 ; Cache for CMOS RAM
[ E2ROMSupport
NVRamSize # 1 ; Size of NVRam (E2ROM & CMOS) fitted in 256byte units
RTCFitted # 1 ; flag =1 iff RTC is fitted
]
Export_ResetType # 1 ; &322 ; bit 0 => 1 = por, 0 = not por ; bits 1-7 reserved (zero)
ASSERT Export_ResetType = ResetType
ASSERT ?Export_ResetType = ?ResetType
AlignSpace
AppSpaceDANode # DANode_NodeSize ; Dummy area node for application space (not on list)
FreePoolDANode # DANode_NodeSize ; Area node for free pool
SysHeapDANode # DANode_NodeSize ; Area node for system heap
......@@ -1386,7 +1398,7 @@ RedirectBuff |#| OscliBuffSize
; ARM600/700 specific but for the moment it is assumed that they are
; used on the same machines).
[ MorrisSupport
DefIRQ1Vspace * 12*4+12*23+2*256+64 + 5*12+3*4+32 ;Morris adds 5 more
DefIRQ1Vspace * 12*4+12*23+2*256+64 + 7*4+12*16+32+256 ;Morris adds 2 more IRQ registers
|
DefIRQ1Vspace * 12*4+12*23+2*256+64 ; for size checking in MOS
]
......
hdr/KeyWS
View file @ c3d9625b
......@@ -44,6 +44,7 @@ ModulesOK # 1 ; bit0=1 => modules are initialised
; bit1=1 => we have offered service
LastLED # 1 ; last request for LED change, so we don't send repeated ones
MouseType # 1 ; current pointer device type
MousePresent # 1 ; mouse detected
[ Keyboard_Type = "A1A500"
JustGotKbId # 1
......
hdr/PublicWS
View file @ c3d9625b
......@@ -26,6 +26,7 @@ OldOpt SETA {OPT}
; 15-Jun-94 AMcC Created - holds values 'exported' from KernelWS
; Corresponds to Values previously set in VickySpace / NewSpace
; 03-Nov-94 AMcC Added ScreenBlankFlag and ScreenBlankDPMSState
; 12-Jul-95 JRH Added RestType
;
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Memory map values: (in address order)
......@@ -45,6 +46,9 @@ IRQsema # 4
^ &00000114
MEMC_CR_SoftCopy # 4
^ &00000322
ResetType # 1 ; bit 0 => type of last reset. Other bits reserved (zero).
^ &0000047C
ScreenBlankFlag # 1 ; 0 => unblanked, 1 => blanked
......@@ -94,5 +98,6 @@ SoundDMABufferSize * &1000
^ &01F06000
SoundDMABuffers # SoundDMABufferSize * 2
OPT OldOpt
END
hdr/VduExt
View file @ c3d9625b
......@@ -117,6 +117,7 @@ Flag_HiResMono * 16
Flag_DoubleVertical * 32
Flag_HardScrollDisabled * 64 ; set when outputting to a sprite
Flag_FullPalette * 128 ; set when palette is not brain damaged
Flag_InterlacedMode * 256 ; set when full interlaced mode
OPT OldOpt
......
s/ARM600
View file @ c3d9625b
......@@ -54,6 +54,17 @@ DebugAborts SETL {FALSE}
; (on IOMD we allow this to be in any of the 4 RAM sites, ie you don't have to have RAM in any particular SIMM site)
; Consequently the base of the fixed system pages is not known at assembly time, so has to be passed in a register
; to the generic code.
;
; 17-Jun-96 BAR Change speed settings for the second bank of ROM space.
; 09-Jul-96 BAR Improve IOMD ID vsn code - two places.
; Change ROM Speed settings for 7500FE and non-7500FE parts.
; 25-Jul-96 BAR Correct bug in video bandwidth code, wrong label used.
; 16-Aug-96 JRH Programming of 2nd ROM bank (IOMD ROMCR1 register):
; reinstated ExtROMSupport code, added CanLiveOnROMCard code
; MemInitTable:
; If ExtROMSupport: added assertion that ImageSize <= 4096
; and maps 4MB of each ROM bank.
; Otherwise: always maps 8MB of ROM space independant of ImageSize
; Fixed page allocation is as follows
......@@ -521,6 +532,9 @@ RamSkipTable
ASSERT DRAMOffset_PageZero + L2PTSize < DRAMOffset_L2PT
LTORG
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; InitMEMC - Initialise memory controller
......@@ -532,13 +546,14 @@ RamSkipTable
; endif
InitMEMC ROUT
;
[ MEMC_Type = "IOMD"
; Note: On IOMD, all accesses go to ROM until the first write cycle.
MOV r12, #IOMD_Base
[ MorrisSupport
[ MorrisSupport
; Perform a dummy write to IOMD (some harmless register) to get it out of ROM force mode.
; Reads from IOMD will return garbage before this has happened. If we're actually running out
; of 32-bit wide ROMs on MORRIS, a write will already have happened, to get ROMCR0 from
......@@ -547,46 +562,149 @@ InitMEMC ROUT
STRB r12, [r12, #IOMD_DMAREQ] ; writes to DMAREQ are ignored
LDRB r0, [r12, #IOMD_ID0]
CMP r0, #&98
LDRB r0, [r12, #IOMD_ID1]
CMPEQ r0, #&5B
;MOVEQ r3, #xxxx
BNE MedusaInit ; NOT MORRIS assume Medusa hardware
LDRB r2,[r12,#IOMD_ID1] ; load r2 with IOMD ID high byte
LDRB r0,[r12,#IOMD_ID0] ; load r0 with IOMD ID low byte
ORR r0,r0,r2, LSL #8 ; Or r0 and r2 - shifted left 8, put in r0
LDR r2,=IOMD_7500 ; get Ref IOMD ID code for IOMD in a 7500
CMPS r0,r2 ; check for IOMD ID Code for IOMD in a 7500
BEQ init7500cpu ; If equal, got to init7500cpu
LDRNE r2,=IOMD_7500FE ; If not, get ID code for IOMD in a 7500FE
CMPNES r0,r2 ; If not, check for IOMD ID Code for IOMD in a 7500FE
BNE MedusaInit ; NOT MORRIS assume Medusa hardware
init7500FEcpu
; Here bceause its an ARM7500 'FE' variant
; Program the CPU, Memory and IO clock prescalers
; Set the prescalers to :-
; CPUCLK divide by 2
; MEMCLK divide by 1
; IOCLK divide by 1
;
; MORRIS contains IOMD equivalant circuitry. Due to lack of VRAM, presence of 16/32 bit support
; and a different ROM speed register, we program it slightly differently.
MOV r0, #IOMD_CLKCTL_CpuclkHalf + IOMD_CLKCTL_MemclkNormal + IOMD_CLKCTL_IOclkNormal
STRB r0, [r12, #IOMD_CLKCTL] ; initialise all the prescalers.
;
; Set ROM speed, take care to preserve 16-bit mode bit...
;
; PSwindell wants all prescalers set to divide by 1
; According to BSiddle on the 15-May-96, Omega will use burst mode roms: use 93nS burst, 156nS initial.
; According to TDbson on the 09-Jul-96, Omega will handle ROMS up to 120nS and 70nS.
; Thus the ROM speed should be initilised to :-
; Half Speed or H bit, clear, which is ON ! : Half the delays, thus DOUBLE all clock ticks.
; Non-Sequental delay : 10 Ticks : Half speed on, so select 5 ticks (5*2)
; Burst delay : 8 Ticks : Half speed on, so select 4 ticks (4*2)
; Remember the Memory clock on Omega is faster than on previous products.
; The fast flash devices used for Omega testing should be able to cope even
; though they aren't burst devices.
LDRB r0, [r12, #IOMD_ROMCR0] ; Get contents of ROMCR0 in to r0
AND r0, r0, #&40 ; clear all but the 16-bit mode flag
ORR r0, r0, #IOMD_ROMCR_HalfSpeed + IOMD_ROMCR_NSTicks_5 + IOMD_ROMCR_BTicks_4
STRB r0, [r12, #IOMD_ROMCR0] ; Prog. the reg.s
; Program the 2nd ROM bank
[ ExtROMSupport
; Unless we're actually running from the 2nd ROM bank (CanLiveOnROMCard), we don't know how fast
; the extension ROM in the 2nd bank goes, so program it for a slow default speed
[ CanLiveOnROMCard
TST pc, #PhysExtROM ; are we running out of the 2nd ROM bank?
STRNEB r0, [r12, #IOMD_ROMCR1] ; Program the 2nd bank the same as the 1st
[ ExtROMis16bit
MOVEQ r0, #IOMD_ROMCR_HalfSpeed + IOMD_ROMCR_16bit + IOMD_ROMCR_NSTicks_7 + IOMD_ROMCR_BurstOff
|
MOVEQ r0, #IOMD_ROMCR_HalfSpeed + IOMD_ROMCR_32bit + IOMD_ROMCR_NSTicks_7 + IOMD_ROMCR_BurstOff
]
STREQB r0, [r12, #IOMD_ROMCR1]
|;CanLiveOnROMCard
[ ExtROMis16bit
MOV r0, #IOMD_ROMCR_HalfSpeed + IOMD_ROMCR_16bit + IOMD_ROMCR_NSTicks_7 + IOMD_ROMCR_BurstOff
|
MOV r0, #IOMD_ROMCR_HalfSpeed + IOMD_ROMCR_32bit + IOMD_ROMCR_NSTicks_7 + IOMD_ROMCR_BurstOff
]
STRB r0, [r12, #IOMD_ROMCR1]
];CanLiveOnROMCard
|;ExtROMSupport
[ CanLiveOnROMCard
STRB r0, [r12, #IOMD_ROMCR1] ; Program the 2nd bank the same as the 1st
|
STRB r0, [r12, #IOMD_ROMCR1] ; 2nd bank unused: program it the same anyway
]
];ExtROMSupport
; Now program ASTCR to add wait states, since MEMCLK is fast relative to IOCLK
MOV r0, #IOMD_ASTCR_WaitStates
STRB r0, [r12, #IOMD_ASTCR]
B init7500cpu_common ; branch to common init code.
;
init7500cpu
; Here because its an ARM7500 variant - NON 'FE' device.
; Program the CPU, Memory and IO clock prescalers
; Set the prescalers to :-
; CPUCLK divide by 1
; MEMCLK divide by 1
; IOCLK divide by 1
;
MOV r0, #IOMD_CLKCTL_CpuclkNormal + IOMD_CLKCTL_MemclkNormal + IOMD_CLKCTL_IOclkNormal
STRB r0, [r12, #IOMD_CLKCTL] ; initialise all prescalers to div1
;
; Set ROM speed, take care to preserve 16-bit mode bit...
;
; According to RJKing on 6/5/94, Kryten will use burst mode roms: use 93nS burst, 156nS initial.
;
; We assume that the extension ROMs are the same access time and width as the main OS ROMS.
;
LDRB r0, [r12, #IOMD_ROMCR0]
AND r0, r0, #&40 ; clear all but 16-bit mode bit
[ NormalSpeedROMS
;Normal code
ORR r0, r0, #IOMD_ROMCR_Normal + IOMD_ROMCR_156 + IOMD_ROMCR_Burst93
; initialise ROM speed to 156.25nS, 93.75nS burst
; the fast EPROMS used for Kryten testing should be able to cope even though they aren't
; burst devices
|
;Slow ROM access for PSwindells test EPROMS. Paul requested 156nS (or slower), burst off.
ORR r0, r0, #IOMD_ROMCR_Normal + IOMD_ROMCR_187 + IOMD_ROMCR_BurstOff
! 0, "*** WARNING *** Slow ROM version ment for PSwindell"
]
STRB r0, [r12, #IOMD_ROMCR0]
STRB r0, [r12, #IOMD_ROMCR1] ; and do the same for extension ROMs (just in case)
; According to BSiddle on 09-Jul-96 - Omenga will need to set the burst speed to 4 ticks from 3 ticks.
; Thus the ROM speed should be initilised to :-
; Half Speed or H bit, Set, which is OFF ! : Don't half the delays.
; Non-Sequental delay : 5 Ticks : Half speed off, so select 5 ticks
; Burst delay : 4 Ticks : Half speed off, so select 4 ticks
; The fast EPROMS used for Kryten testing should be able to cope even though
; they aren't burst devices
LDRB r0, [r12, #IOMD_ROMCR0] ; Get contents of ROMCR0 in to r0
AND r0, r0, #&40 ; clear all but the 16-bit mode flag
ORR r0, r0, #IOMD_ROMCR_Normal + IOMD_ROMCR_NSTicks_5 + IOMD_ROMCR_BTicks_4
STRB r0, [r12, #IOMD_ROMCR0] ; Prog. the reg.s
; Program the 2nd ROM bank
[ ExtROMSupport
; Unless we're actually running from the 2nd ROM bank (CanLiveOnROMCard), we don't know how fast
; the extension ROM in the 2nd bank goes, so program it for a slow default speed
[ CanLiveOnROMCard
TST pc, #PhysExtROM ; are we running out of the 2nd ROM bank?
STRNEB r0, [r12, #IOMD_ROMCR1] ; Program the 2nd bank the same as the 1st
[ ExtROMis16bit
MOVEQ r0, #IOMD_ROMCR_Normal + IOMD_ROMCR_16bit + IOMD_ROMCR_NSTicks_7 + IOMD_ROMCR_BurstOff
|
MOVEQ r0, #IOMD_ROMCR_Normal + IOMD_ROMCR_32bit + IOMD_ROMCR_NSTicks_7 + IOMD_ROMCR_BurstOff
]
STREQB r0, [r12, #IOMD_ROMCR1]
|;CanLiveOnROMCard
[ ExtROMis16bit
MOV r0, #IOMD_ROMCR_Normal + IOMD_ROMCR_16bit + IOMD_ROMCR_NSTicks_7 + IOMD_ROMCR_BurstOff
|
MOV r0, #IOMD_ROMCR_Normal + IOMD_ROMCR_32bit + IOMD_ROMCR_NSTicks_7 + IOMD_ROMCR_BurstOff
]
STRB r0, [r12, #IOMD_ROMCR1]
];CanLiveOnROMCard
|;ExtROMSupport
[ CanLiveOnROMCard
STRB r0, [r12, #IOMD_ROMCR1] ; Program the 2nd bank the same as the 1st
|
STRB r0, [r12, #IOMD_ROMCR1] ; 2nd bank unused: program it the same anyway
]
];ExtROMSupport
; Now program ASTCR to *NOT* add wait states, since MEMCLK is slow relative to IOCLK
MOV r0, #IOMD_ASTCR_Minimal
STRB r0, [r12, #IOMD_ASTCR]
;
;
init7500cpu_common
; Common setup requirments for BOTH 7500 and 7500FE.
;
; MORRIS doesn't support VRAM. Kryten has same DRAM speed as Medusa
;
......@@ -599,22 +717,21 @@ InitMEMC ROUT
MOV r0, #0 ; Podule manager wants TypeA setting by default for all podules
STRB r0, [r12, #IOMD_ECTCR]
[ Select16BitSound
; All MORRIS based machines have 16bit 'Japanese' format sound DAC's
[ Japanese16BitSound
MOV r0, #2_10
STRB r0, [r12, #IOMD_VIDMUX]
]
]
B CommonInit
MedusaInit
]
] ; MorrisSupport
[ Simulator
[ Simulator
MOV r0, #IOMD_ROMCR_62 + IOMD_ROMCR_BurstOff ; make faster for simulation (no point in burst mode, it's
; no faster than the fastest initial speed)
|
[ RISCPCBurstMode
[ 1 = 1
|
[ RISCPCBurstMode
[ 1 = 1
ReadCop r0, CR_ID
BIC r0, r0, #&F ;ignore 4 bit revision field
LDR r2, =&41007100 ;Test for early 710's
......@@ -622,16 +739,21 @@ MedusaInit
MOVEQ r0, #IOMD_ROMCR_156 + IOMD_ROMCR_BurstOff ;cos they can't work in burst mode!
MOVNE r0, #IOMD_ROMCR_156 + IOMD_ROMCR_Burst93 ;610's 710A's and beyond can
! 0, "*** WARNING *** Burst mode enabled on RISC PC iff processor can cope"
|
|
MOV r0, #IOMD_ROMCR_156 + IOMD_ROMCR_Burst93
! 0, "*** WARNING *** Burst mode enabled on RISC PC"
]
|
]
|
MOV r0, #IOMD_ROMCR_156 + IOMD_ROMCR_BurstOff ; initialise ROM speed to 156.25ns (changed from 187ns 21-Jan-94)
]
]
]
] ; Simulator
STRB r0, [r12, #IOMD_ROMCR0]
[ :LNOT: ExtROMis16bit
STRB r0, [r12, #IOMD_ROMCR1] ; and do the same for extension ROMs (just in case)
|
MOV r0, #IOMD_ROMCR_16bit + IOMD_ROMCR_Normal + IOMD_ROMCR_156 + IOMD_ROMCR_BurstOff
STRB r0, [r12, #IOMD_ROMCR1] ; 16bit 156.25nS noburst (Lowest common denominator)
]
MOV r0, #IOMD_VREFCR_VRAM_256Kx64 :OR: IOMD_VREFCR_REF_16 ; select 16s refresh, assume 2 banks of VRAM
STRB r0, [r12, #IOMD_VREFCR]
......@@ -642,10 +764,11 @@ MedusaInit
MOV r0, #0 ; Podule manager wants TypeA setting by default for all podules
STRB r0, [r12, #IOMD_ECTCR]
|
| ; MEMC_Type = "IOMD"
LDR R0, ResetMemC_Value
STR R0, [R0] ; set ROM access times, refresh on flyback, no DMA
]
] ; MEMC_Type = "IOMD"
CommonInit
; On breaks (ie software resets) we have to turn the MMU off.
; This is slightly tricky if we've been soft-loaded!
......@@ -808,16 +931,23 @@ MemSize ROUT
[ MorrisSupport
;
LDRB r0, [r12, #IOMD_ID0]
CMP r0, #&98
LDRB r0, [r12, #IOMD_ID1]
CMPEQ r0, #&5B
;MOVEQ r3, #xxxx
BNE MemSizeIOMD ; NOT MORRIS assume Medusa hardware
LDRB r0, [r12, #IOMD_ID0] ; load r1 with IOMD ID high byte
LDRB r1, [r12, #IOMD_ID1] ; load r0 with IOMD ID low byte
ORR r0,r0,r1,LSL#8 ; Or r0 and r1, shifted left 8, put in r0
LDR r1,=IOMD_Original ; get Ref IOMD ID code - original
CMPS r0,r1 ; check for IOMD ID Code - original
BEQ MemSizeIOMD ; Not ID Code - original,
; therefore jump to Medusa hardware code
; else fall through to Morris code.
;
; MemSize for Morris
;
MOV r11, #IOMD_DRAMWID_DRAM_32bit * &0F ;set all 4 banks to be 32bit initially
LDR r1, =IOMD_7500FE
TEQ r0, r1 ; are we on FE part?
ORREQ r11, r11, #IOMD_DRAMWID_EDO_Enable :OR: IOMD_DRAMWID_RASCAS_3 :OR: IOMD_DRAMWID_RASPre_3
; if so, then enable EDO and slower RASCAS and RASPre times
MOV r14, #IOMD_Base
STRB r11, [r14, #IOMD_DRAMWID]
[ 1 = 0
......@@ -1064,8 +1194,13 @@ AllocateTheRAM
STR r0, [r14, #IOMD_VIDSTART] ; do same for VIDSTART
STR r0, [r14, #IOMD_VIDINIT] ; and for VIDINIT
; so we don't get a mess when we turn video DMA on later
LDR r4, =46500000 ; if no VRAM, then 46.5E6 bytes/sec bandwidth
LDRB r4, [r14, #IOMD_ID0]
LDRB r7, [r14, #IOMD_ID1]
ORR r4, r4, r7, LSL #8
LDR r7, =IOMD_7500FE ; if FE part, then assume EDO DRAM
TEQ r4, r7
LDREQ r4, =80000000 ; so allow 80E6 bytes/s
LDRNE r4, =44000000 ; else only allow 44E6 bytes/s
STR r4, [r2, #VideoBandwidth-PhysRamTable] ; store video bandwidth
ADD r4, r0, r1 ;form VIDEND (will be on mult. of SAM)
......@@ -1304,9 +1439,10 @@ MemSizeDone
STR r4, [r2, #VideoBandwidth-PhysRamTable]
]
ADRL r4, ROM ; use PC-relative addressing to get to start of image
TEQ r4, #PhysROM ; then see if it's the normal ROM address
BEQ %FT55 ; if so, then we're OK
ADRL r4, ROM ; use PCrelative addressing to get to start of image
TEQ r4, #PhysROM ; then see if it's the normal ROM address
TEQNE r4, #PhysExtROM ; or if it's the 2nd ROM bank
BEQ %FT55 ; if so, then we're not soft-loaded
SUB r1, r1, #OSROM_ImageSize*1024 ; if we've been soft-loaded, then we have ?M less than we thought
ADD r5, r4, #OSROM_ImageSize*1024 ; point r5 at end of ROM
......@@ -1640,16 +1776,13 @@ MemInitTable ; sz, U, C, B, logaddr, (ap, (physaddr))
MemInitSection 1, 1, 0, 0, &03500000, AP_None, &03400000 ; VIDC20 space
MemInitSection 2, 1, 0, 0, &03600000, AP_None, &03600000 ; LAGs
[ OSROM_ImageSize = 4096
[ ExtROMSupport ; System build option
ASSERT (OSROM_ImageSize <= 4096) ; No room for extension ROMs with an 8MB OS image
MemInitROMs 4, 1, 1, 1, &03800000, AP_Read ; ROM
MemInitROMs 4, 1, 1, 1, &03C00000, AP_Read ; ROM
|
MemInitROMs 2, 1, 1, 1, &03800000, AP_Read ; ROM
MemInitROMs 2, 1, 1, 1, &03A00000, AP_Read ; ROM
MemInitROMs 2, 1, 1, 1, &03C00000, AP_Read ; ROM
MemInitROMs 2, 1, 1, 1, &03E00000, AP_Read ; ROM
]
MemInitSection 4, 1, 1, 1, &03C00000, AP_Read, &01000000 ; Extension ROM
|
MemInitROMs 8, 1, 1, 1, &03800000, AP_Read ; ROM (1st or 2nd bank)
]
[ :LNOT: NewStyle_Screen
MemInitVideo 16, 1, 0, 1, &05000000, AP_None ; real screen (section-mapped)
......
s/ChangeDyn
View file @ c3d9625b
......@@ -104,6 +104,7 @@ DAHandler_PreGrow * 0
DAHandler_PostGrow * 1
DAHandler_PreShrink * 2
DAHandler_PostShrink * 3
DAHandler_TestShrink * 4 ; new reason added to find amount area could shrink by
; Number of entries in page block on stack
......@@ -1708,7 +1709,8 @@ DAReason_Remove * 1
DAReason_GetInfo * 2
DAReason_Enumerate * 3
DAReason_Renumber * 4
DAReason_Limit * 5
DAReason_ReturnFree * 5
DAReason_Limit * 6
DynArea_NewAreas * &100 ; Allocated area numbers start here
DynArea_NewAreasBase * &04000000 ; Allocated area addresses start here
......@@ -1723,17 +1725,18 @@ DynAreaFlags_NotUserDraggable * 1 :SHL: 7
[ DAF_SpecifyBit
DynAreaFlags_NeedsSpecificPages * 1 :SHL: 8 ; whether area will ever require particular physical pages
]
DynAreaFlags_Shrinkable * 1 :SHL: 9 ; whether area should be shrunk when need more space in free pool
DynAreaFlags_AccessMask * DynAreaFlags_APBits :OR: DynAreaFlags_NotBufferable :OR: DynAreaFlags_NotCacheable :OR: DynAreaFlags_DoublyMapped
; The following bits are only present in page flags
TempUncacheableShift * 9
TempUncacheableShift * 10
PageFlags_TempUncacheableBits * 15 :SHL: TempUncacheableShift ; temporary count of uncacheability, used by DMA mgr
PageFlags_Unavailable * 1 :SHL: 13 ; physical page may not be requested by a PreShrink handler
PageFlags_Unavailable * 1 :SHL: 14 ; physical page may not be requested by a PreShrink handler
; Temporary flags only used by kernel
PageFlags_Required * 1 :SHL: 14 ; physical page asked for by handler
PageFlags_Required * 1 :SHL: 15 ; physical page asked for by handler
DynamicAreaSWI ENTRY
BL DynAreaSub
......@@ -1750,6 +1753,7 @@ DynAreaSub
B DynArea_GetInfo
B DynArea_Enumerate
B DynArea_Renumber
B DynArea_ReturnFree
; unknown OS_DynamicArea reason code
......@@ -2148,6 +2152,45 @@ DynArea_Renumber ALTENTRY
SETV
EXIT
;**************************************************************************
;
; DynArea_ReturnFree - Return total free space, including shrinkables
;
; Internal routine called by DynamicAreaSWI
;
; in: r0 = reason code (5)
; r1 = area number to exclude, or -1 to include all shrinkable areas
;
; out: r2 = total amount of free memory
;
DynArea_ReturnFree ALTENTRY
CMP r1, #-1 ; if no excluded area,
MOVEQ r10, r1 ; then point r10 nowhere
BEQ %FT10
BL CheckAreaNumber ; else check area number is valid
BCC UnknownDyn ; [unknown area]
10
MOV r11, #DAList
MOV r2, #0
LDR r2, [r2, #FreePoolDANode + DANode_Size] ; start with current size of free pool
20
LDR r11, [r11, #DANode_Link] ; load next area
TEQ r11, #0 ; if end of list
EXIT EQ ; then exit, with r2 = correct value
LDR lr, [r11, #DANode_Flags] ; load area flags
TST lr, #DynAreaFlags_Shrinkable ; must be shrinkable
TEQNE r11, r10 ; and not excluded area
BEQ %BT20 ; [don't try this one]
Push r3
BL CallTestShrink
ADD r2, r2, r3 ; add on amount if any
Pull r3
B %BT20 ; then go back for more
;**************************************************************************
;
; CheckAreaNumber - Try to find area with number r1
......@@ -2515,8 +2558,6 @@ AllocateBackingLevel2 ENTRY "r0-r8,r11"
CLRV
EXIT
LTORG
; Come here if not enough space in free pool to allocate level2
90
......@@ -2614,6 +2655,8 @@ InitDynamicAreas ENTRY "r0-r8,r11"
EXIT
LTORG
InitFreePoolTable
& 0 ; link: no more nodes on list
& ChangeDyn_FreePool
......@@ -2737,16 +2780,21 @@ AreaShrink
LDMIA r2, {r2, r3}
SUB lr, r3, r2 ; lr = amount dest could grow
LDR r2, [r11, #DANode_Size] ; amount src could shrink
CMP r2, lr
MOVCC lr, r2 ; lr = min(amount dest could grow, amount src could shrink)
CMP r1, lr
MOVHI r1, lr ; r1 = the most we want to move if we could
BLHI GenNotAllMovedError ; but if not all we still want error
SUB lr, r5, #1 ; lr = pagesize mask
BICS r1, r1, lr ; a pagesize multiple
BEQ IssueServiceMemoryMoved
CMP r1, lr
BLS %FT15
LDR r2, [r11, #DANode_Size] ; amount src could shrink
CMP r2, r1
BLCC TryToShrinkShrinkables
BCS %FT15 ; [we can now do it all]
; we can't move all that is required, so move smaller amount
MOV r1, lr ; move smaller amount
MOV r1, r2 ; move smaller amount
BL GenNotAllMovedError
SUB lr, r5, #1 ; lr = pagesize mask
BICS r1, r1, lr ; a pagesize multiple
......@@ -2902,6 +2950,23 @@ AreaGrow
B %FT65
62
; growing another area from free pool
; insert code here to check for shrinking shrinkable areas
CMP r1, lr ; if dest can't grow by this amount,
BHI %FT64 ; we're definitely not doing anything
CMP r2, r1 ; this should definitely set C=0 as required by TryToShrinkShrinkables
Push "lr"
BLCC TryToShrinkShrinkables
Pull "lr"
MOVCS r3, r1 ; if succeeded set r3 to number of bytes to do
BCS %FT65 ; and do it
64
; end of inserted code
MOV r4, #AppSpaceDANode
LDR r6, [r4, #DANode_Size] ; get current size of apl space
SUB r6, r6, #&8000 ; can't take away 0-&7FFF
......@@ -3063,6 +3128,53 @@ IssueServiceMemoryMoved
Pull "r0, r2-r9, r10, lr"
ExitSWIHandler
; ***********************************************************************************
;
; TryToShrinkShrinkables - Attempt to make more space by shrinking shrinkable areas if appropriate
;
; in: r1 = total amount we wish to have in src area (already limited by max_size of destination area)
; r2 = current size of src area
; r11 -> src area node (we don't do anything unless this is the free pool)
; r12 -> dst area node
; C = 0
;
; out: r2 = new size of src area
; C=0 => failed to move as much as we wanted
; C=1 => succeeded in moving as much as we wanted
TryToShrinkShrinkables Entry "r0,r1,r10"
LDR lr, [r11, #DANode_Number]
TEQ lr, #ChangeDyn_FreePool
EXITS NE ; if src <> free pool, exit with flags intact
MOV r10, #DAList
ASSERT DANode_Link = 0 ; because DAList has only link
10
LDR r10, [r10, #DANode_Link] ; and load next
CMP r10, #1 ; any more nodes?
EXIT CC ; no, then no match
TEQ r10, r12 ; check area <> dest
LDRNE lr, [r10, #DANode_Flags] ; and area is shrinkable
TSTNE lr, #DynAreaFlags_Shrinkable
BEQ %BT10 ; if not, try next area
SUBS r1, r1, r2 ; r1 = amount we still need
LDR lr, [r10, #DANode_Size] ; available size of this area
CMP lr, r1
MOVCC r1, lr ; min(amount we need, size of this area)
RSB r1, r1, #0 ; make negative - it's a shrink
MOV r0, #0
STR r0, [r0, #CDASemaphore] ; momentarily pretend we're not threaded
LDR r0, [r10, #DANode_Number]
SWI XOS_ChangeDynamicArea
MOV r0, #1
STR r0, [r0, #CDASemaphore-1] ; we're threaded again
LDR r1, [sp, #4] ; reload original r1
LDR r2, [r11, #DANode_Size] ; get new size of src area
CMP r2, r1
BCC %BT10 ; if still too small, loop
EXIT ; exit CS indicating success
; ***********************************************************************************
;
; DoTheGrow - Do one chunk of growing, small enough to fit into the page block on the stack
......@@ -3774,6 +3886,46 @@ CallPostGrow ENTRY "r0,r3,r4, r12"
LDMIA r12, {r12, pc} ; load workspace pointer and jump to handler
EXIT
; ***********************************************************************************
;
; CallTestShrink - Call test-shrink routine
;
; in: r11 -> area node
;
; out: If handler exits VC, then r3 = no. of bytes area can shrink by
; else r0 -> error block or 0 for generic error, and r3=0
;
CallTestShrink ENTRY "r0,r4,r5, r12"
LDR r0, [r11, #DANode_Handler] ; check if no handler
CMP r0, #0 ; if none (V=0)
EXIT EQ ; then exit
MOV r0, #DAHandler_TestShrink ; r0 = reason code
LDR r4, [r11, #DANode_Size] ; r4 = current size
MOV r5, #0
LDR r5, [r5, #Page_Size] ; set r5 = page size
ASSERT DANode_Handler = DANode_Workspace +4
ADD r12, r11, #DANode_Workspace
MOV lr, pc
LDMIA r12, {r12, pc} ; load workspace pointer and jump to handler
; shrink amount returned by handler may not be page multiple (according to spec),
; so we'd better make it so.
SUBVC lr, r5, #1
BICVC r3, r3, lr ; make page multiple
EXIT VC
TEQ r0, #0 ; if generic error returned
ADREQL r0, ErrorBlock_ChDynamNotAllMoved ; then substitute real error message
[ International
BLEQ TranslateError
]
STR r0, [sp]
MOV r3, #0 ; indicate no shrink possible
SETV
EXIT
; ***********************************************************************************
;
; MovePageAtR0ToR1WithAccessR6
......
s/GetAll
View file @ c3d9625b
......@@ -147,8 +147,7 @@ Fix16 SETL {TRUE}
GBLS VersionNo
VersionNo SETS "$VString ($Date)"
GBLS SystemName
SystemName SETS "RISC OS" ; ", p.k.a. Arthur a.k.a. Richard III"
; SystemName moved to Machine.* header files.
GBLS MosTitle
MosTitle SETS "$SystemName $VersionNo"
......@@ -191,8 +190,14 @@ RISCPCBurstMode SETL {FALSE}
;>>>RISC PC (no reason why it shouldn't) all references to RISCPCBurstMode
;>>>could be replaced by NormalSpeedROMS
GBLL Select16BitSound
Select16BitSound SETL {TRUE}
GBLL DoInitialiseMode
DoInitialiseMode SETL {TRUE}
GBLL Select16BitSound ; STBs and pre-IOMD systems don't have this link
Select16BitSound SETL {FALSE}
GBLL Japanese16BitSound
Japanese16BitSound SETL {TRUE}
GBLL Simulator ; running on simulator?
Simulator SETL {FALSE}
......@@ -261,7 +266,7 @@ IgnoreVRAM SETL {FALSE}
LateAborts SETL MEMM_Type = "ARM600" :LAND: {TRUE}
GBLL CheckProtectionLink ; if true, disallow CMOS RAM changes if link in protected position
CheckProtectionLink SETL (IO_Type = "IOMD") :LAND: {TRUE} ; NB affects Delete/Copy/R/T and 0-9/.
CheckProtectionLink SETL (IO_Type = "IOMD") :LAND: {FALSE} ; NB affects Delete/Copy/R/T and 0-9/.
GBLL RMTidyDoesNowt ; if true, RMTidy does nothing
RMTidyDoesNowt SETL (MEMC_Type = "IOMD") :LAND: {TRUE} ; should really be "machine has FSLock in ROM"
......@@ -319,6 +324,20 @@ StorkPowerSave SETL MorrisSupport ;False=> older A4 code only
GBLL FixR9CorruptionInExtensionSWI ; whether R9 corruption by ExtensionSWI handler is fixed
FixR9CorruptionInExtensionSWI SETL {FALSE} ; currently FALSE as CC's !SpellMod (possibly others) rely on it being broken
GBLL InterlacedPointer
InterlacedPointer SETL {TRUE} ; enable code to do proper interlaced pointer
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; New Options for STB/NCD builds - JHarris 8/1/96
; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
GBLL ValidateCMOS ; Apply special CMOS-corruption detection code, and do minimal default settings.
ValidateCMOS SETL {TRUE}
GBLL UseHClk
UseHClk SETL {TRUE} ; Use HClk when driving TVs.
[ DebugHeaps
! 0, "*** WARNING *** Heap debugging assembled in"
......
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