Enable/disable HAL cache controller when enabling/disabling ARM caches

Detail:
  s/VMSAv6 - Modify OS_MMUControl to ensure any HAL-based cache is disabled when either the ARM I or D cache is disabled. This emulates the behaviour of an integrated L2 cache controller.
Admin:
  Tested on Pandaboard


Version 5.35, 4.79.2.254. Tagged as 'Kernel-5_35-4_79_2_254'

VersionASM

@@ -13,11 +13,11 @@
                         GBLS    Module_ComponentPath
 Module_MajorVersion     SETS    "5.35"
 Module_Version          SETA    535
-Module_MinorVersion     SETS    "4.79.2.253"
-Module_Date             SETS    "16 Jan 2015"
-Module_ApplicationDate  SETS    "16-Jan-15"
+Module_MinorVersion     SETS    "4.79.2.254"
+Module_Date             SETS    "17 Jan 2015"
+Module_ApplicationDate  SETS    "17-Jan-15"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.35 (4.79.2.253)"
-Module_HelpVersion      SETS    "5.35 (16 Jan 2015) 4.79.2.253"
+Module_FullVersion      SETS    "5.35 (4.79.2.254)"
+Module_HelpVersion      SETS    "5.35 (17 Jan 2015) 4.79.2.254"
                         END

VersionNum

@@ -5,19 +5,19 @@
  *
  */
 #define Module_MajorVersion_CMHG        5.35
-#define Module_MinorVersion_CMHG        4.79.2.253
-#define Module_Date_CMHG                16 Jan 2015
+#define Module_MinorVersion_CMHG        4.79.2.254
+#define Module_Date_CMHG                17 Jan 2015
 
 #define Module_MajorVersion             "5.35"
 #define Module_Version                  535
-#define Module_MinorVersion             "4.79.2.253"
-#define Module_Date                     "16 Jan 2015"
+#define Module_MinorVersion             "4.79.2.254"
+#define Module_Date                     "17 Jan 2015"
 
-#define Module_ApplicationDate          "16-Jan-15"
+#define Module_ApplicationDate          "17-Jan-15"
 
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.35 (4.79.2.253)"
-#define Module_HelpVersion              "5.35 (16 Jan 2015) 4.79.2.253"
+#define Module_FullVersion              "5.35 (4.79.2.254)"
+#define Module_HelpVersion              "5.35 (17 Jan 2015) 4.79.2.254"
 #define Module_LibraryVersionInfo       "5:35"

s/VMSAv6

@@ -399,6 +399,22 @@ MMUControl_ModifyControl ROUT
 
         ARMop   Cache_InvalidateAll,,,r3
 10
+        ; If I+D currently enabled, and at least one is turning off, turn off
+        ; HAL L2 cache
+        TST     r1, #MMUC_C
+        TSTNE   r1, #MMUC_I
+        BEQ     %FT11
+        TST     r2, #MMUC_C
+        TSTNE   r2, #MMUC_I
+        BNE     %FT11
+        LDR     r0, [r3, #Cache_HALDevice]
+        TEQ     r0, #0
+        BEQ     %FT11
+        Push    "r1-r3,r12"
+        MOV     lr, pc
+        LDR     pc, [r0, #HALDevice_Deactivate]
+        Pull    "r1-r3,r12"
+11
         BIC     lr, r1, r2              ; lr = bits going from 1->0
         TST     lr, #MMUC_C             ; if cache turning off then clean data cache first
         BEQ     %FT15
@@ -413,6 +429,22 @@ MMUControl_ModifyControl ROUT
         LDR     r3,=ZeroPage
         ARMop   Cache_InvalidateAll,,,r3
 20
+        ; If either I+D was disabled, and now both are turned on, turn on HAL
+        ; L2 cache
+        TST     r1, #MMUC_C
+        TSTNE   r1, #MMUC_I
+        BNE     %FT30
+        TST     r2, #MMUC_C
+        TSTNE   r2, #MMUC_I
+        BEQ     %FT30
+        LDR     r0, [r3, #Cache_HALDevice]
+        TEQ     r0, #0
+        BEQ     %FT30
+        Push    "r1-r3,r12"
+        MOV     lr, pc
+        LDR     pc, [r0, #HALDevice_Activate]
+        Pull    "r1-r3,r12"
+30
         PLP     r4                      ; restore IRQ state
         Pull    "r0,r3,r4,r5,pc"