Improve ClearPhysRAM performance

Detail:
  s/HAL - Change ClearPhysRAM to always map in memory as cacheable + bufferable instead of only on StrongARM, as it's an optimisation that can help other platforms as well.
Admin:
  Tested on BB-xM, StrongARM RiscPC


Version 5.35, 4.79.2.231. Tagged as 'Kernel-5_35-4_79_2_231'

VersionASM

@@ -13,11 +13,11 @@
                         GBLS    Module_ComponentPath
 Module_MajorVersion     SETS    "5.35"
 Module_Version          SETA    535
-Module_MinorVersion     SETS    "4.79.2.230"
-Module_Date             SETS    "20 Jul 2014"
-Module_ApplicationDate  SETS    "20-Jul-14"
+Module_MinorVersion     SETS    "4.79.2.231"
+Module_Date             SETS    "23 Jul 2014"
+Module_ApplicationDate  SETS    "23-Jul-14"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.35 (4.79.2.230)"
-Module_HelpVersion      SETS    "5.35 (20 Jul 2014) 4.79.2.230"
+Module_FullVersion      SETS    "5.35 (4.79.2.231)"
+Module_HelpVersion      SETS    "5.35 (23 Jul 2014) 4.79.2.231"
                         END

VersionNum

@@ -5,19 +5,19 @@
  *
  */
 #define Module_MajorVersion_CMHG        5.35
-#define Module_MinorVersion_CMHG        4.79.2.230
-#define Module_Date_CMHG                20 Jul 2014
+#define Module_MinorVersion_CMHG        4.79.2.231
+#define Module_Date_CMHG                23 Jul 2014
 
 #define Module_MajorVersion             "5.35"
 #define Module_Version                  535
-#define Module_MinorVersion             "4.79.2.230"
-#define Module_Date                     "20 Jul 2014"
+#define Module_MinorVersion             "4.79.2.231"
+#define Module_Date                     "23 Jul 2014"
 
-#define Module_ApplicationDate          "20-Jul-14"
+#define Module_ApplicationDate          "23-Jul-14"
 
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.35 (4.79.2.230)"
-#define Module_HelpVersion              "5.35 (20 Jul 2014) 4.79.2.230"
+#define Module_FullVersion              "5.35 (4.79.2.231)"
+#define Module_HelpVersion              "5.35 (23 Jul 2014) 4.79.2.231"
 #define Module_LibraryVersionInfo       "5:35"

s/HAL

@@ -2138,11 +2138,9 @@ ClearPhysRAM ROUT
         MOV     r9, #0
         MOV     r10, #0
         MOV     r11, #0
-   [ {FALSE} ; Not used at the moment
         MOV     r12, #0
         MOV     r13, #0
         MOV     r14, #0
-   ]
         MSR     CPSR_c, #F32_bit+SVC32_mode
 
       [ EmulatorSupport
@@ -2211,14 +2209,11 @@ ClearPhysRAM ROUT
         LDMIA   r9!, {r10, r11}
         MOV     r11, r11, LSR #12                       ; get rid of flags
 50
-        ; Map in this area
-        MOV     r0, #L1_B
-      [ StrongARM
-        ARM_read_ID r2
-        AND     r2, r2, #&F000
-        CMP     r2, #&A000
-        ORREQ   r0, r0, #L1_B+L1_C                      ; StrongARM can't burst to B=1 C=0
-      ]
+        ; Map in this area, cacheable + bufferable to ensure burst writes are
+        ; performed. We're careful to not partially overwrite any pages which
+        ; are being used, so this shouldn't cause any issues due to being
+        ; cachable + potentially doubly mapped.
+        MOV     r0, #L1_B+L1_C
         MOV     r1, r10
         MOV     r2, #0
         BL      RISCOS_AccessPhysicalAddressUnchecked
@@ -2226,19 +2221,20 @@ ClearPhysRAM ROUT
         ; Inner loop will process one page at a time to keep things simple
         MOV     r3, r11
         MSR     CPSR_c, #F32_bit+FIQ32_mode             ; switch to our bank o'zeros
+        MOV     r2, #0
 60
         CMP     r4, r5
         CMPHS   r6, r4
+        ADD     r1, r0, #4096
         BHS     %FT80
         ; Clear this page
-        ADD     r1, r0, #4096
 70
-        STMDB   r1!, {r8-r11}
-        STMDB   r1!, {r8-r11}
+        STMIA   r0!, {r2,r8-r14}
+        STMIA   r0!, {r2,r8-r14}
         TEQ     r0, r1
         BNE     %BT70
 80
-        ADD     r0, r0, #4096                           ; increment log addr
+        MOV     r0, r1                                  ; increment log addr
         ADD     r4, r4, #1                              ; increment page no
         SUBS    r3, r3, #1                              ; decrement length
         MOVNES  r1, r0, LSL #12                         ; check for MB limit
@@ -2246,10 +2242,11 @@ ClearPhysRAM ROUT
 
         MSR     CPSR_c, #F32_bit+SVC32_mode
 
+        ; Clean & invalidate the cache before the 1MB window closes
       [ StrongARM
-        ; If it was B=1 C=1 for StrongARM, clean the cache before the 1MB window closes.
-        ; We're careful to only ever write the PhysicalAccess area so only a clean is needed,
-        ; no flush. The next user of PhysicalAccess will restore everything to bufferable.
+        ; StrongARM requires special clean code, because we haven't mapped in
+        ; DCacheCleanAddress yet. Cheat and only perform a clean, not full
+        ; clean + invalidate (should be safe as we've only been writing)
         ARM_read_ID r2
         AND     r2, r2, #&F000
         CMP     r2, #&A000
@@ -2259,8 +2256,12 @@ ClearPhysRAM ROUT
         ARMA_clean_DCentry r0
         MOVS    r1, r0, LSL #12                         ; start of the MB?
         BNE     %BT85
+        B       %FT91
 90
       ]
+        ARMop Cache_CleanInvalidateAll
+91
+
         ADD     r10, r10, r11, LSL #12                  ; r10+(r11-r3) = next MB
         MOVS    r11, r3                                 ; next block needed? also resets r11 ready for next pass
         SUBNE   r10, r10, r3, LSL #12
@@ -2292,6 +2293,8 @@ CPR_skipped
 
         MACRO
         MakeSkipTable $addr, $size
+        ASSERT  ($addr :AND: 31) = 0
+        ASSERT  ($size :AND: 31) = 0
         &       $addr, $size
         MEND