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Commit 5f9b5a63 authored by ROOL's avatar ROOL 🤖
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This commit was manufactured by cvs2git to create branch 'StrongARM'. 

Sprout from Black 1996-11-05 09:41:48 UTC Neil Turton <nturton@gitlab.riscosopen.org> 'Import from cleaned 360 CD'
Cherrypick from master 1996-11-05 09:40:48 UTC Neil Turton <nturton@gitlab.riscosopen.org> 'Clean reimport of hdr.RISCOS (real commit date 2008-03-28 by bavison), without any of the 3rd party allocations.':
    hdr/RISCOS
Delete:
    Doc/!ReadMe
    Doc/0197276.02
    Doc/5thColumn/Manual
    Doc/A540Extend
    Doc/Kernel
    Doc/KernlSplit
    Doc/MMUControl
    Doc/MemMaps/130
    Doc/MemMaps/258
    Doc/Mode22
    Doc/Modes
    Doc/MonLead
    Doc/PaletteV
    Doc/PrivDoc/5thColumn/Concept
    Doc/PrivDoc/MMPM
    Doc/PrivDoc/ScreenMode
    Doc/ReadSysInf
    Doc/TVmodesMed,dde
    OldTestSrc/A600tlb
    OldTestSrc/Arm3
    OldTestSrc/Begin
    OldTestSrc/Cmos
    OldTestSrc/ExtCmd
    OldTestSrc/ExtIO
    OldTestSrc/Ioc
    OldTestSrc/MEMC1
    OldTestSrc/Mem1IOMD
    OldTestSrc/Mem1MEMC1
    OldTestSrc/Mem2
    OldTestSrc/Mem3
    OldTestSrc/Mem4
    OldTestSrc/Mem5
    OldTestSrc/TestMain
    OldTestSrc/Vidc
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OldTestSrc/Cmos deleted 100644 → 0
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; > TestSrc.Cmos
TTL RISC OS 2+ POST battery-backed RAM access
;
; A function to read bytes from CMOS, for use in verifying the checksum
; and reading memory test flag & video modes.
;------------------------------------------------------------------------
; History
;
; Date Name Comment
; ---- ---- -------
; 05-Apr-91 ArtG Initial version, based on IICMod.
;
;
;------------------------------------------------------------------------
;
; in:
; R0 = device address (bit 8 - 15 register address )
; R1 = length of block to read
; R2 = initial sum value
;
; out: R0 = sum of all bytes in block
; R1 - R13 trashed
;
ts_CMOSread ROUT
MOV R13,R14
MOV R8,R2 ; initialise accumulator
MOV R7,R1 ; initialise byte counter
MOV R6,R0 ; stash register address
MOV R2, #IOC
MOV R0, #-1 ; ensure timer is ticking
STRB R0, [R2, #Timer0LL] ; (nonzero in input latch)
STRB R0, [R2, #Timer0LH]
STRB R0, [R2, #Timer0GO] ; load the count registers
BL ts_Start
BEQ %FT30 ; check clock line toggles OK
AND R0, R6, #&FE
BL ts_TXCheckAck ; transmit device address (write)
BVS %FT30
MOV R0, R6, LSR #8
BL ts_TXCheckAck ; write register address
BVS %FT30
BL ts_Start ; Extra START bit to switch modes
AND R0, R6, #&FE
ORR R0, R0, #1
BL ts_TXCheckAck ; transmit device address (read)
BVS %FT30
20
BL ts_RXByte ; read byte from bus
ADD R8, R8, R0 ; accumulate total
SUBS R7, R7, #1 ; is it last byte ?
MOVNE R0, #0 ; no, then acknowledge with 0 bit
MOVEQ R0, #1 ; yes, then don't acknowledge
BL ts_ClockData ; but always send ack clock pulse
TEQ R7, #0 ; loop, until last byte
BNE %BT20
30
MOVVS R7, #-1 ; pass error indicator to caller
BL ts_Stop
MOV R0, R8
TEQ R7, #0 ; return zero flag if read OK
MOV PC,R13
; *****************************************************************************
;
; TXCheckACK - transmit a byte and wait for slave to ACK
;
; out: Trashes r0,r1,r2,r3,r4,r5,r9,r10,r11,r12
; V bit set on error.
;
ts_TXCheckAck ROUT
MOV R12,R14
BL ts_TXByte
BL ts_Acknowledge
MOVVC PC, R12 ; acknowledged ok, so return
ORRS PC, R12, #V_bit
; *****************************************************************************
;
; SetC1C0 - Set clock and data lines to values in R1 and R0 respectively
;
; out: Trashes r0,r1,r2,r11
;
ts_SetC1C0 ROUT
MOV R11, R14
BIC R14, R14, #Z_bit ; indicate not checking clock
ts_SetOrCheck
ORR R14, R14, #I_bit ; disable interrupts
TEQP R14, #0
ADD R0, R0, R1, LSL #1 ; R0 := C0 + C1*2
ORR R0, R0, #&C0 ; make sure two test bits are
; always set to 1 !
MOV R2, #IOC
STRB R0, [R2, #IOCControl]
10
LDREQB R1, [R2, #IOCControl] ; wait for clock
TSTEQ R1, #i2c_clock_bit ; to read high
BEQ %BT10
MOV R0, #10 ; delay for >= 10/2 microsecs
;
; in-line do-micro-delay to save a stack level
;
STRB R0, [R2, #Timer0LR] ; copy counter into output latch
LDRB R1, [R2, #Timer0CL] ; R1 := low output latch
20
STRB R0, [R2, #Timer0LR] ; copy counter into output latch
LDRB R14, [R2, #Timer0CL] ; R14 := low output latch
TEQ R14, R1 ; unchanged ?
MOVNE R1, R14 ; copy anyway
BEQ %BT20 ; then loop
SUBS R0, R0, #1 ; decrement count
BNE %BT20 ; loop if not finished
;
; end do-micro-delay
;
MOV PC, R11
; Set clock and data lines to R1 and R0 and then wait for clock to be high
ts_SetC1C0CheckClock ROUT
MOV R11, R14
ORR R14, R14, #Z_bit ; indicate checking clock
B ts_SetOrCheck
; *****************************************************************************
;
; ClockData - Clock a bit of data down the IIC bus
;
; in: R0 = data bit
;
; out: Trashes r0,r1,r2,r3,r10,r11
;
ts_ClockData ROUT
MOV R10,R14
MOV R3, R0 ; save data
MOV R1, #0 ; clock LO
BL ts_SetC1C0
MOV R1, #1 ; clock HI
MOV R0, R3
BL ts_SetC1C0CheckClock
; Delay here must be >= 4.0 microsecs
MOV R1, #0 ; clock LO
MOV R0, R3
BL ts_SetC1C0
MOV PC,R10
; *****************************************************************************
;
; Start - Send the Start signal
;
; out: Trashes r0,r1,r2,r9,r11
; R0 (and Z flag) indicates state of clock .. should be NZ.
;
ts_Start ROUT
MOV R9,R14
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
BL ts_SetC1C0
; Delay here must be >= 4.0 microsecs
MOV R0, #0 ; clock HI, data LO
MOV R1, #1
BL ts_SetC1C0
; Make sure clock really is high (and not shorted to gnd)
LDRB R3, [R2, #IOCControl]
; Delay here must be >= 4.7 microsecs
MOV R0, #0 ; clock LO, data LO
MOV R1, #0
BL ts_SetC1C0
ANDS R0, R3, #i2c_clock_bit
MOV PC,R9
; *****************************************************************************
;
; Acknowledge - Check acknowledge after transmitting a byte
;
; out: Trashes r0,r1,r2,r3,r9,r11
; V=0 => acknowledge received
; V=1 => no acknowledge received
;
ts_Acknowledge ROUT
MOV R9,R14
MOV R0, #1 ; clock LO, data HI
MOV R1, #0
BL ts_SetC1C0
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
BL ts_SetC1C0CheckClock
; Delay here must be >= 4.0 microsecs
MOV R2, #IOC
LDRB R3, [R2, #IOCControl] ; get the data from IOC
MOV R0, #1 ; clock LO, data HI
MOV R1, #0
BL ts_SetC1C0
TST R3, #1 ; should be LO for correct acknowledge
MOV R3, PC
BICEQ R3, R3, #V_bit ; clear V if correct acknowledge
ORRNE R3, R3, #V_bit ; set V if no acknowledge
TEQP R3, #0
MOV PC,R9
; *****************************************************************************
;
; Stop - Send the Stop signal
;
; out: Trashes r0,r1,r2,r9,r11
;
ts_Stop ROUT
MOV R9,R14
MOV R0, #0 ; clock HI, data LO
MOV R1, #1
BL ts_SetC1C0
; Delay here must be >= 4.0 microsecs
MOV R0, #1 ; clock HI, data HI
MOV R1, #1
BL ts_SetC1C0
MOV PC,R9
; *****************************************************************************
;
; TXByte - Transmit a byte
;
; in: R0 = byte to be transmitted
;
; out: Trashes r0,r1,r2,r3,r4,r5,r9,r10,r11
;
ts_TXByte ROUT
MOV R9, R14
MOV R4, R0 ; byte goes into R4
MOV R5, #&80 ; 2^7 the bit mask
10
ANDS R0, R4, R5 ; zero if bit is zero
MOVNE R0, #1
BL ts_ClockData ; send the bit
MOVS R5, R5, LSR #1
BNE %BT10
MOV PC, R9
; *****************************************************************************
;
; RXByte - Receive a byte
;
; out: R0 = byte received
; Trashes r1,r2,r3,r4,r9,r11
;
ts_RXByte ROUT
MOV R9, R14
MOV R3, #0 ; byte:=0
MOV R2, #IOC
MOV R4, #7
MOV R0, #1 ; clock LO, data HI
MOV R1, #0
BL ts_SetC1C0
10
MOV R0, #1 ; pulse clock HI
MOV R1, #1
BL ts_SetC1C0CheckClock
LDRB R1, [R2, #IOCControl] ; get the data from IOC
AND R1, R1, #1
ADD R3, R1, R3, LSL #1 ; byte:=byte*2+(IOC?0)AND1
MOV R0, #1 ; return clock LO
MOV R1, #0
BL ts_SetC1C0
SUBS R4, R4, #1
BCS %BT10
MOV R0, R3 ; return the result in R0
MOV PC, R9
LTORG
END
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; > TestSrc.IOC
TTL RISC OS 2+ POST IO controller
;
; This initial IOC test simply reports the content of the IRQ and FIRQ
; registers, to show any unexpected pending IRQs.
; Certain of these should really be cleared, and the effect of an
; interrupt tested.
;
;------------------------------------------------------------------------
; History
;
; Date Name Comment
; ---- ---- -------
; 18-Dec-89 ArtG Initial version
; 29-Nov-91 ArtG Added IOC bus test using mask registers
; 20-Jun-93 ArtG Modified for 29-bit IOMD test
;
;
;------------------------------------------------------------------------
[ IO_Type = "IOMD"
ts_IObase * IOMD_Base
ts_IOmask * &1fffffff
ts_IOreg1 * IOMD_VIDCUR
ts_IOreg2 * IOMD_VIDSTART
ts_IObswap * 32
ts_IOMD_ID * &D4E7
|
ts_IObase * IOC
ts_IOmask * &ff0000
ts_IOreg1 * IOCIRQMSKA
ts_IOreg2 * IOCIRQMSKB
ts_IObswap * 16
]
ts_IOCreg
MOV r0,#0 ; zero error accumulator
LDR r3, =ts_IObase
MOV r1,#(1 :SHL: 31) ; initialise bit-set test mask
0
MVN r2,r1 ; make bit-clear test mask
ANDS r4,r1,#ts_IOmask
BEQ %FT1 ; skip if this bit isn't tested
STR r1,[r3,#ts_IOreg1]
STR r2,[r3,#ts_IOreg2]
LDR r4,[r3,#ts_IOreg1]
; EOR r4, r4, r1, LSR #ts_IObswap ; check bit-set test was OK
EOR r4, r4, r1 ; check bit-set test was OK
ORR r0, r0, r4 ; accumulate errors in r0
LDR r4,[r3,#ts_IOreg2]
; EOR r4, r4, r2, LSR #ts_IObswap ; check bit-clear test was OK
EOR r4, r4, r2 ; check bit-clear test was OK
ORR r0, r0, r4 ; accumulate errors in r0
1
MOV r1, r1, LSR #1 ; shift mask downwards
TEQ r1,#0
BNE %BT0 ; and loop until all bits tested
ANDS r8, r0, #ts_IOmask
MOV pc,r14 ; return error if any bit failed
ts_IOCstat
LDR r3, =ts_IObase
MOV r0,#0
[ IO_Type = "IOMD"
LDRB r1,[r3,#IOMD_ID1]
ORR r0,r0,r1, LSL #(32-24)
LDRB r1,[r3,#IOMD_ID0]
ORR r0,r0,r1
LDR r1,=ts_IOMD_ID
CMPS r0,r1 ; check IOMD identity
MOV r0,r0,LSL #16
LDRB r1,[r3,#IOMD_VERSION]
ORR r8,r0,r1, LSL #12
MOV pc,r14
|
LDRB r1,[r3,#IOCControl]
ORR r0,r0,r1, LSL #(32 - 8)
LDRB r1,[r3,#IOCIRQSTAA]
ORR r0,r0,r1, LSL #(32 - 16)
LDRB r1,[r3,#IOCIRQSTAB]
ORR r0,r0,r1, LSL #(32 - 24)
LDRB r1,[r3,#IOCFIQSTA]
ORR r8,r0,r1
ANDS r1,r1,#0 ; return zero flag (OK)
MOV pc,r14
]
END
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;> RomCheck
;
; RISC OS 2+ BOOT TEST SOFTWARE
; MEMORY TEST 3 VERSION A.
; BRIAN RICE 01-11-89
; 24.04.90 0.10 ArtG Added ROM size test
; 15.05.90 1.00 ArtG Changed to put checksum at (end - 2 words)
; 17.05.90 1.01 ArtG Changed to get ROM length from vectot table
;
;
; This file will perform quick checksum test on the OS ROMS.
;
;
; The test code for this test is a simple additive checksum routine.
; The software will read eight words from ROM then add the contents from ROM
; to a register. When the test is complete the contents of the checksum
; register is checked by adding the final word in ROM - this should give
; zero.
; The program will be run from ROM, at slowest speed.
;
; All except the last two words are checksummed : these hold the numbers
; that cause each individual ROM to CRC to zero, so they can't simultaneously
; be included in an all-zero additive checksum.
ts_CRCsize * (2 * 4)
;
;
;r0 IS A POINTER TO THE LOCATIONS IN MEMORY.
;r1 HAS THE CALCULATED CHECKSUM.
;r2 HOLDS A COUNTER INDICATION HOW MANY WORDS ARE LEFT TO GET
;r3 is a temporary variable
;r4 TO r11 ARE USED TO LOAD THE CONTENTS OF 8 LOCATIONS FROM THE ROM.
;
ROUT
ts_ROM_checksum
MOV r1, #&00 ; initialise accumulator
LDR r0, =PhysROM ; initialise pointer
LDR r2, [r0, #ts_ROMSIZE] ; initialise endstop
ADD r2, r2, r0 ; - must be at least 8 words
SUB r2, r2, #(10 * 4) ; below the real endpoint
loop1 LDMIA r0!, {r4 - r11} ;LOAD r4 TO r11 WITH THE CONTENTS
;OF LOCATIONS POINTED TO BY r0
;WHICH IS INCREMEMTED AUTOMATICALLY
;TO POINT TO THE NEXT LOCATION
01
ADD r1, r1, r4 ;ADD r4 TO CHECKSUM
ADD r1, r1, r5 ;ADD r5 TO CHECKSUM
ADD r1, r1, r6 ;ADD r6 TO CHECKSUM
ADD r1, r1, r7 ;ADD r7 TO CHECKSUM
ADD r1, r1, r8 ;ADD r8 TO CHECKSUM
ADD r1, r1, r9 ;ADD r9 TO CHECKSUM
ADD r1, r1, r10 ;ADD r10 TO CHECKSUM
ADD r1, r1, r11 ;ADD r11 TO CHECKSUM
02
ASSERT ((%02 - %01) = 32) ; else r2 won't count down correctly
CMPS r0, r2
BCC loop1 ;loop until pointer reaches endstop
LDMIA r0!, {r4 - r9} ; get last 6 words (miss last 2 in ROM)
03
ADD r1, r1, r4 ;ADD r4 TO CHECKSUM
ADD r1, r1, r5 ;ADD r5 TO CHECKSUM
ADD r1, r1, r6 ;ADD r6 TO CHECKSUM
ADD r1, r1, r7 ;ADD r7 TO CHECKSUM
ADD r1, r1, r8 ;ADD r8 TO CHECKSUM
ADD r1, r1, r9 ;ADD r9 TO CHECKSUM
04
ASSERT (((%04 - %03) + (2*4)) = 32) ; Change this if you like -
; but be careful to count nearly
; to the top in eights, then add
; add in the last few words.
MOVS r0,r1 ; should be zero if all OK
MOV pc,r14 ;return with zero flag set on OK
;and the calculated sum in r0.
;
; ROM alias check.
; This test looks for an aliased copy of the vector table at varying
; distances from the start of ROM space.
; 16K is fairly arbitrary but corresponds approximately with the size of
; the POST. If there's an alias below that, we've probably already crashed !
;
; This test is only called if the checksum fails, in order to indicate a
; possible high ROM address line failure.
ts_ROM_alias ROUT
MOV r0,#PhysROM ; get some words from ROM start
LDR r3,[r0, #ts_ROMSIZE] ; get the ROM length word
LDMIA r0,{r4,r5,r6,r7}
MOV r1,#(16 * 1024)
01 ADD r2,r0,r1 ; get some words from possible alias
LDMIA r2,{r8,r9,r10,r11}
CMPS r4,r8
CMPNE r5,r9
CMPNE r6,r10
CMPNE r7,r11
BEQ %10 ; aliased : found MS ROM address bit
MOVS r1, r1, LSL #1 ; test the next (more significant) bit
CMPS r1, r3 ; reached the limit yet ?
BLT %01 ; no - try again.
10 MOV r0,r1 ; reached the end, or an alias.
MOV pc,lr
LTORG
END
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; > TestMain
; Main assembly file for isolated assembly of machine test software
MEMCADR * &3600000
ROM * &3800000
[ MEMC_Type = "IOMD"
VideoPhysRam * &02000000 ; Amazing - it's in the same place!
DRAM0PhysRam * &10000000 ; 4 DRAM banks
DRAM1PhysRam * &14000000
DRAM2PhysRam * &18000000
DRAM3PhysRam * &1C000000
DRAMBaseAddressMask * &1C000000 ; used to mask off bits after stealing video RAM
PhysSpaceSize * &20000000 ; IOMD physical map is 512M big
PhysROM * &00000000 ; and real ROM starts at 0
SAMLength * 512*4 ; SAM length in bytes for 1 bank of VRAM
EASISpacePhys * &08000000
EASISpace * PhysSpace + EASISpacePhys
|
VideoPhysRam * &02000000
PhysSpaceSize * &04000000 ; MEMC1 physical map is 64M big
PhysROM * &03800000
PhysRamPhys * &02000000 ; physical space starts here
]
ORG ROM
GET TestSrc/Begin
CONT
ADRL r2,TestVIDCTAB
LDR r0,=IOMD_MonitorType
LDR r0,[r0]
ANDS r0,r0,#IOMD_MonitorIDMask
ADDEQ r2,r2,#(TestVVIDCTAB-TestVIDCTAB)
MOV r0,#ts_VIDCPhys
08 LDR r1, [r2],#4
CMP r1, #-1
STRNE r1, [r0]
BNE %BT08
MOV r9,#0
10
ORR r9,r9,#&40000000
STR r9,[r0] ; write the border colour
ADD r9,r9,#&00000005
ADD r9,r9,#&00000300
ADD r9,r9,#&00010000
AND r9,r9,#&00ffffff
MOV r1,#&10000
12 ADDS r1,r1,#(-1)
BNE %BT12
B %BT10
;
; The RISC-OS MEMC setup code is re-used to ensure similar
; detection of memory configuration. The MEMC1 code is modified only
; to remove an unnecessary function.
GBLL Module
Module SETL {FALSE}
GBLL AssembleSAtest
AssembleSAtest SETL {FALSE}
DynAreaFlags_DoublyMapped * 1 :SHL: 6
DynAreaFlags_NotCacheable * 1 :SHL: 5
DynAreaFlags_NotBufferable * 1 :SHL: 4
DynAreaFlags_APBits * 15 :SHL: 0 ; currently onl
END
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