Fix IIC bus information being wiped by RAM clear

Detail:
  hdr/KernelWS - Enlarge the SkippedTables area to encompass IICBus_Base
  s/PMF/IIC - Manually set IICBus_Status of each bus to 0 within IICInit
Admin:
  Bug was introduced in Kernel-5_35-4_79_2_168 when IIC initialisation was moved to earlier in the ROM init sequence, but has gone unnoticed due to it only really affecting the high-level API (and none of the relevant HALs were relying on the kernel for the RAM clear)
  Tested on BB-xM with kernel RAM clear


Version 5.35, 4.79.2.236. Tagged as 'Kernel-5_35-4_79_2_236'

VersionASM

@@ -13,11 +13,11 @@
                         GBLS    Module_ComponentPath
 Module_MajorVersion     SETS    "5.35"
 Module_Version          SETA    535
-Module_MinorVersion     SETS    "4.79.2.235"
-Module_Date             SETS    "29 Aug 2014"
-Module_ApplicationDate  SETS    "29-Aug-14"
+Module_MinorVersion     SETS    "4.79.2.236"
+Module_Date             SETS    "15 Sep 2014"
+Module_ApplicationDate  SETS    "15-Sep-14"
 Module_ComponentName    SETS    "Kernel"
 Module_ComponentPath    SETS    "castle/RiscOS/Sources/Kernel"
-Module_FullVersion      SETS    "5.35 (4.79.2.235)"
-Module_HelpVersion      SETS    "5.35 (29 Aug 2014) 4.79.2.235"
+Module_FullVersion      SETS    "5.35 (4.79.2.236)"
+Module_HelpVersion      SETS    "5.35 (15 Sep 2014) 4.79.2.236"
                         END

VersionNum

@@ -5,19 +5,19 @@
  *
  */
 #define Module_MajorVersion_CMHG        5.35
-#define Module_MinorVersion_CMHG        4.79.2.235
-#define Module_Date_CMHG                29 Aug 2014
+#define Module_MinorVersion_CMHG        4.79.2.236
+#define Module_Date_CMHG                15 Sep 2014
 
 #define Module_MajorVersion             "5.35"
 #define Module_Version                  535
-#define Module_MinorVersion             "4.79.2.235"
-#define Module_Date                     "29 Aug 2014"
+#define Module_MinorVersion             "4.79.2.236"
+#define Module_Date                     "15 Sep 2014"
 
-#define Module_ApplicationDate          "29-Aug-14"
+#define Module_ApplicationDate          "15-Sep-14"
 
 #define Module_ComponentName            "Kernel"
 #define Module_ComponentPath            "castle/RiscOS/Sources/Kernel"
 
-#define Module_FullVersion              "5.35 (4.79.2.235)"
-#define Module_HelpVersion              "5.35 (29 Aug 2014) 4.79.2.235"
+#define Module_FullVersion              "5.35 (4.79.2.236)"
+#define Module_HelpVersion              "5.35 (15 Sep 2014) 4.79.2.236"
 #define Module_LibraryVersionInfo       "5:35"

hdr/KernelWS

@@ -1244,9 +1244,6 @@ Cache_Lx_ITable                   #       4*7     ; Instruction cache layout for
 IOAllocPtr      #       4               ; current lowpoint of mapped I/O space (also upper limit on DAs)
 IOAllocLimit    #       4               ; current lowest allowed I/O space (DA creation may move this up)
 
-                AlignSpace 32   ; skipped bit must end on 32-byte boundary (due to speedup)
-SkippedTablesEnd #      0
-
 
   [ :DEF: ShowWS
         ! 0, "Free space before DebuggerSpace = ":CC::STR:(&300-@)
@@ -1255,6 +1252,10 @@ SkippedTablesEnd #      0
         ASSERT  @ <= &300
                         #       (&300-@)
  [ :LNOT: HiProcVecs
+; Note that this is currently located within the skipped region, even though it
+; doesn't need to be. It was just an easy way of adding the IIC bus info to the
+; region. The debugger will initialise DebuggerSpace on startup, so it doesn't
+; matter that it doesn't get cleared during the main RAM clear.
 DebuggerSpace           #       16*8    ; Debugger module needs some zero page
 DebuggerSpace_Size      *       ?DebuggerSpace
 
@@ -1265,6 +1266,12 @@ DebuggerSpace           *       &2000   ; Debugger gets a page all to itself!
 DebuggerSpace_Size      *       &1000
  ]
 
+IICBus_Count       *    4 ; 4 busses is enough for all current machines
+IICBus_Base        #    IICBus_Size*IICBus_Count
+
+                AlignSpace 32   ; skipped bit must end on 32-byte boundary (due to speedup)
+SkippedTablesEnd #      0
+
 ; NVRAM support
 
 NVRamSize          #    1               ; Size of NVRam (E2ROM & CMOS) fitted in 256byte units
@@ -1275,8 +1282,6 @@ NVRamWriteSize     #    1               ; Size of writable region (256byte units
 
                    AlignSpace
 
-IICBus_Count       *    4 ; 4 busses is enough for all current machines
-IICBus_Base        #    IICBus_Size*IICBus_Count
 
 AppSpaceDANode     #    DANode_NodeSize ; Dummy area node for application space (not on list)
 FreePoolDANode     #    DANode_NodeSize ; Area node for free pool

s/PMF/IIC

@@ -954,6 +954,8 @@ IICInit
         CMP     R7, R0
         Pull    "R7-R9,R14",HS
         BHS     IICAbort ; Ensure any CMOS operation aborted
+        MOV     a1, #0
+        STR     a1, [R8, #IICBus_Status]
         MOV     a1, R7
         CallHAL HAL_IICType
         STR     a1, [R8, #IICBus_Type]