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Commit 119585a5 authored by Jeffrey Lee's avatar Jeffrey Lee
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Minor MMU_ChangingEntries_WB_CR7_Lx fix 

Detail:
  s/ARMops - previous version of MMU_ChangingEntries_WB_CR7_Lx would behave improperly if cleaning the last page of the address map by neglecting to flush any more than one TLB entry
Admin:
  Untested!


Version 5.35, 4.79.2.98.2.28. Tagged as 'Kernel-5_35-4_79_2_98_2_28'
parent de8e610e
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Showing with 8 additions and 8 deletions
VersionASM
View file @ 119585a5
......@@ -13,11 +13,11 @@
GBLS Module_ComponentPath
Module_MajorVersion SETS "5.35"
Module_Version SETA 535
Module_MinorVersion SETS "4.79.2.98.2.27"
Module_MinorVersion SETS "4.79.2.98.2.28"
Module_Date SETS "23 Jun 2010"
Module_ApplicationDate SETS "23-Jun-10"
Module_ComponentName SETS "Kernel"
Module_ComponentPath SETS "castle/RiscOS/Sources/Kernel"
Module_FullVersion SETS "5.35 (4.79.2.98.2.27)"
Module_HelpVersion SETS "5.35 (23 Jun 2010) 4.79.2.98.2.27"
Module_FullVersion SETS "5.35 (4.79.2.98.2.28)"
Module_HelpVersion SETS "5.35 (23 Jun 2010) 4.79.2.98.2.28"
END
VersionNum
View file @ 119585a5
......@@ -5,12 +5,12 @@
*
*/
#define Module_MajorVersion_CMHG 5.35
#define Module_MinorVersion_CMHG 4.79.2.98.2.27
#define Module_MinorVersion_CMHG 4.79.2.98.2.28
#define Module_Date_CMHG 23 Jun 2010
#define Module_MajorVersion "5.35"
#define Module_Version 535
#define Module_MinorVersion "4.79.2.98.2.27"
#define Module_MinorVersion "4.79.2.98.2.28"
#define Module_Date "23 Jun 2010"
#define Module_ApplicationDate "23-Jun-10"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "Kernel"
#define Module_ComponentPath "castle/RiscOS/Sources/Kernel"
#define Module_FullVersion "5.35 (4.79.2.98.2.27)"
#define Module_HelpVersion "5.35 (23 Jun 2010) 4.79.2.98.2.27"
#define Module_FullVersion "5.35 (4.79.2.98.2.28)"
#define Module_HelpVersion "5.35 (23 Jun 2010) 4.79.2.98.2.28"
#define Module_LibraryVersionInfo "5:35"
s/ARMops
View file @ 119585a5
......@@ -2183,7 +2183,7 @@ MMU_ChangingEntries_WB_CR7_Lx ROUT
MCR p15, 0, lr, c8, c7, 1 ; invalidate DTLB & ITLB entry
ADD lr, lr, #PageSize
CMP lr, a2
BLO %BT20
BNE %BT20
MCR p15, 0, a1, c7, c5, 6 ; invalidate branch predictors
myDSB
myISB
......
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