- 16 Mar, 2020 1 commit
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ROOL authored
* Better document the history of ErrorBase_AbortRegions * Define OS_Pointer reason codes + missing PointerV code Version 2.89. Tagged as 'HdrSrc-2_89'
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- 25 Feb, 2020 1 commit
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ROOL authored
Error allocations, including retrospective allocations for some errors used in RISC OS 6. Version 2.88. Tagged as 'HdrSrc-2_88'
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- 23 Jan, 2020 1 commit
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Ben Avison authored
Extra service calls for long descriptor page table support Version 2.87. Tagged as 'HdrSrc-2_87'
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- 16 Nov, 2019 1 commit
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Jeffrey Lee authored
Version 2.86. Tagged as 'HdrSrc-2_86'
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- 09 Nov, 2019 1 commit
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Timothy E Baldwin authored
Version 2.85. Tagged as 'HdrSrc-2_85'
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- 02 Nov, 2019 1 commit
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Jeffrey Lee authored
Version 2.84. Tagged as 'HdrSrc-2_84'
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- 12 Oct, 2019 1 commit
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Ben Avison authored
Macros in this header file had inconsistent capitalisation. This is a legacy of the earliest macros being `ENTRY` and `EXIT`. Macro names that are all uppercase or all lowercase are a bad idea, because they can clash with opcodes or assembler directives that are added at a later date: this is what happened with `ENTRY` when objasm was developed, hence the introduction of the identical `Entry` macro, and mass renaming across the source tree was required when it switched to using objasm. The other downside of all-uppercase or all-lowercase macro names is that it makes it impossible to design a syntax colouring algorithm that is forward compatible with new opcodes (and ARM continues to add new opcodes with almost every new minor revision of the architecture). Note that related macro names depend on the vintage of the header at which they were introduced: compare `ALTENTRY` with `EntryS`. Additional mixed-case versions of macros `ALTENTRY`, `EXIT`, `EXITS`, `EXITV`, `EXITVC`, `EXITVS`, `FRAMLDR` and `FRAMSTR` are hereby introduced. The old macro names are also retained (it would be a very large job to substitute them throughout the source tree) but at least new code can now consistently use mixed case. The `FRAMCOM` and `FRAMSPL` macros are for internal use of the header file, so uppercase versions of these did not need to be retained. Also: * Delete `ENTRY` macro: it's a long time since anything has been buildable using aasm, which is the only assembler that accepts this macro * Correct cut-and-paste errors in the messages `ExitVC without EntryS` and `ExitVS without EntryS` Version 2.83. Tagged as 'HdrSrc-2_83'
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- 08 Oct, 2019 1 commit
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Ben Avison authored
Add public filetype for JSON files Version 2.82. Tagged as 'HdrSrc-2_82'
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- 12 Sep, 2019 1 commit
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Ben Avison authored
* SWI chunk for the CompressPNG module * Wimp message structure definitions Version 2.81. Tagged as 'HdrSrc-2_81'
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- 19 Aug, 2019 1 commit
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Ben Avison authored
Some later XScales also supported supersections - albeit ones we don't support yet - but they mean it's not incorrect to include these definitions in this header. However, defining the bits now means that we don't need to insert MEMM_Type build-time switches into the kernel for the page table code that now handles supersections. Version 2.80. Tagged as 'HdrSrc-2_80'
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- 15 Jul, 2019 1 commit
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Ben Avison authored
Version 2.79. Tagged as 'HdrSrc-2_79'
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- 23 Jun, 2019 1 commit
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Ben Avison authored
Detail: The memory barriers ISB, DSB & DMB were intially introduced in ARMv6 as CP15 operations, however they were replaced at ARMv7 with dedicated instructions and the old CP15 encodings deprecated. Since ARMv7VE was introduced, some CPUs can be configured to make the CP15 encodings undefined instructions. For unconfigurable CPUs, the CP15 encodings are always enabled, but for others, we need to set this bit in SCTLR. Note, this sort of behaviour usually implies ARM intend on removing these instructions in a future architecture, so we might need to plan for this eventuality. Version 2.78. Tagged as 'HdrSrc-2_78'
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- 30 May, 2018 1 commit
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Ben Avison authored
Video overlay allocations, and a correction to ErrorBase_SMP Version 2.77. Tagged as 'HdrSrc-2_77'
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- 27 Apr, 2018 1 commit
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Ben Avison authored
Version 2.76. Tagged as 'HdrSrc-2_76'
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- 15 Apr, 2018 1 commit
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Ben Avison authored
Version 2.75. Tagged as 'HdrSrc-2_75'
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- 12 Apr, 2018 1 commit
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Ben Avison authored
Detail: HdrSrc is such an unusual component that the only shared makefile fragment it uses is StdTools. Almost every line requires edits to accommodate the differences between amu and GNU make, so for clarity we use separate makefiles for the two tools. Admin: I'd forgotten that I'd created the XCompile branch a few years back until just now! I think this is a superior solution because it confines the changes to a single file, at least in the short-term. Version 2.74. Tagged as 'HdrSrc-2_74'
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- 26 Jan, 2018 1 commit
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Jeffrey Lee authored
Detail: * Neither of our native Cortex-A9 machines natively support 16 colour modes, so HiResTTX must be used since the kernel only supports >16 colour TTX when that option is on. * Our Cortex-A8 machines can do 16 colours, but we might as well switch them to HiResTTX as well since they've got plenty of horsepower to render it at that resolution. * That just leaves IOMD as the odd one out using low-res TTX. If hardware scrolling or VDU 23,18,1 is used then performance of hi-res TTX doesn't seem to be that much worse than low-res, so for consistency it's probably best to take the performance hit and run all platforms with HiResTTX. hdr/Machine/Machine - Updated as above. Also use TTX256 for Cortex-A9 so that the "native" mode 7 will be 256 colour instaed of 16 colour. Admin: Tested on Pandaboard, iMX6, BB-xM, StrongARM RiscPC Fixes lack of teletext on Pandaboard + iMX6 Version 2.73. Tagged as 'HdrSrc-2...
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- 25 Jul, 2017 1 commit
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Ben Avison authored
Version 2.72. Tagged as 'HdrSrc-2_72'
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- 07 Jun, 2017 1 commit
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Ben Avison authored
Version 2.71. Tagged as 'HdrSrc-2_71'
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- 29 Dec, 2016 1 commit
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Ben Avison authored
Detail: Additional error and service call definitions requested by Sprow Version 2.70. Tagged as 'HdrSrc-2_70'
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- 02 Aug, 2016 1 commit
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Jeffrey Lee authored
Detail: hdr/MEMM/VMSAv6 - Add AP_PROM for the "privileged mode ROM" permission. Define the shareable bit for L1 page table entries. Admin: Tested on Raspberry Pi Version 2.69. Tagged as 'HdrSrc-2_69'
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- 01 Aug, 2016 1 commit
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Ben Avison authored
Detail: Additional kernel error numbers for Jeffrey Lee Version 2.68. Tagged as 'HdrSrc-2_68'
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- 03 Jul, 2016 1 commit
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Ben Avison authored
Version 2.67. Tagged as 'HdrSrc-2_67'
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- 18 Jun, 2016 1 commit
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Jeffrey Lee authored
Detail: hdr/CPU/Generic32 - Copy-paste error led to wrong variable name in a conditional block Admin: Tested on Raspberry Pi, Iyonix Version 2.66. Tagged as 'HdrSrc-2_66'
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- 12 Jun, 2016 1 commit
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Jeffrey Lee authored
Detail: Many of our existing PSR manipulation macros (specifically, ones used for changing mode or controlling interrupts) are based around the code sequences you'd typically use on a 26bit system. Although this has worked well in terms of producing a 32bit version of the OS, it's also left us with macros that can be sub-optimal for 32bit machines, or are inconvenient to use due to the potential of corrupting other PSR flags This change adds a new set of macros which are designed and optimised for 32bit-only targets, but can still fall back to 26/32bit neutral or 26bit-only configurations hdr/CPU/Generic32: - Add the new macros (SEI, CLI, SetModeSEI, SetModeCLI & variants). - Improve existing SetMode macro to add 26bit compatibility, and to add an extra optimisation for pre-ARMv6 (emit single MSR if IRQ state is known) - Improve SCPSR to allow the source mode to be any 32bit mode - Fix conditional 26bit/32bit neutral SCPSR - the 32bit check TEQ corrupts NZCV so we can't do conditional execution on $cond after it (and we've already branched on the opposite condition anyway) - Fix 26bit/32bit neutral SCPSR to preserve NZCV when following the MSR code path - Make CLRPSR and SETPSR just call through to SCPSR - in terms of output the first two have no advantages over SCPSR - Update WritePSRc documentation to reflect that it can now be used in any (non-USR) source mode hdr/CPU/Generic26: - Update WritePSRc documentation to match Generic32 Admin: Tested on Raspberry Pi Output of new macros manually checked for various machine types (RPi, Tungsten, All, 26) Version 2.65. Tagged as 'HdrSrc-2_65'
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- 05 Jun, 2016 1 commit
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Steve Revill authored
MODE 7 doesn't really work because the DVI framer chip can't clock as low as 13.5MHz for 320x200. Version 2.64. Tagged as 'HdrSrc-2_64'
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- 28 May, 2016 1 commit
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Jeffrey Lee authored
Detail: hdr/Machine/26, hdr/Machine/Machine - Add new "26" machine type, which targets all 26 bit machines/OS versions (running only in 26 bit mode) hdr/CPU/Arch - Use ELIF to avoid bracket spam. Remove duplicate CortexA7 case. hdr/CPU/Generic26 - Add NOPs to PSR manipulation macros in order to make them ARM2-safe (Generic32 macros are already structured to have suitable NOPs when generating 32bit-neutral code, so it makes sense for Generic26 to take care of ARM2 as well). This removes the need for components which use these macros to insert any manual NOPs, whether for the StrongARM MSR bug or the ARM2 TEQP bug. hdr/CPU/Generic32 - Flag the StrongARM MSR NOP diagnostic message as a warning, so the line number can be included in the output, so developers can more easily investigate the issue. Admin: Tested with PlingSystem build Version 2.63. Tagged as 'HdrSrc-2_63'
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- 09 May, 2016 1 commit
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Jeffrey Lee authored
Detail: hdr/Macros - Remove GET of Hdr:CPU.Arch that was added in HdrSrc 2.61. Closer inspection of the OS sources suggest that only a handful of files were affected by the DivRem breakage, so to avoid HdrSrc turning into a tangled mess of headers that all include each other it's been decided that it's better to stick with the status quo and require users of Hdr:Macros to include Hdr:CPU.Arch as and when necessary (99% of the time Hdr:System will have already pulled it in). Admin: Tested on Raspberry Pi Version 2.62. Tagged as 'HdrSrc-2_62'
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- 08 May, 2016 2 commits
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Jeffrey Lee authored
Detail: hdr/Macros - Several macros now depend on Hdr:CPU.Arch, and it's reasonable to assume more architecture-specific optimisations will be made in future, so make sure we GET that header if necessary Admin: Tested on Raspberry Pi Fixes issues building components that GET Hdr:Macros but not Hdr:CPU.Arch, e.g. DivRem usage in several HALs Version 2.61. Tagged as 'HdrSrc-2_61'
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Jeffrey Lee authored
Detail: hdr/Macros - DivRem is now able to use UDIV when building for architectures that support it. A "norem" option is also available, to allow the remainder calculation to be skipped if it's not needed (since we don't get it for free when using UDIV). hdr/CPU/Generic32 - PHPSEI, WritePSRc and SetMode now use the ARMv6 CPS instruction where possible, delivering performance gains compared to the equivalent MSR. Where CPS isn't used, WritePSRc now attempts to emit a single MSR instead of the 4 instructions generated by the SCPSR macro. Admin: Tested on Cortex-A15 PSR manipulation macros trialed on a few different CPU architectures to arrive at the conclusion that CPS is as good or better than MSR Version 2.60. Tagged as 'HdrSrc-2_60'
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- 04 Apr, 2016 1 commit
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Ben Avison authored
Version 2.59. Tagged as 'HdrSrc-2_59'
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- 29 Feb, 2016 1 commit
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Ben Avison authored
* ARMv7VE (virtualisation extension) * ARMv8 * ARMv8 cryptographic extension Machine=RPi builds now targets ARMv8 as well as ARMv6 and ARMv7; Machine=CortexA7 builds now set the VE flag; and All and All32 include ARMv8. Version 2.58. Tagged as 'HdrSrc-2_58'
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- 29 Nov, 2015 1 commit
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Ben Avison authored
Detail: A couple of new error allocations for the sound subsystem Version 2.57. Tagged as 'HdrSrc-2_57'
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- 08 Nov, 2015 3 commits
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Ben Avison authored
Detail: This is the mode used for hypervisor exceptions in ARMv7VE and later. Version 2.56. Tagged as 'HdrSrc-2_56'
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Ben Avison authored
Detail: * Decloak ATA switcher error base Retagged as 'HdrSrc-2_55' Version 2.55. Not tagged
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Ben Avison authored
Detail: * Complete the Cortex-A7 support which was initially added for RPi 2, to allow for builds that only target Cortex-A7. Because Cortex-A15 and Cortex-A17 CPUs are indistinguishable architecturally from Cortex-A7 (all are ARMv7VE with VFPv4, Advanced SIMD v2 and hardware integer divide) any such platforms are expected to use Machine=CortexA7. Also bear in mind that if we ever support multiple cores on big.LITTLE CPUs, execution can move between these core types at runtime, making an assembly time option to distinguish between them meaningless! * Correct Machines All and All32 to include support for VFPv4 * Decloak the ATA driver SWI chunk * Add a global error allocation for use by the ATA subsystem (placed in global space because it propagates into the CD stack) Version 2.55. Tagged as 'HdrSrc-2_55'
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- 29 Sep, 2015 1 commit
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Ben Avison authored
Detail: Various allocations relating to SPIDriver and SATAFS made public Version 2.54. Tagged as 'HdrSrc-2_54'
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- 23 Aug, 2015 1 commit
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Ben Avison authored
Detail: Two extra kernel error numbers in NewErrors Updated comment in FSNumbers to state filing system prefix used by SDFS Version 2.53. Tagged as 'HdrSrc-2_53'
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- 05 Aug, 2015 1 commit
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Jeffrey Lee authored
Detail: hdr/MEMM/VMSAv6 - Remove XScale-specific L1_X, L2_X, L2L_X flags. Add L2_S flag. Add definitions for the cache size ID register fields. Admin: Tested on ARM11, Cortex-A7, -A8, -A9, -A15 Version 2.52. Tagged as 'HdrSrc-2_52'
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- 18 May, 2015 1 commit
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Ben Avison authored
Detail: * Filetype for MJPEG files * Extra AUN error * Resolved error base clash between AbortRegions and VFPSupport * New alias for OS_Byte 221 Version 2.51. Tagged as 'HdrSrc-2_51'
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