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Commit 7d4000d9 authored by Ben Avison's avatar Ben Avison
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Initial import of S3C6410 HAL 

Detail:
  The S3C6410 HAL is aimed at the Mini6410 board. There's a major bug
  somewhere which prevents the FP emulator from working (crashes on
  initialisation), and the interrupt handling is broken (which is believed to
  break USB). But video works (hardwired to 480x272), though the cursor hasn't
  been implemented yet, and the debugging console works.
Admin:
  Code submitted by Tom Walker

Version 0.01. Tagged as 'S3C6410-0_01'
parent 4829261e
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Showing with 3818 additions and 7 deletions
.gitattributes 0 → 100644
View file @ 7d4000d9
hdr/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
s/** gitlab-language=armasm linguist-language=armasm linguist-detectable=true
Makefile 0 → 100644
View file @ 7d4000d9
# Copyright 2011 Castle Technology Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Makefile for Kernel
#
# ***********************************
# *** C h a n g e L i s t ***
# ***********************************
# Date Name Description
# ---- ---- -----------
# 25-May-94 AMcC Created.
#
#
# Paths
#
EXP_HDR = <export$dir>
C_EXP_HDR = <cexport$dir>.Global.h
#
# Generic options:
#
MKDIR = mkdir -p
AS = aasm
ARMASM = objasm
CP = copy
RM = remove
CCFLAGS = -c -depend !Depend -IC:
ASFLAGS = -depend !Depend ${THROWBACK} -Stamp -quit -To $@ -From
ARMASMFLAGS = -depend !Depend -g -APCS 3/nofp/noswst ${THROWBACK}
CPFLAGS = ~cfr~v
TOKENISE = tokenise
TOKENS = Hdr:Tokens
#
# Program specific options:
#
COMPONENT = S3C6410
TARGET = bin.S3C6410
DBGTARGET = aif.S3C6410
GPATARGET = gpa.S3C6410
EXPORTS =
OBJECTS = o.Boot o.Interrupts o.Timers o.Video
# o.Video o.RTC
.s.o:; ${ARMASM} ${ARMASMFLAGS} $< $@
#
# Generic rules:
#
rom: ${TARGET}
@echo ${COMPONENT}: rom module built
debug: ${GPATARGET}
@echo ${COMPONENT}: debug module built
install_rom: ${TARGET}
${CP} ${TARGET} ${INSTDIR}.${COMPONENT} ${CPFLAGS}
@echo ${COMPONENT}: rom module installed
clean:
${RM} ROM
${RM} ${TARGET}
-Wipe o.* ~C~V
-Wipe aif.* ~C~V
-Wipe gpa.* ~C~V
@echo ${COMPONENT}: cleaned
export: ${EXPORTS}
@echo ${COMPONENT}: export complete
resources:
@echo ${COMPONENT}: nothing to do
${TARGET}: ${OBJECTS}
Link -bin -base 0xFC000000 -o $@ ${OBJECTS}
${DBGTARGET}: ${OBJECTS}
Link -bin -base 0xFC000000 -aif -d -o $@ ${OBJECTS}
${GPATARGET}: ${DBGTARGET}
ToGPA -s ${DBGTARGET} $@
# Dynamic dependencies:
MkClean,fd7 0 → 100644
View file @ 7d4000d9
| Copyright 2011 Castle Technology Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
amu_machine clean
MkRom,fd7 0 → 100644
View file @ 7d4000d9
| Copyright 2011 Castle Technology Ltd
|
| Licensed under the Apache License, Version 2.0 (the "License");
| you may not use this file except in compliance with the License.
| You may obtain a copy of the License at
|
| http://www.apache.org/licenses/LICENSE-2.0
|
| Unless required by applicable law or agreed to in writing, software
| distributed under the License is distributed on an "AS IS" BASIS,
| WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
| See the License for the specific language governing permissions and
| limitations under the License.
|
Dir <Obey$Dir>
time
amu_machine rom debug THROWBACK=-throwback
time
VersionNum
View file @ 7d4000d9
/* (0.00)
/* (0.01)
*
* This file is automatically maintained by srccommit, do not edit manually.
* Last processed by srccommit version: 1.1.
*
*/
#define Module_MajorVersion_CMHG 0.00
#define Module_MajorVersion_CMHG 0.01
#define Module_MinorVersion_CMHG
#define Module_Date_CMHG 03 Jun 2011
#define Module_MajorVersion "0.00"
#define Module_Version 0
#define Module_MajorVersion "0.01"
#define Module_Version 1
#define Module_MinorVersion ""
#define Module_Date "03 Jun 2011"
......@@ -18,6 +18,6 @@
#define Module_ComponentName "S3C6410"
#define Module_ComponentPath "castle/RiscOS/Sources/HAL/S3C6410"
#define Module_FullVersion "0.00"
#define Module_HelpVersion "0.00 (03 Jun 2011)"
#define Module_LibraryVersionInfo "0:0"
#define Module_FullVersion "0.01"
#define Module_HelpVersion "0.01 (03 Jun 2011)"
#define Module_LibraryVersionInfo "0:1"
hdr/StaticWS 0 → 100644
View file @ 7d4000d9
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
sb RN 9
^ 0,sb
OSheader # 4
OSentries # 4*(HighestOSEntry+1)
UART_Address # 4
CLK_Address # 4
Timer_Address # 4
INT_Address # 4
LCD_Address # 4
GPIO_Address # 4
USB_Address # 4
MEM_Address # 4
RTC_Address # 4
TimerPeriods # 4*2
VIDX_Size # 4
VID_BPP # 4
IOCRSoftCopy # 1
IOSystemType # 1
IOST_7500 * 1
# 2
; workspace for video functions
;
VRAMWidth # 1
# 3
VIDC_NextPaletteIndex # 4 ; last index used in setting normal palette entry
VIDC_SoftPalette0 # 4 ; soft copy of BBGGRRSS for normal palette entry 0
; (used to support ReadPaletteEntry)
VIDC_Interlace # 4 ; flag from VIDCList3 SyncPol word
VIDC_VertiDisplaySize # 4 ; we keep this for vertical pointer clipping
VIDC_PointerVAdjust # 4 ; vertical adjust for pointer
VIDC_PointerHAdjust # 4 ; horizontal adjust for pointer
VIDC_ExternalSoftCopy # 4
VIDC_FSynSoftCopy # 4
VIDC_ControlSoftCopy # 4
VIDC_HSWRSoftCopy # 4 ; horizontal sync width
VIDC_VSWRSoftCopy # 4 ; vertical sync width
IOMD_VInitSoftCopy # 4
IOMD_VEndSoftCopy # 4
;
HAL_WsSize * :INDEX:@
END
hdr/Video 0 → 100644
View file @ 7d4000d9
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; -----------------------------------------------------------------------------------
;
;VIDC20 parameters size (for table of VIDC20 registers)
;
VIDC20ParmsSize * (128*4) ; 128 words from 80xxxxxx to FFxxxxxx step 01000000
;
; VRAM SAM length in bytes
;
SAMLength * 512*4
; -----------------------------------------------------------------------------------
;
; VIDC20 Registers
;
VIDCPalAddress * &10000000 ; used in palette programming
LCDOffsetRegister0 * &30000000
LCDOffsetRegister1 * &31000000
VIDC20BorderColour * &40000000 ; added by mjs
VIDC20PointerColour * &50000000 ; added by mjs
HorizCycle * &80000000
HorizSyncWidth * &81000000
HorizBorderStart * &82000000
HorizDisplayStart * &83000000
HorizDisplayEnd * &84000000
HorizBorderEnd * &85000000
HorizCursorStart * &86000000 ; used in pointer programming
HorizInterlace * &87000000
VertiCycle * &90000000
VertiSyncWidth * &91000000 ; Needed to set up FSIZE register in IOMD
VertiBorderStart * &92000000 ; First register affected by *TV
VertiDisplayStart * &93000000
VertiDisplayEnd * &94000000
VertiBorderEnd * &95000000
VertiCursorStart * &96000000
VertiCursorEnd * &97000000 ; Last register affected by *TV
VIDCExternal * &C0000000
VIDCFSyn * &D0000000
VIDCControl * &E0000000
VIDCDataControl * &F0000000
; Pseudo-registers used to return additional information to kernel
PseudoRegisters * 5 ; number of pseudo-register entries at end of table
PseudoRegister_HClockSpeed * &FB000000 ; used to indicate VIDC hclock speed (and use it)
PseudoRegister_ClockSpeed * &FC000000 ; used to indicate real VIDC rclock speed
; Bits in VCSR, VCER
CursorSinglePanel * 0 :SHL: 13
CursorTopPanel * 1 :SHL: 13
CursorBottomPanel * 1 :SHL: 14
CursorStraddle * 3 :SHL: 13
; Bits in external register
Ext_HSYNCbits * 3 :SHL: 16
Ext_InvertHSYNC * 1 :SHL: 16
Ext_CompHSYNC * 2 :SHL: 16
Ext_InvertCompHSYNC * 3 :SHL: 16
Ext_VSYNCbits * 3 :SHL: 18
Ext_InvertVSYNC * 1 :SHL: 18
Ext_CompVSYNC * 2 :SHL: 18
Ext_InvertCompVSYNC * 3 :SHL: 18
Ext_HiResMono * 1 :SHL: 14
Ext_LCDGrey * 1 :SHL: 13
Ext_DACsOn * 1 :SHL: 12
Ext_PedsOn * 7 :SHL: 8
Ext_PedsShift * 8
Ext_ERegShift * 4
Ext_ECKOn * 1 :SHL: 2
Ext_ERegBits * 3 :SHL: 0
Ext_ERegRed * 0 :SHL: 0
Ext_ERegGreen * 1 :SHL: 0
Ext_ERegBlue * 2 :SHL: 0
Ext_ERegExt * 3 :SHL: 0 ; use this for lowest power
; Bits in Frequency Synthesizer Register
FSyn_VShift * 8
FSyn_RShift * 0
FSyn_ClearV * 1 :SHL: 15
FSyn_ForceLow * 1 :SHL: 14
FSyn_ClearR * 1 :SHL: 7
FSyn_ForceHigh * 1 :SHL: 6
FSyn_ResetValue * FSyn_ClearV :OR: FSyn_ClearR :OR: FSyn_ForceLow :OR: (63 :SHL: FSyn_RShift) :OR: (0 :SHL: FSyn_VShift) ; value to get PLL working properly
; Bits in Control Register
CR_DualPanel * 1 :SHL: 13
CR_Interlace * 1 :SHL: 12
CR_FIFOLoadShift * 8
CR_LBPP0 * 0 :SHL: 5
CR_LBPP1 * 1 :SHL: 5
CR_LBPP2 * 2 :SHL: 5
CR_LBPP3 * 3 :SHL: 5
CR_LBPP4 * 4 :SHL: 5
CR_LBPP5 * 6 :SHL: 5 ; spot the gap!
CR_PixelDivShift * 2
CR_VCLK * 0 :SHL: 0
CR_HCLK * 1 :SHL: 0
CR_RCLK * 2 :SHL: 0
; Bits in Data Control Register
DCR_VRAMOff * 0 :SHL: 18
DCR_VRAMDiv1 * 1 :SHL: 18
DCR_VRAMDiv2 * 2 :SHL: 18
DCR_VRAMDiv4 * 3 :SHL: 18
DCR_BusBits * 3 :SHL: 16
DCR_Bus31_0 * 1 :SHL: 16
DCR_Bus63_32 * 2 :SHL: 16
DCR_Bus63_0 * 3 :SHL: 16
DCR_HDis * 1 :SHL: 13
DCR_Sync * 1 :SHL: 12
DCR_HDWRShift * 0
; -----------------------------------------------------------------------------------
; mjs - this had better agree with the format specified in kernel s.vdu.vdumodes
;
; format of a VIDC list type 3
;
^ 4
VIDCList3_PixelDepth # 4
VIDCList3_HorizSyncWidth # 4
VIDCList3_HorizBackPorch # 4
VIDCList3_HorizLeftBorder # 4
VIDCList3_HorizDisplaySize # 4
VIDCList3_HorizRightBorder # 4
VIDCList3_HorizFrontPorch # 4
VIDCList3_VertiSyncWidth # 4
VIDCList3_VertiBackPorch # 4
VIDCList3_VertiTopBorder # 4
VIDCList3_VertiDisplaySize # 4
VIDCList3_VertiBottomBorder # 4
VIDCList3_VertiFrontPorch # 4
VIDCList3_PixelRate # 4
VIDCList3_SyncPol # 4 ; sync polarity/flag bits
VIDCList3_ControlList # 0 ; possibly empty list of pairs of index,value words
;
; and VIDCList3 is terminated by a -1 word
;
; Indices in VIDCList3_ControlList
;
^ 1
ControlList_LCDMode # 1
ControlList_LCDDualPanelMode # 1
ControlList_LCDOffset0 # 1
ControlList_LCDOffset1 # 1
ControlList_HiResMode # 1
ControlList_DACControl # 1
ControlList_RGBPedestals # 1
ControlList_ExternalRegister # 1
ControlList_HClockSelect # 1
ControlList_RClockFrequency # 1
ControlList_DPMSState # 1
ControlList_Interlaced # 1
ControlList_InvalidReason # 0
; bits/flags in VIDCList3_SyncPol word:
;
SyncPol_InvertHSync * 1
SyncPol_InvertVSync * 2
SyncPol_InterlaceSpecified * 4 ; if set, interlace bit has been specified, else filled in by kernel
SyncPol_Interlace * 8 ; set=interlaced, either specified by service call claimant or filled in from *TV by kernel
; -----------------------------------------------------------------------------------
END
s/Boot 0 → 100644
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s/IIC 0 → 100644
View file @ 7d4000d9
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:Machine.<Machine>
GET Hdr:ImageSize.<ImageSize>
$GetIO
GET Hdr:OSEntries
GET Hdr:HALEntries
GET hdr.StaticWS
EXPORT HAL_IICBuses
EXPORT HAL_IICType
EXPORT HAL_IICSetLines
EXPORT HAL_IICReadLines
AREA |Asm$$Code|, CODE, READONLY, PIC
HAL_IICBuses
MOV a1, #1
MOV pc, lr
HAL_IICType
MOV a1, #IICFlag_LowLevel
[ MaxI2Cspeed >= 400
ORR a1, a1, #IICFlag_Fast
]
MOV pc, lr
; In: a1 = bus number, a2 = SDA, a3 = SCL
; Out: a1 = SDA, a2 = SCL
HAL_IICSetLines
LDRB ip, IOCRSoftCopy
LDR a4, IOMD_Address
ADD a2, a2, a3, LSL #1 ; bit 1 = SCL, bit 0 = SDA
BIC ip, ip, #3
ORR ip, ip, a2
STRB ip, IOCRSoftCopy
STRB ip, [a4, #IOCControl]
10 LDRB a1, [a4, #IOCControl]
MOV a2, a1, LSR #1
AND a1, a1, #1
AND a2, a2, #1
MOV pc, lr
HAL_IICReadLines
LDR a4, IOMD_Address
B %BT10
END
s/Interrupts 0 → 100644
View file @ 7d4000d9
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:Machine.<Machine>
GET Hdr:ImageSize.<ImageSize>
$GetIO
GET Hdr:DevNos
GET Hdr:OSEntries
GET Hdr:HALEntries
GET hdr.StaticWS
AREA |Asm32$$Code|, CODE, READONLY, PIC, ALIGN=5
NoInterrupt * 38
EXPORT HAL_IRQSource
EXPORT HAL_IRQEnable
EXPORT HAL_IRQDisable
EXPORT HAL_IRQClear
EXPORT HAL_IRQStatus
; EXPORT HAL_FIQSource
; EXPORT HAL_FIQEnable
; EXPORT HAL_FIQDisable
; EXPORT HAL_FIQDisableAll
; EXPORT HAL_FIQClear
; EXPORT HAL_FIQStatus
IMPORT serial2
IMPORT serials
IMPORT serialn
IMPORT serial8
HAL_IRQSource
;STMDB sp!,{r0-r5,lr}
;LDR r0, UART_Address
;ADR r4, IRQSR2_txt
;BL serials
;LDMIA sp!,{r0-r5,lr}
LDR r3, INT_Address
LDR r0, [r3,#0xF00]
CMP r0, #0
ADDEQ r3, r3, #0x100000
LDREQ r0, [r3,#0xF00]
;STMDB sp!,{r0-r5,lr}
;MOV r4,r0
;LDR r0, UART_Address
;BL serial8
;LDMIA sp!,{r0-r5,lr}
; LDR r1, [r3]
;
; MOV r0, #31
; MOV r2, #1
;irqlp CMP r0, #-1
; BEQ noirq
; TST r1, r2, LSL r0
; SUBEQ r0,r0,#1
; BEQ irqlp
;
;noirq
;STMDB sp!,{r0-r5,lr}
;STMDB sp!,{r0}
;LDR r0, UART_Address
;ADR r4, IRQSR_txt
;;BL serials
;;LDMIA sp!,{r4}
;BL serial8
;LDMIA sp!,{r0-r5,pc}
MOV pc,lr
;HAL_FIQSource
; LDR r3, IOMD_Address
; LDRB r0, [r3, #IOCFIQREQ]
; ORR r0, r0, r0, LSR #4
; ORR r0, r0, r0, LSR #2
; ORR r0, r0, r0, LSR #1
; ADD r0, r0, #1 ; r0 = 2, 4, 8, 16, 32, 64, 128 or 256
; MOV r1, #&0E800000
; MUL r0, r1, r0 ; r0>>29 = 0, 1, 3, 7, 6, 5, 2 or 4
; LDRB r0, [pc, r0, LSR #29]
; MOV pc, lr
; DCB 0, 1, 6, 2, 7, 5, 4, 3
;HAL_FIQEnable
; LDR a4, IOMD_Address
; MOV ip, #1
; MRS a3, CPSR
; MOV ip, ip, LSL a1
; ORR a2, a3, #F32_bit+I32_bit
; MSR CPSR_c, a2
; LDRB a1, [a4, #IOCFIQMSK]
; ORR a2, a1, ip
; STRB a2, [a4, #IOCFIQMSK]
; MSR CPSR_c, a3
; AND a1, a1, ip
; MOV pc, lr
;HAL_FIQDisable
; LDR a4, IOMD_Address
; MOV ip, #1
; MRS a3, CPSR
; MOV ip, ip, LSL a1
; ORR a2, a3, #F32_bit+I32_bit
; MSR CPSR_c, a2
; LDRB a1, [a4, #IOCFIQMSK]
; BIC a2, a1, ip
; STRB a2, [a4, #IOCFIQMSK]
; MSR CPSR_c, a3
; AND a1, a1, ip
; MOV pc, lr
;
;HAL_FIQDisableAll
; LDR a4, IOMD_Address
; MOV a1, #0
; STRB a1, [a4, #IOCFIQMSK]
; MOV pc, lr
;
;HAL_FIQClear
; MOV pc, lr
;
;HAL_FIQStatus
; LDR a4, IOMD_Address
; MOV ip, #1
; LDRB a2, [a4, #IOCFIQSTA]
; AND a1, a2, ip, LSL a1
; MOV pc, lr
IRQSR2_txt = "Getting IRQ source"
= 10,13,0
IRQEN_txt = "IRQ enable = "
= 0
IRQDS_txt = "IRQ disable = "
= 0
IRQCL_txt = "IRQ clear = "
= 0
IRQSR_txt = "IRQ source = "
= 0
ALIGN
HAL_IRQEnable
STMDB sp!,{lr}
; CMP a1, #16
; LDMEQIA sp!,{pc}
; STMDB sp!,{r0-r5}
; MOV r4,a1
; LDR r0, UART_Address
; MOV r4,a1
; BL serial8
; LDMIA sp!,{r0-r5}
STMDB sp!,{r0-r5}
LDR a2, INT_Address
TST a1, #32
ANDNE a1, a1, #31
ADDNE a2, a2, #0x100000
MOV a4, #1
MOV a1, a4, LSL a1
;LDR a3, [a2,#8]
;BIC a3, a3, a1
STR a1, [a2,#0x10]
;STMDB sp!,{a2}
STMDB sp!,{r0-r5}
STMDB sp!,{a2}
STMDB sp!,{a1}
LDR r0, UART_Address
ADR r4, IRQEN_txt
BL serials
LDMIA sp!,{r4}
BL serial8
LDMIA sp!,{r4}
BL serial8
LDMIA sp!,{r0-r5}
;LDMIA sp!,{a2}
;STMDB sp!,{r0-r5}
;LDR r0, UART_Address
;MOV r4,a2
;BL serial8
;LDMIA sp!,{r0-r5}
LDMIA sp!,{r0-r5}
LDMIA sp!,{pc}
MOV pc,lr
HAL_IRQDisable
;STMDB sp!,{lr}
;STMDB sp!,{r0-r5}
LDR a2, INT_Address
TST a1, #32
ANDNE a1, a1, #31
ADDNE a2, a2, #0x100000
MOV a4, #1
MOV a1, a4, LSL a1
; LDR a3, [a2,#8]
; ORR a3, a3, a1
STR a1, [a2,#0x14]
;STMDB sp!,{r0-r5}
;STMDB sp!,{a1}
;LDR r0, UART_Address
;ADR r4, IRQDS_txt
;BL serials
;LDMIA sp!,{r4}
;BL serial8
;LDMIA sp!,{r0-r5}
;LDMIA sp!,{r0-r5}
;LDMIA sp!,{pc}
MOV pc,lr
HAL_IRQClear
; STMDB sp!,{lr}
STMDB sp!,{r0-r12,lr}
; CMP a1, #16
; MOVEQ a4, #3
; LDRQ a2, LCD_Address
; STR
; STREQ a4, [a2, #0x54]
; STREQ a4, [a2, #0x58]
; MOV a4, #1
; MOV a1, a4, LSL a1
CMP a1,#0x1C
LDREQ a2,Timer_Address
LDREQ a3,[a2,#0x44]
ORREQ a3,a3,#0x200
STREQ a3,[a2,#0x44]
LDR a2, INT_Address
;TST a1, #32
;ANDNE a1, a1, #31
;ADDNE a2, a2, #0x100000
STR a1, [a2,#0xF00]
ADD a2, a2, #0x100000
STR a1, [a2,#0xF00]
; STR a1, [a2, #0x10]
; MOV r4,a1
;; LDR r0, UART_Address
; BL serial8
;STMDB sp!,{r0-r5}
;STMDB sp!,{a1}
;ADR r0, UART_Address
;ADR r4, IRQCL_txt
;BL serials
;LDMIA sp!,{r4}
;BL serial8
;LDMIA sp!,{r0-r5}
LDMIA sp!,{r0-r12,lr}
; LDMIA sp!,{pc}
MOV pc, lr
HAL_IRQStatus
; MOV a1,#1
;STMDB sp!,{lr}
;STMDB sp!,{r0-r5}
;STMDB sp!,{a1}
;LDR r0, UART_Address
;ADR r4, IRQST_txt
;BL serials
;LDMIA sp!,{r4}
;BL serial8
;LDMIA sp!,{r0-r5}
MOV a1, #1
MOV a4, #1
MOV a1, a4, LSL a1
LDR a2, INT_Address
LDR a3, [a2]
AND a1, a3, a4
;LDMIA sp!,{pc}
MOV pc, lr
IRQST_txt = "IRQ status = "
= 0
ALIGN
END
s/MachineID 0 → 100644
View file @ 7d4000d9
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:Machine.<Machine>
GET Hdr:ImageSize.<ImageSize>
$GetIO
GET Hdr:Proc
GET Hdr:OSEntries
GET Hdr:HALEntries
GET hdr.StaticWS
AREA |Asm$$Code|, CODE, READONLY, PIC
EXPORT HAL_MachineID
IMPORT HAL_TimerPeriod
IMPORT HAL_TimerSetPeriod
; +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; ReadUniqueID - Read unique machine ID
;
; 10-Dec-93 BCockburn Modified to leave raw 64 bit ID from chip in RawMachineID
defaultlatch * 20000-1 ; TMD 21-May-93: "-1" correction applied
Tsyc * 5 ; time between frames - minimum of 1s, so give it a bit more
Trstl * 500 ; time reset pulse held low - minimum of 480s, so give it a bit more
Trsth * 500 ; time reset pulse held high - minimum of 480s, so give it a bit more
Tlow0 * 80 ; time for write0 low - min 60s, max 120s
Tlow1 * 5 ; time for write1 low - min 1s, max 15s
Tslot * 90 ; time for total read/write slot - min 60s, max 120s
Trdlow * 5 ; time for read slot low before release - min 1s, max 15s
Trddat * 3 ; time after read slot high before read it
ASSERT Tslot-Tlow0 > Tsyc
ASSERT Trdlow+Trddat < 15
; Macro to set wire to a given state, and optionally count transitions (starting at low) while waiting for a given time
MACRO
SetWire $hilo, $time, $monstate, $count
LCLS reg
[ "$hilo"="LOW"
reg SETS "r4"
|
ASSERT "$hilo"="HIGH"
reg SETS "r5"
]
[ ($time) = 0
STRB $reg, [r1, #IOCControl] ; set appropriate level on line
|
ASSERT ($time) < 32768
MOV r12, #(($time)*2):AND:&FF
STRB r12, [r1, #Timer0LL] ; program low latch
MOV r12, #(($time)*2):SHR:8
STRB r12, [r1, #Timer0LH] ; program high latch
STRB $reg, [r1, #IOCControl] ; set appropriate level on line
STRB r12, [r1, #Timer0GO] ; and start timer
LDRB r12, [r1, #IOCIRQSTAA] ; dummy instruction to avoid bug in IOC
LDRB r12, [r1, #IOCIRQSTAA] ; dummy instruction (repeated for FE)
STRB r11, [r1, #IOCIRQCLRA] ; immediately clear IRQ bit
[ "$monstate"<>""
MOV $monstate, #0
]
[ "$count"<>""
MOV $count, #0
]
10
LDRB r12, [r1, #IOCIRQSTAA]
TST r12, r11
[ "$count"<>""
ADDEQ $count, $count, #1
]
[ "$monstate"=""
BEQ %BT10 ; not timed out, so just loop
|
BNE %FT30 ; timed out
LDRB r12, [r1, #IOCControl]
TST r12, #IOEB_unique_machine_ID_bit
BEQ %BT10 ; if still low then loop to 10
ADD $monstate, $monstate, #1 ; increment number of transitions
20
LDRB r12, [r1, #IOCIRQSTAA]
TST r12, r11
[ "$count"<>""
ADDEQ $count, $count, #1
]
BNE %FT30 ; timed out
LDRB r12, [r1, #IOCControl]
TST r12, #IOEB_unique_machine_ID_bit
BNE %BT20 ; if still high then loop to 20
ADD $monstate, $monstate, #1 ; increment number of transitions
B %BT10
30
]
]
MEND
HAL_MachineID
Entry "r4-r11",8
MOV r0, #0
LDR r1, IOMD_Address
MRS r8, CPSR ; remember PSR in r8
ORR r3, r8, #I32_bit+F32_bit
MSR CPSR_c, r3 ; FIQs and IRQs off
LDRB r3, IOCRSoftCopy
BIC r4, r3, #IOEB_unique_machine_ID_bit ; r4 is value to pull ID line low
ORR r5, r3, #IOEB_unique_machine_ID_bit ; r5 is value to pull ID line high
MOV r11, #timer0_bit
BL SendResetPulse
BVS ResetFailed
BL SendCommandWord
MOV r7, #0 ; no. of bytes to store = 8 bits type + 48 bits ID + 8 bits checksum
10
BL GetAByte
STRB r6, [sp, r7]
ADD r7, r7, #1
CMP r7, #8
BNE %BT10
BL RestoreIOCState
MOV r1, sp
BL CheckCRC
BVS IDError
LDMIA sp, {r0, r1}
EXIT
ResetFailed
BL RestoreIOCState
IDError
MOV r0, #0
MOV r1, #0 ; indicate no ID by putting zero here
EXIT
RestoreIOCState Entry
STRB r3, [r1, #IOCControl] ; put back old value
MOV r0, #0
BL HAL_TimerPeriod
MOV r1, r0
MOV r0, #0
BL HAL_TimerSetPeriod
MSR CPSR_c, r8 ; restore old interrupt state
EXIT
SendResetPulse ROUT
SetWire HIGH, Tsyc
SetWire LOW, Trstl,,r6
SetWire HIGH, Trsth,r10
TEQ r6, #0
; ADREQ r0, IOCBugHappenedError
BEQ %FT05
CMP r10, #3 ; H-L-H is ok
MOVEQ pc, lr ; V clear
; ADRHI r0, TooManyTransitionsError ; H-L-H-L...
; CMP r10, #2
; ADREQ r0, NeverWentHighAgainError ; H-L
; CMP r10, #1
; ADREQ r0, NeverWentLowError ; H
; ADRCC r0, NeverWentHighError ; stayed low permanently even though we released it
05
SETV
MOV pc, lr
[ {FALSE} ; only for debugging
NeverWentHighError
= "Never went high", 0
NeverWentLowError
= "Never went low", 0
NeverWentHighAgainError
= "Never went high again", 0
TooManyTransitionsError
= "Too many transitions", 0
IOCBugHappenedError
= "IOC bug happened", 0
ALIGN
]
SendCommandWord ROUT
CLRV
LDR r6, =&10F ; &0F is command word
10
MOVS r6, r6, LSR #1
MOVEQ pc, lr
BCS SendOne
SetWire LOW, Tlow0
SetWire HIGH, Tslot-Tlow0
B %BT10
SendOne
SetWire LOW, Tlow1
SetWire HIGH, Tslot-Tlow1
B %BT10
GetAByte ROUT
MOV r6, #&80
10
SetWire LOW, Trdlow
SetWire HIGH, Trddat
LDRB r10, [r1, #IOCControl]
SetWire HIGH, Tslot-Trdlow-Trddat
MOVS r10, r10, LSR #IOEB_ID_bit_number+1 ; move bit into carry
MOVS r6, r6, RRX
BCC %BT10
MOV r6, r6, LSR #24
MOV pc, lr
CheckCRC ROUT
MOV r2, #0
MOV r3, #7 ; number of bytes to do
10
LDRB r4, [r1], #1
EOR r2, r2, r4
MOV r4, #8 ; number of bits to do
20
MOVS r2, r2, LSR #1 ; shift bit out into carry
EORCS r2, r2, #&8C ; feedback carry into other bits
SUBS r4, r4, #1 ; one less bit to do
BNE %BT20 ; loop until done whole byte
SUBS r3, r3, #1 ; one less byte to do
BNE %BT10 ; loop until done all 7 bytes
LDRB r4, [r1], #1 ; read CRC
CMP r4, r2 ; if correct
MOVEQ pc, lr ; exit (V clear)
RETURNVS ; else exit indicating error
END
s/NVRAM 0 → 100644
View file @ 7d4000d9
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:Machine.<Machine>
GET Hdr:ImageSize.<ImageSize>
$GetIO
GET Hdr:OSEntries
GET Hdr:HALEntries
GET hdr.StaticWS
EXPORT HAL_NVMemoryType
EXPORT HAL_NVMemorySize
EXPORT HAL_NVMemoryPageSize
EXPORT HAL_NVMemoryProtectedSize
EXPORT HAL_NVMemoryProtection
EXPORT HAL_NVMemoryIICAddress
EXPORT HAL_NVMemoryRead
EXPORT HAL_NVMemoryWrite
AREA |Asm$$Code|, CODE, READONLY, PIC
HAL_NVMemoryType
LDR R0, =NVMemoryFlag_IIC :OR: NVMemoryFlag_ProtectAtEnd
MOV pc, lr
HAL_NVMemorySize
MOV R0, #256
MOV pc, lr
HAL_NVMemoryPageSize
MOV R0, #16
MOV pc, lr
HAL_NVMemoryProtectedSize
MOV R0, #0
MOV pc, lr
; in: r0 = 0/1 to unprotect/protect
HAL_NVMemoryProtection
MOV pc, lr
HAL_NVMemoryIICAddress
MOV R0, #&a0
MOV pc, lr
HAL_NVMemoryRead
MOV pc, lr
HAL_NVMemoryWrite
MOV pc, lr
END
s/RTC 0 → 100644
View file @ 7d4000d9
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:Machine.<Machine>
GET Hdr:ImageSize.<ImageSize>
$GetIO
GET Hdr:OSEntries
GET Hdr:HALEntries
GET Hdr:HALDevice
GET Hdr:RTCDevice
GET hdr.StaticWS
AREA |Asm$$Code|, CODE, READONLY, PIC
EXPORT RTC_Init
IMPORT serial8
; Note - debug stuff won't work since we don't get passed a HAL workspace pointer!
; IMPORT DebugHALPrint
; IMPORT DebugHALPrintReg
; IMPORT DebugMemDump
; IMPORT DebugHALPrintByte
; TWL/TPS RTC IIC address
TPSRTC_IIC * &4b
; Some RTC registers
SECONDS_REG * &1C
RTC_CTRL_REG * &29
RTC_STATUS_REG * &2a
MACRO
CallOS $entry, $tailcall
ASSERT $entry <= HighestOSEntry
[ "$tailcall"=""
MOV lr, pc
|
[ "$tailcall"<>"tailcall"
! 0, "Unrecognised parameter to CallOS"
]
]
LDR pc, OSentries + 4*$entry
MEND
RTC_Init
STMDB sp!,{lr}
MOV r0, #0xF9000000
ORR r0, r0, #0xF00000
ADR r1, RTCDevice
LDR r4, [r1, #HALDevice_Activate]
BL serial8
LDMIA sp!,{lr}
; Just register our HAL Device with the OS
MOV a1, #0
ADR a2, RTCDevice
CallOS OS_AddDevice, tailcall
RTCDevice
DCW HALDeviceType_SysPeri + HALDeviceSysPeri_RTC
DCW HALDeviceID_RTC_TPS65950
DCD HALDeviceBus_Pro
DCD 0 ; API version
DCD RTCDesc
DCD 0 ; Address - N/A
% 12 ; Reserved
DCD RTCActivate
DCD RTCDeactivate
DCD RTCReset
DCD RTCSleep
DCD -1 ; Interrupt N/A
DCD 0
% 8
DCB RTCTimeFormat_BCD
DCB RTCFormatFlags_BCD_YearLOIsGood ; todo - add RTCFormatFlags_BCD_NeedsYearHelp once NVRAM is implemented
% 2
DCD RTCReadTime
DCD RTCWriteTime
RTCDesc
DCB "S3C6410 real-time clock",0
ALIGN
RTCActivate
MOV a1, #1
RTCDeactivate
RTCReset
MOV pc, lr
RTCSleep
MOV a1, #0 ; Previously at full power
MOV pc, lr
RTCReadTime
; In:
; a1 = HALDevice ptr
; a2 = RTCTimeStruct ptr
; a3 = IICOp func ptr
; a4 = kernel workspace ptr
; Out:
; a1 = return code
; RTCTimeStruct updated
Push "v1-v3,lr"
MOV v1, a3
MOV v2, a4
MOV v3, a2
STMDB sp!, {r2-r12}
MOV r0, #13
ORR r0,r0,#&20000
ORR r0,r0,#&3C0000
MOV r1,#&57000000
MOV r2,#&100000
SWI 0x68
MOV a1, r3
LDMIA sp!, {r2-r12}
;LDR a1, RTC_Address
LDRB a2, [a1, #0x70]
STRB a2, [v3, #RTCTimeStruct_BCD_Seconds]
LDRB a2, [a1, #0x74]
STRB a2, [v3, #RTCTimeStruct_BCD_Minutes]
LDRB a2, [a1, #0x78]
STRB a2, [v3, #RTCTimeStruct_BCD_Hours]
LDRB a2, [a1, #0x7C]
STRB a2, [v3, #RTCTimeStruct_BCD_DayOfMonth]
LDRB a2, [a1, #0x84]
STRB a2, [v3, #RTCTimeStruct_BCD_Month]
LDRB a2, [a1, #0x88]
STRB a2, [v3, #RTCTimeStruct_BCD_YearLO]
MOV a2, #0
STRB a2, [v3, #RTCTimeStruct_BCD_Centiseconds]
; Construct a fakey YearHI by looking at YearLO
; Anything 70 or above is considered 1970+, else 2000+
; This should work OK, since RISC OS clamps the time to 1970 for unix compatability (or it does on boot, at least)
LDRB a2, [v3, #RTCTimeStruct_BCD_YearLO]
CMP a2, #&70
MOVGE a3, #&19
MOVLT a3, #&20
STRB a3, [v3, #RTCTimeStruct_BCD_YearHI]
MOV a1, #0
ASSERT RTCRetCode_OK = 0
Pull "v1-v3,pc"
RTCWriteTime
; In:
; a1 = HALDevice ptr
; a2 = RTCTimeStruct ptr
; a3 = IICOp func ptr
; a4 = kernel workspace ptr
; Out:
; a1 = return code
Push "v1-v3,lr"
MOV v1, a3
MOV v2, a4
MOV v3, a2
; Writing the time safely involves several transfers:
; 1. Write 0 to RTC_CTRL_REG to stop the clock (just in case there are any issues with the clock updating while it's being written to)
; 2. Write the new time values
; 3. Write 1 to RTC_CTRL_REG to start the clock
STMDB sp!, {r2-r12}
MOV r0, #13
ORR r0,r0,#&20000
ORR r0,r0,#&3C0000
MOV r1,#&57000000
MOV r2,#&100000
SWI 0x68
MOV a1, r3
LDMIA sp!, {r2-r12}
; LDR a1, RTC_Address
LDRB a2, [v3, #RTCTimeStruct_BCD_Seconds]
STRB a2, [a1, #0x70]
LDRB a2, [v3, #RTCTimeStruct_BCD_Minutes]
STRB a2, [a1, #0x74]
LDRB a2, [v3, #RTCTimeStruct_BCD_Hours]
STRB a2, [a1, #0x78]
LDRB a2, [v3, #RTCTimeStruct_BCD_DayOfMonth]
STRB a2, [a1, #0x7C]
LDRB a2, [v3, #RTCTimeStruct_BCD_Month]
STRB a2, [a1, #0x84]
LDRB a2, [v3, #RTCTimeStruct_BCD_YearLO]
STRB a2, [a1, #0x88]
Pull "v1-v3,pc"
END
s/Timers 0 → 100644
View file @ 7d4000d9
; Copyright 2011 Castle Technology Ltd
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
GET Hdr:ListOpts
GET Hdr:Macros
GET Hdr:System
GET Hdr:Machine.<Machine>
GET Hdr:ImageSize.<ImageSize>
$GetIO
GET Hdr:OSEntries
GET Hdr:HALEntries
GET hdr.StaticWS
AREA |Asm$$Code|, CODE, READONLY, PIC
EXPORT HAL_Timers
EXPORT HAL_TimerDevice
EXPORT HAL_TimerGranularity
EXPORT HAL_TimerMaxPeriod
EXPORT HAL_TimerSetPeriod
EXPORT HAL_TimerPeriod
EXPORT HAL_TimerReadCountdown
EXPORT HAL_CounterRate
EXPORT HAL_CounterPeriod
EXPORT HAL_CounterRead
EXPORT HAL_CounterDelay
EXPORT HAL_VideoFlybackDevice
IMPORT serials
IMPORT serial8
HAL_Timers
MOV a1, #1 ; 1 timer
MOV pc, lr
HAL_TimerDevice
ADD a1, a1, #28 ; device 14
MOV pc, lr
HAL_VideoFlybackDevice
MOV a1, #-1
MOV pc, lr
HAL_CounterRate
HAL_TimerGranularity
LDR a1, =4000000 ; 4MHz
MOV pc, lr
HAL_TimerMaxPeriod
MOV a1, #&10000 ; 16-bit counter
MOV pc, lr
TSet_txt = "Timer set = "
= 0
ALIGN
HAL_TimerSetPeriod
LDR a3, Timer_Address
STR a2, [a3, #0x3C]
ADR a4, TimerPeriods
STR a2, [a4, a1, LSL #2]
STMDB sp!,{r0-r5,lr}
STMDB sp!,{a2}
LDR r0, UART_Address
ADR r4, TSet_txt
BL serials
LDMIA sp!,{r4}
BL serial8
LDMIA sp!,{r0-r5,pc}
;MOV pc, lr
HAL_TimerPeriod
ADR a4, TimerPeriods
LDR a1, [a4, a1, LSL #2]
MOV pc, lr
HAL_CounterRead
MOV a1, #0
; Fall through
HAL_TimerReadCountdown
LDR a4, Timer_Address
LDR a1, [a4, #0x40]
MOV pc, lr
HAL_CounterPeriod
LDR a1, TimerPeriods + 0
MOV pc, lr
; If they want n ticks, wait until we've seen n+1 transitions of the clock.
HAL_CounterDelay
MOV pc, lr
END
s/Video 0 → 100644
View file @ 7d4000d9
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